Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	109045	1			T21	6		T13	20		T16	4
class_i[0x1]	50749	1			T21	36		T18	328		T42	89
class_i[0x2]	55229	1			T1	8		T16	1		T18	453
class_i[0x3]	49319	1			T21	2		T16	4		T42	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	67145	1			T1	7		T21	17		T13	11
alert[0x1]	67787	1			T1	1		T21	6		T13	1
alert[0x2]	64939	1			T21	6		T13	8		T18	955
alert[0x3]	64471	1			T21	15		T16	1		T18	583

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

264085

1

T1

8

T21

44

T13

20

esc_ping_fail

257

1

T5

6

T7

4

T8

9

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	67079	1			T1	7		T21	17		T13	11
esc_integrity_fail	alert[0x1]	67715	1			T1	1		T21	6		T13	1
esc_integrity_fail	alert[0x2]	64883	1			T21	6		T13	8		T18	955
esc_integrity_fail	alert[0x3]	64408	1			T21	15		T16	1		T18	583
esc_ping_fail	alert[0x0]	66	1			T5	2		T7	2		T8	4
esc_ping_fail	alert[0x1]	72	1			T5	2		T8	1		T65	1
esc_ping_fail	alert[0x2]	56	1			T5	1		T7	2		T8	2
esc_ping_fail	alert[0x3]	63	1			T5	1		T8	2		T98	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	108995	1			T21	6		T13	20		T16	4
esc_integrity_fail	class_i[0x1]	50683	1			T21	36		T18	328		T42	89
esc_integrity_fail	class_i[0x2]	55146	1			T1	8		T16	1		T18	453
esc_integrity_fail	class_i[0x3]	49261	1			T21	2		T16	4		T42	1
esc_ping_fail	class_i[0x0]	50	1			T7	2		T8	1		T65	2
esc_ping_fail	class_i[0x1]	66	1			T5	6		T7	1		T335	2
esc_ping_fail	class_i[0x2]	83	1			T7	1		T335	1		T72	5
esc_ping_fail	class_i[0x3]	58	1			T8	8		T28	1		T72	1