Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	682582373	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	682582373	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	682582373	682408176	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	682582373	682408176	0	0
tb.dut.EdnKnownO_A	0	0	682582373	682408176	0	0
tb.dut.EscPKnownO_A	0	0	682582373	682408176	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	682582373	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	682582373	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	682582373	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	682582373	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	682582373	80	0	0
tb.dut.IrqAKnownO_A	0	0	682582373	682408176	0	0
tb.dut.IrqBKnownO_A	0	0	682582373	682408176	0	0
tb.dut.IrqCKnownO_A	0	0	682582373	682408176	0	0
tb.dut.IrqDKnownO_A	0	0	682582373	682408176	0	0
tb.dut.TlAReadyKnownO_A	0	0	682582373	682408176	0	0
tb.dut.TlDValidKnownO_A	0	0	682582373	682408176	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	707163861	3066658	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	707163861	12366	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	707163861	12243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	707163861	11877	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	707163861	11934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	707163861	11936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	707163861	12040	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	707163861	12033	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	707163861	11892	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	707163861	12253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	707163861	12257	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	707163861	11811	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	707163861	12231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	707163861	12075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	707163861	12310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	707163861	12068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	707163861	12058	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	707163861	12141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	707163861	12116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	707163861	12334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	707163861	12041	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	707163861	12263	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	707163861	12357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	707163861	12143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	707163861	12410	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	707163861	12448	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	707163861	12107	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	707163861	12089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	707163861	11864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	707163861	12328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	707163861	12446	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	707163861	11979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	707163861	12646	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	707163861	12197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	707163861	11946	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	707163861	12197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	707163861	11934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	707163861	12021	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	707163861	11917	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	707163861	12405	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	707163861	12048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	707163861	11984	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	707163861	12300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	707163861	12361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	707163861	12123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	707163861	12053	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	707163861	12120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	707163861	12121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	707163861	12153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	707163861	12234	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	707163861	12222	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	707163861	12248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	707163861	11923	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	707163861	12031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	707163861	12188	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	707163861	12199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	707163861	12454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	707163861	12495	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	707163861	12123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	707163861	12358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	707163861	12025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	707163861	12166	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	707163861	12335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	707163861	11959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	707163861	12278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	707163861	12024	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	707163861	12007	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	707163861	12283	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	707163861	12193	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	707163861	12129	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	707163861	22917	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	707163861	12112	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	707163861	12195	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	707163861	11788	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	707163861	12221	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	707163861	12145	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	707163861	12079	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	707163861	12126	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	707163861	12289	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	682582373	3760	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	682582373	251112	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	682582373	343916449	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	682582373	267	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	682582373	921	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	682582373	64	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	682582373	495	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	682339515	258448175	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	682582373	1026	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	682582373	1001	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	682582373	972	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	682582373	949	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	682582373	952	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	682582373	115421	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	682582373	821	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	682582373	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682582373	1476	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	682582373	1236	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	682582373	682408176	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	682582373	4501	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	682582373	197604	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	682582373	390100920	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	682582373	281	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	682582373	510	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	682582373	21	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	682582373	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	682339515	314014669	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	682582373	581	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	682582373	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	682582373	559	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	682582373	552	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	682582373	527	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	682582373	65470	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	682582373	441	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	682582373	64	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682582373	1463	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	682582373	1223	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	682582373	682408176	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	682582373	2639	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	682582373	160992	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	682582373	392391764	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	682582373	297	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	682582373	504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	682582373	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	682582373	232	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	682339515	316324223	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	682582373	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	682582373	571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	682582373	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	682582373	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	682582373	1033	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	682582373	109603	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	682582373	944	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	682582373	63	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682582373	1416	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	682582373	1176	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	682582373	682408176	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	682582373	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	682582373	3576	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	682582373	202604	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	682582373	376745982	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	682582373	263	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	682582373	476	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	682582373	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	682582373	222	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	682339515	294503307	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	682582373	564	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	682582373	555	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	682582373	547	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	682582373	533	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	682582373	825	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	682582373	99193	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	682582373	733	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	682582373	69	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	682582373	1402	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	682582373	1162	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	682582373	682408176	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	707163861	136165528	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	707163861	706471201	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	707163861	706471201	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	707163861	175564166	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	707163861	706471201	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	707163861	706471201	0	0
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