Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	177	1			T16	1		T17	1		T18	2
index[0x1]	178	1			T4	1		T16	1		T17	4
index[0x2]	203	1			T2	1		T20	1		T17	1
index[0x3]	185	1			T13	1		T14	1		T16	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	220	1			T16	1		T17	5		T18	1
lens_less_than_1000[1]	144	1			T20	1		T16	1		T18	1
lens_less_than_1000[2]	108	1			T14	1		T18	2		T46	1
lens_less_than_1000[3]	76	1			T4	1		T16	1		T17	1
lens_less_than_1000[4]	61	1			T17	1		T26	2		T30	1
lens_less_than_1000[5]	46	1			T2	1		T5	1		T27	1
lens_less_than_1000[6]	39	1			T13	1		T48	1		T89	1
lens_less_than_1000[7]	19	1			T5	1		T71	1		T50	1
lens_less_than_1000[8]	15	1			T88	1		T90	1		T92	1
lens_less_than_1000[9]	4	1			T43	1		T198	1		T273	1
len_2	11	1			T17	1		T22	1		T306	3

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	52	1			T16	1		T77	1		T27	1
index[0x0]	lens_less_than_1000[1]	28	1			T18	1		T250	1		T81	1
index[0x0]	lens_less_than_1000[2]	35	1			T18	1		T8	1		T65	1
index[0x0]	lens_less_than_1000[3]	16	1			T17	1		T42	1		T79	1
index[0x0]	lens_less_than_1000[4]	13	1			T29	1		T86	1		T57	1
index[0x0]	lens_less_than_1000[5]	8	1			T277	1		T307	1		T215	1
index[0x0]	lens_less_than_1000[6]	12	1			T308	1		T309	1		T59	1
index[0x0]	lens_less_than_1000[7]	4	1			T5	1		T50	1		T51	1
index[0x0]	lens_less_than_1000[8]	3	1			T90	1		T59	1		T310	1
index[0x0]	lens_less_than_1000[9]	3	1			T43	1		T273	1		T311	1
index[0x0]	len_2	3	1			T306	3		-	-		-	-
index[0x1]	lens_less_than_1000[0]	49	1			T17	3		T45	1		T269	1
index[0x1]	lens_less_than_1000[1]	44	1			T16	1		T224	1		T250	1
index[0x1]	lens_less_than_1000[2]	23	1			T29	1		T312	1		T308	1
index[0x1]	lens_less_than_1000[3]	23	1			T4	1		T18	1		T70	1
index[0x1]	lens_less_than_1000[4]	10	1			T26	2		T313	1		T106	1
index[0x1]	lens_less_than_1000[5]	8	1			T5	1		T197	1		T96	1
index[0x1]	lens_less_than_1000[6]	7	1			T314	1		T61	1		T315	1
index[0x1]	lens_less_than_1000[7]	6	1			T286	2		T106	1		T112	1
index[0x1]	lens_less_than_1000[8]	2	1			T316	2		-	-		-	-
index[0x1]	lens_less_than_1000[9]	1	1			T198	1		-	-		-	-
index[0x1]	len_2	5	1			T17	1		T22	1		T317	1
index[0x2]	lens_less_than_1000[0]	66	1			T44	1		T67	1		T77	1
index[0x2]	lens_less_than_1000[1]	46	1			T20	1		T94	1		T84	2
index[0x2]	lens_less_than_1000[2]	18	1			T29	1		T52	1		T318	1
index[0x2]	lens_less_than_1000[3]	14	1			T6	1		T93	1		T29	1
index[0x2]	lens_less_than_1000[4]	23	1			T17	1		T319	11		T97	1
index[0x2]	lens_less_than_1000[5]	22	1			T2	1		T27	1		T49	1
index[0x2]	lens_less_than_1000[6]	6	1			T89	1		T266	1		T106	1
index[0x2]	lens_less_than_1000[7]	2	1			T71	1		T110	1		-	-
index[0x2]	lens_less_than_1000[8]	5	1			T88	1		T92	1		T59	1
index[0x2]	len_2	1	1			T320	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	53	1			T17	2		T18	1		T45	2
index[0x3]	lens_less_than_1000[1]	26	1			T75	1		T70	1		T28	1
index[0x3]	lens_less_than_1000[2]	32	1			T14	1		T18	1		T46	1
index[0x3]	lens_less_than_1000[3]	23	1			T16	1		T228	1		T52	1
index[0x3]	lens_less_than_1000[4]	15	1			T30	1		T92	1		T104	1
index[0x3]	lens_less_than_1000[5]	8	1			T321	1		T56	1		T288	1
index[0x3]	lens_less_than_1000[6]	14	1			T13	1		T48	1		T92	1
index[0x3]	lens_less_than_1000[7]	7	1			T84	1		T57	1		T105	2
index[0x3]	lens_less_than_1000[8]	5	1			T59	1		T286	1		T310	2
index[0x3]	len_2	2	1			T97	1		T322	1		-	-