Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T18	1		T69	1		T48	2
class_index[0x1]	64	1			T20	1		T18	1		T23	1
class_index[0x2]	63	1			T78	1		T24	1		T29	4
class_index[0x3]	69	1			T18	1		T42	1		T76	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	90	1			T20	1		T23	1		T76	1
intr_timeout_cnt[1]	55	1			T18	1		T78	1		T85	1
intr_timeout_cnt[2]	29	1			T131	2		T86	1		T92	1
intr_timeout_cnt[3]	20	1			T69	1		T88	5		T57	1
intr_timeout_cnt[4]	9	1			T18	1		T50	1		T92	1
intr_timeout_cnt[5]	18	1			T18	1		T90	1		T284	1
intr_timeout_cnt[6]	11	1			T42	1		T115	1		T89	1
intr_timeout_cnt[7]	11	1			T24	1		T285	1		T286	1
intr_timeout_cnt[8]	10	1			T50	1		T92	1		T104	1
intr_timeout_cnt[9]	5	1			T287	1		T215	1		T288	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[2]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	20	1			T48	2		T84	1		T83	1
class_index[0x0]	intr_timeout_cnt[1]	16	1			T85	1		T24	1		T289	1
class_index[0x0]	intr_timeout_cnt[2]	10	1			T86	1		T290	2		T284	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T69	1		T282	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T18	1		T50	1		T110	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T286	1		T291	1		T272	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T292	1		T293	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T294	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T50	1		T273	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T215	1		T293	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T20	1		T23	1		T38	1
class_index[0x1]	intr_timeout_cnt[1]	14	1			T18	1		T51	1		T87	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T295	1		T284	1		T106	1
class_index[0x1]	intr_timeout_cnt[3]	7	1			T290	3		T284	1		T286	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T92	1		T296	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T90	1		T297	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T89	1		T273	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T286	1		T298	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	18	1			T29	4		T41	4		T89	2
class_index[0x2]	intr_timeout_cnt[1]	14	1			T78	1		T116	1		T290	1
class_index[0x2]	intr_timeout_cnt[3]	9	1			T88	5		T57	1		T59	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T59	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	5	1			T284	1		T294	1		T299	2
class_index[0x2]	intr_timeout_cnt[6]	2	1			T115	1		T109	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	7	1			T24	1		T285	1		T215	1
class_index[0x2]	intr_timeout_cnt[8]	4	1			T92	1		T286	1		T300	1
class_index[0x2]	intr_timeout_cnt[9]	3	1			T287	1		T288	1		T300	1
class_index[0x3]	intr_timeout_cnt[0]	25	1			T76	1		T120	1		T86	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T59	1		T109	1		T215	1
class_index[0x3]	intr_timeout_cnt[2]	11	1			T131	2		T92	1		T57	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T301	1		T302	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T303	1		T25	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	8	1			T18	1		T271	1		T296	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T42	1		T104	1		T124	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T304	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T104	1		T305	1		T294	1