Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362505	1			T1	20		T2	1493		T3	1889
all_values[1]	362505	1			T1	20		T2	1493		T3	1889
all_values[2]	362505	1			T1	20		T2	1493		T3	1889
all_values[3]	362505	1			T1	20		T2	1493		T3	1889

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

722054

1

T1

41

T2

2897

T3

3806

auto[1]

727966

1

T1

39

T2

3075

T3

3750

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

865061

1

T1

9

T2

3030

T3

5908

auto[1]

584959

1

T1

71

T2

2942

T3

1648

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103076	1			T1	1		T2	360		T3	548
all_values[0]	auto[0]	auto[1]	77401	1			T1	10		T2	358		T3	350
all_values[0]	auto[1]	auto[0]	104546	1			T1	1		T2	388		T3	615
all_values[0]	auto[1]	auto[1]	77482	1			T1	8		T2	387		T3	376
all_values[1]	auto[0]	auto[0]	109156	1			T1	1		T2	374		T3	931
all_values[1]	auto[0]	auto[1]	71662	1			T1	9		T2	346		T3	3
all_values[1]	auto[1]	auto[0]	110113	1			T2	410		T3	955		T19	21
all_values[1]	auto[1]	auto[1]	71574	1			T1	10		T2	363		T19	20
all_values[2]	auto[0]	auto[0]	107792	1			T1	1		T2	346		T3	509
all_values[2]	auto[0]	auto[1]	72411	1			T1	9		T2	346		T3	479
all_values[2]	auto[1]	auto[0]	109324	1			T1	4		T2	401		T3	461
all_values[2]	auto[1]	auto[1]	72978	1			T1	6		T2	400		T3	440
all_values[3]	auto[0]	auto[0]	109744	1			T1	1		T2	387		T3	986
all_values[3]	auto[0]	auto[1]	70812	1			T1	9		T2	380		T19	17
all_values[3]	auto[1]	auto[0]	111310	1			T2	364		T3	903		T19	19
all_values[3]	auto[1]	auto[1]	70639	1			T1	10		T2	362		T19	19