Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362505	1			T1	20		T2	1493		T3	1889
all_pins[1]	362505	1			T1	20		T2	1493		T3	1889
all_pins[2]	362505	1			T1	20		T2	1493		T3	1889
all_pins[3]	362505	1			T1	20		T2	1493		T3	1889

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1157347	1			T1	46		T2	4460		T3	6740
values[0x1]	292673	1			T1	34		T2	1512		T3	816
transitions[0x0=>0x1]	194578	1			T1	17		T2	929		T3	815
transitions[0x1=>0x0]	194818	1			T1	18		T2	930		T3	816

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285023	1			T1	12		T2	1106		T3	1513
all_pins[0]	values[0x1]	77482	1			T1	8		T2	387		T3	376
all_pins[0]	transitions[0x0=>0x1]	76817	1			T1	3		T2	386		T3	375
all_pins[0]	transitions[0x1=>0x0]	70214	1			T1	6		T2	362		T19	19
all_pins[1]	values[0x0]	290931	1			T1	10		T2	1130		T3	1889
all_pins[1]	values[0x1]	71574	1			T1	10		T2	363		T19	20
all_pins[1]	transitions[0x0=>0x1]	39026	1			T1	5		T2	169		T19	8
all_pins[1]	transitions[0x1=>0x0]	44934	1			T1	3		T2	193		T3	376
all_pins[2]	values[0x0]	289527	1			T1	14		T2	1093		T3	1449
all_pins[2]	values[0x1]	72978	1			T1	6		T2	400		T3	440
all_pins[2]	transitions[0x0=>0x1]	40465	1			T1	3		T2	204		T3	440
all_pins[2]	transitions[0x1=>0x0]	39061	1			T1	7		T2	167		T19	12
all_pins[3]	values[0x0]	291866	1			T1	10		T2	1131		T3	1889
all_pins[3]	values[0x1]	70639	1			T1	10		T2	362		T19	19
all_pins[3]	transitions[0x0=>0x1]	38270	1			T1	6		T2	170		T19	11
all_pins[3]	transitions[0x1=>0x0]	40609	1			T1	2		T2	208		T3	440