Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	296	1			T175	7		T176	7		T177	7
all_values[1]	296	1			T175	7		T176	7		T177	7
all_values[2]	296	1			T175	7		T176	7		T177	7
all_values[3]	296	1			T175	7		T176	7		T177	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

658

1

T175

20

T176

10

T177

18

auto[1]

526

1

T175

8

T176

18

T177

10

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

436

1

T175

11

T176

7

T177

8

auto[1]

748

1

T175

17

T176

21

T177

20

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

686

1

T175

17

T176

14

T177

16

auto[1]

498

1

T175

11

T176

14

T177

12

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

57

1

T175

1

T177

3

T283

2

all_values[0]

auto[0]

auto[0]

auto[1]

33

1

T175

2

T176

1

T177

1

all_values[0]

auto[0]

auto[1]

auto[0]

46

1

T367

1

T283

1

T368

2

all_values[0]

auto[0]

auto[1]

auto[1]

37

1

T176

3

T367

2

T369

1

all_values[0]

auto[1]

auto[0]

auto[1]

69

1

T175

3

T176

2

T177

3

all_values[0]

auto[1]

auto[1]

auto[1]

54

1

T175

1

T176

1

T283

1

all_values[1]

auto[0]

auto[0]

auto[0]

63

1

T175

4

T176

1

T177

1

all_values[1]

auto[0]

auto[0]

auto[1]

39

1

T177

2

T369

2

T370

2

all_values[1]

auto[0]

auto[1]

auto[0]

35

1

T175

1

T176

3

T177

1

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T283

1

T369

2

T371

1

all_values[1]

auto[1]

auto[0]

auto[1]

89

1

T175

2

T176

1

T177

3

all_values[1]

auto[1]

auto[1]

auto[1]

41

1

T176

2

T283

1

T369

1

all_values[2]

auto[0]

auto[0]

auto[0]

70

1

T175

4

T176

2

T177

1

all_values[2]

auto[0]

auto[0]

auto[1]

26

1

T177

2

T283

2

T368

1

all_values[2]

auto[0]

auto[1]

auto[0]

55

1

T177

1

T367

3

T369

2

all_values[2]

auto[0]

auto[1]

auto[1]

27

1

T175

1

T176

1

T177

1

all_values[2]

auto[1]

auto[0]

auto[1]

52

1

T176

1

T367

1

T283

2

all_values[2]

auto[1]

auto[1]

auto[1]

66

1

T175

2

T176

3

T177

2

all_values[3]

auto[0]

auto[0]

auto[0]

57

1

T175

1

T177

1

T367

2

all_values[3]

auto[0]

auto[0]

auto[1]

29

1

T175

1

T372

1

T373

1

all_values[3]

auto[0]

auto[1]

auto[0]

53

1

T176

1

T283

2

T369

3

all_values[3]

auto[0]

auto[1]

auto[1]

30

1

T175

2

T176

2

T177

2

all_values[3]

auto[1]

auto[0]

auto[1]

74

1

T175

2

T176

2

T177

1

all_values[3]

auto[1]

auto[1]

auto[1]

53

1

T175

1

T176

2

T177

3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal