Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	88110	1			T2	1482		T4	478		T13	653
accum_cnt_1000	214159	1			T2	1718		T3	1271		T4	425
accum_cnt_100	25932	1			T2	111		T3	73		T19	11
accum_cnt_50	65303	1			T1	32		T2	1206		T3	53
accum_cnt_10	190201	1			T1	26		T2	56		T3	1196
accum_cnt_0	435786	1			T1	58		T2	7		T3	3099

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	267492	1			T1	29		T2	1145		T3	1423
class_index[0x1]	267492	1			T1	29		T2	1145		T3	1423
class_index[0x2]	267492	1			T1	29		T2	1145		T3	1423
class_index[0x3]	267492	1			T1	29		T2	1145		T3	1423

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	22308	1			T2	538		T13	256		T16	603
class_index[0x0]	accum_cnt_1000	55945	1			T2	535		T3	1271		T13	601
class_index[0x0]	accum_cnt_100	7238	1			T2	38		T3	73		T13	31
class_index[0x0]	accum_cnt_50	16622	1			T2	21		T3	53		T13	21
class_index[0x0]	accum_cnt_10	53510	1			T2	11		T3	16		T19	34
class_index[0x0]	accum_cnt_0	96394	1			T1	29		T2	2		T3	10
class_index[0x1]	accum_cnt_2000	23301	1			T2	439		T4	478		T13	397
class_index[0x1]	accum_cnt_1000	52236	1			T2	622		T4	425		T13	466
class_index[0x1]	accum_cnt_100	6507	1			T2	37		T4	26		T13	28
class_index[0x1]	accum_cnt_50	15272	1			T1	21		T2	32		T4	17
class_index[0x1]	accum_cnt_10	46586	1			T1	8		T2	15		T3	1178
class_index[0x1]	accum_cnt_0	111278	1			T3	245		T19	36		T20	4
class_index[0x2]	accum_cnt_2000	20230	1			T14	599		T44	349		T80	408
class_index[0x2]	accum_cnt_1000	55116	1			T14	520		T17	122		T18	959
class_index[0x2]	accum_cnt_100	6389	1			T19	11		T14	29		T17	15
class_index[0x2]	accum_cnt_50	20282	1			T1	11		T2	1123		T19	16
class_index[0x2]	accum_cnt_10	40476	1			T1	18		T2	20		T3	2
class_index[0x2]	accum_cnt_0	116798	1			T2	2		T3	1421		T19	3
class_index[0x3]	accum_cnt_2000	22271	1			T2	505		T14	400		T16	194
class_index[0x3]	accum_cnt_1000	50862	1			T2	561		T14	382		T16	174
class_index[0x3]	accum_cnt_100	5798	1			T2	36		T14	25		T16	10
class_index[0x3]	accum_cnt_50	13127	1			T2	30		T21	18		T14	18
class_index[0x3]	accum_cnt_10	49629	1			T2	10		T21	5		T13	5
class_index[0x3]	accum_cnt_0	111316	1			T1	29		T2	3		T3	1423