Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6694	1			T13	820		T16	47		T270	2
alert[0x1]	6932	1			T16	237		T69	4		T8	1
alert[0x2]	4653	1			T13	74		T26	368		T224	3
alert[0x3]	12492	1			T13	58		T16	198		T26	265
alert[0x4]	9599	1			T5	1		T26	29		T27	54
alert[0x5]	9700	1			T18	11		T69	135		T26	14
alert[0x6]	4647	1			T5	1		T69	4		T26	50
alert[0x7]	2208	1			T13	253		T26	126		T75	2
alert[0x8]	10879	1			T13	986		T26	41		T250	1
alert[0x9]	13733	1			T13	227		T16	289		T69	8
alert[0xa]	5479	1			T5	1		T69	1		T26	578
alert[0xb]	6751	1			T13	11		T26	860		T224	5
alert[0xc]	7488	1			T13	47		T16	11		T48	192
alert[0xd]	6624	1			T16	67		T5	1		T80	1
alert[0xe]	11542	1			T16	53		T18	97		T26	77
alert[0xf]	5003	1			T26	23		T7	1		T120	60
alert[0x10]	9132	1			T13	574		T69	17		T26	180
alert[0x11]	5549	1			T13	96		T16	44		T18	4
alert[0x12]	4123	1			T1	1		T16	26		T69	3
alert[0x13]	9189	1			T3	1		T13	334		T16	428
alert[0x14]	8274	1			T13	59		T16	1239		T18	112
alert[0x15]	8352	1			T13	33		T18	435		T69	26
alert[0x16]	7650	1			T13	69		T5	1		T120	74
alert[0x17]	6254	1			T13	19		T8	1		T120	79
alert[0x18]	8037	1			T16	53		T18	8		T80	3
alert[0x19]	2769	1			T13	18		T18	10		T26	4
alert[0x1a]	4896	1			T13	1327		T75	2		T70	91
alert[0x1b]	7893	1			T26	3		T224	1		T117	15
alert[0x1c]	8732	1			T16	182		T117	1		T120	106
alert[0x1d]	12200	1			T8	1		T48	41		T28	627
alert[0x1e]	14398	1			T13	200		T26	35		T8	1
alert[0x1f]	9814	1			T13	15		T18	232		T26	686
alert[0x20]	9134	1			T26	7		T8	1		T120	202
alert[0x21]	4296	1			T16	32		T27	11		T327	8
alert[0x22]	6925	1			T7	1		T120	203		T70	32
alert[0x23]	2094	1			T20	4		T13	291		T16	18
alert[0x24]	8825	1			T16	37		T8	1		T120	78
alert[0x25]	9713	1			T80	4		T26	42		T7	1
alert[0x26]	4033	1			T13	155		T16	1		T18	228
alert[0x27]	9511	1			T13	1211		T16	755		T5	1
alert[0x28]	8045	1			T7	1		T27	177		T28	12
alert[0x29]	8651	1			T21	13		T18	36		T224	3
alert[0x2a]	5603	1			T3	1		T16	185		T18	263
alert[0x2b]	7158	1			T3	1		T13	84		T16	65
alert[0x2c]	7184	1			T16	391		T18	762		T26	20
alert[0x2d]	3264	1			T20	2		T16	34		T5	1
alert[0x2e]	5373	1			T13	1848		T75	3		T27	64
alert[0x2f]	6824	1			T16	311		T18	28		T70	86
alert[0x30]	7097	1			T18	25		T5	1		T26	110
alert[0x31]	4104	1			T16	66		T26	431		T8	1
alert[0x32]	4791	1			T21	2		T13	809		T16	1013
alert[0x33]	2437	1			T13	107		T26	34		T224	125
alert[0x34]	5629	1			T80	1		T26	27		T224	1
alert[0x35]	3340	1			T16	691		T5	1		T26	125
alert[0x36]	2957	1			T26	10		T7	1		T120	126
alert[0x37]	7894	1			T21	4		T16	16		T7	1
alert[0x38]	5438	1			T13	69		T26	177		T75	1
alert[0x39]	14976	1			T16	248		T5	1		T80	4
alert[0x3a]	12410	1			T13	11		T5	1		T26	45
alert[0x3b]	8403	1			T13	734		T16	659		T80	8
alert[0x3c]	10271	1			T21	36		T16	92		T224	1
alert[0x3d]	17539	1			T26	437		T70	18		T27	104
alert[0x3e]	3459	1			T16	109		T69	2		T8	1
alert[0x3f]	5502	1			T21	9		T13	69		T16	412
alert[0x40]	6628	1			T13	25		T18	71		T48	4

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	122225	1			T21	6		T13	9		T16	24
class_i[0x1]	98252	1			T3	3		T21	25		T5	10
class_i[0x2]	146529	1			T1	1		T20	6		T18	2499
class_i[0x3]	114188	1			T21	33		T13	10624		T16	7985

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

480515

1

T1

1

T20

6

T21

64

alert_ping_fail

679

1

T3

3

T5

11

T6

3

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6689	1			T13	820		T16	47		T270	2
alert_integrity_fail	alert[0x1]	6917	1			T16	237		T69	4		T120	16
alert_integrity_fail	alert[0x2]	4644	1			T13	74		T26	368		T224	3
alert_integrity_fail	alert[0x3]	12479	1			T13	58		T16	198		T26	265
alert_integrity_fail	alert[0x4]	9584	1			T26	29		T27	54		T49	8
alert_integrity_fail	alert[0x5]	9683	1			T18	11		T69	135		T26	14
alert_integrity_fail	alert[0x6]	4628	1			T69	4		T26	50		T120	15
alert_integrity_fail	alert[0x7]	2197	1			T13	253		T26	126		T75	2
alert_integrity_fail	alert[0x8]	10869	1			T13	986		T26	41		T30	2
alert_integrity_fail	alert[0x9]	13727	1			T13	227		T16	289		T69	8
alert_integrity_fail	alert[0xa]	5461	1			T69	1		T26	578		T224	4
alert_integrity_fail	alert[0xb]	6747	1			T13	11		T26	860		T224	5
alert_integrity_fail	alert[0xc]	7481	1			T13	47		T16	11		T48	192
alert_integrity_fail	alert[0xd]	6615	1			T16	67		T80	1		T69	10
alert_integrity_fail	alert[0xe]	11536	1			T16	53		T18	97		T26	77
alert_integrity_fail	alert[0xf]	4994	1			T26	23		T120	60		T70	24
alert_integrity_fail	alert[0x10]	9122	1			T13	574		T69	17		T26	180
alert_integrity_fail	alert[0x11]	5541	1			T13	96		T16	44		T18	4
alert_integrity_fail	alert[0x12]	4109	1			T1	1		T16	26		T69	3
alert_integrity_fail	alert[0x13]	9180	1			T13	334		T16	428		T18	6
alert_integrity_fail	alert[0x14]	8263	1			T13	59		T16	1239		T18	112
alert_integrity_fail	alert[0x15]	8340	1			T13	33		T18	435		T69	26
alert_integrity_fail	alert[0x16]	7634	1			T13	69		T120	74		T51	114
alert_integrity_fail	alert[0x17]	6241	1			T13	19		T120	79		T328	25
alert_integrity_fail	alert[0x18]	8029	1			T16	53		T18	8		T80	3
alert_integrity_fail	alert[0x19]	2758	1			T13	18		T18	10		T26	4
alert_integrity_fail	alert[0x1a]	4884	1			T13	1327		T75	2		T70	91
alert_integrity_fail	alert[0x1b]	7879	1			T26	3		T224	1		T117	15
alert_integrity_fail	alert[0x1c]	8726	1			T16	182		T117	1		T120	106
alert_integrity_fail	alert[0x1d]	12189	1			T48	41		T28	627		T29	346
alert_integrity_fail	alert[0x1e]	14391	1			T13	200		T26	35		T62	9
alert_integrity_fail	alert[0x1f]	9804	1			T13	15		T18	232		T26	686
alert_integrity_fail	alert[0x20]	9118	1			T26	7		T120	202		T70	14
alert_integrity_fail	alert[0x21]	4287	1			T16	32		T27	11		T327	8
alert_integrity_fail	alert[0x22]	6912	1			T120	203		T70	32		T27	939
alert_integrity_fail	alert[0x23]	2085	1			T20	4		T13	291		T16	18
alert_integrity_fail	alert[0x24]	8819	1			T16	37		T120	78		T70	3354
alert_integrity_fail	alert[0x25]	9701	1			T80	4		T26	42		T120	42
alert_integrity_fail	alert[0x26]	4023	1			T13	155		T16	1		T18	228
alert_integrity_fail	alert[0x27]	9505	1			T13	1211		T16	755		T26	2339
alert_integrity_fail	alert[0x28]	8036	1			T27	177		T28	12		T29	340
alert_integrity_fail	alert[0x29]	8640	1			T21	13		T18	36		T224	3
alert_integrity_fail	alert[0x2a]	5592	1			T16	185		T18	263		T28	67
alert_integrity_fail	alert[0x2b]	7149	1			T13	84		T16	65		T69	18
alert_integrity_fail	alert[0x2c]	7167	1			T16	391		T18	762		T26	20
alert_integrity_fail	alert[0x2d]	3252	1			T20	2		T16	34		T26	20
alert_integrity_fail	alert[0x2e]	5363	1			T13	1848		T75	3		T27	64
alert_integrity_fail	alert[0x2f]	6815	1			T16	311		T18	28		T70	86
alert_integrity_fail	alert[0x30]	7085	1			T18	25		T26	110		T120	16
alert_integrity_fail	alert[0x31]	4096	1			T16	66		T26	431		T120	50
alert_integrity_fail	alert[0x32]	4780	1			T21	2		T13	809		T16	1013
alert_integrity_fail	alert[0x33]	2421	1			T13	107		T26	34		T224	125
alert_integrity_fail	alert[0x34]	5625	1			T80	1		T26	27		T224	1
alert_integrity_fail	alert[0x35]	3330	1			T16	691		T26	125		T27	22
alert_integrity_fail	alert[0x36]	2941	1			T26	10		T120	126		T70	238
alert_integrity_fail	alert[0x37]	7884	1			T21	4		T16	16		T29	306
alert_integrity_fail	alert[0x38]	5429	1			T13	69		T26	177		T75	1
alert_integrity_fail	alert[0x39]	14963	1			T16	248		T80	4		T224	1
alert_integrity_fail	alert[0x3a]	12402	1			T13	11		T26	45		T30	1
alert_integrity_fail	alert[0x3b]	8395	1			T13	734		T16	659		T80	8
alert_integrity_fail	alert[0x3c]	10266	1			T21	36		T16	92		T224	1
alert_integrity_fail	alert[0x3d]	17525	1			T26	437		T70	18		T27	104
alert_integrity_fail	alert[0x3e]	3446	1			T16	109		T69	2		T120	43
alert_integrity_fail	alert[0x3f]	5497	1			T21	9		T13	69		T16	412
alert_integrity_fail	alert[0x40]	6625	1			T13	25		T18	71		T48	4
alert_ping_fail	alert[0x0]	5	1			T329	1		T318	1		T330	1
alert_ping_fail	alert[0x1]	15	1			T8	1		T98	1		T331	1
alert_ping_fail	alert[0x2]	9	1			T329	1		T332	1		T333	1
alert_ping_fail	alert[0x3]	13	1			T72	1		T329	1		T318	1
alert_ping_fail	alert[0x4]	15	1			T5	1		T72	1		T334	1
alert_ping_fail	alert[0x5]	17	1			T71	1		T324	1		T98	1
alert_ping_fail	alert[0x6]	19	1			T5	1		T335	1		T72	2
alert_ping_fail	alert[0x7]	11	1			T7	1		T335	1		T72	1
alert_ping_fail	alert[0x8]	10	1			T250	1		T71	1		T332	2
alert_ping_fail	alert[0x9]	6	1			T336	1		T253	1		T337	1
alert_ping_fail	alert[0xa]	18	1			T5	1		T8	1		T98	1
alert_ping_fail	alert[0xb]	4	1			T333	1		T338	1		T339	1
alert_ping_fail	alert[0xc]	7	1			T253	2		T255	1		T281	1
alert_ping_fail	alert[0xd]	9	1			T5	1		T336	1		T340	1
alert_ping_fail	alert[0xe]	6	1			T65	1		T255	1		T281	2
alert_ping_fail	alert[0xf]	9	1			T7	1		T333	1		T341	1
alert_ping_fail	alert[0x10]	10	1			T7	1		T98	2		T281	1
alert_ping_fail	alert[0x11]	8	1			T98	1		T255	1		T280	2
alert_ping_fail	alert[0x12]	14	1			T332	1		T342	1		T340	1
alert_ping_fail	alert[0x13]	9	1			T3	1		T280	1		T343	1
alert_ping_fail	alert[0x14]	11	1			T325	1		T72	2		T332	1
alert_ping_fail	alert[0x15]	12	1			T6	1		T335	1		T329	1
alert_ping_fail	alert[0x16]	16	1			T5	1		T65	1		T318	1
alert_ping_fail	alert[0x17]	13	1			T8	1		T72	1		T318	1
alert_ping_fail	alert[0x18]	8	1			T7	1		T342	1		T336	1
alert_ping_fail	alert[0x19]	11	1			T98	1		T329	1		T255	2
alert_ping_fail	alert[0x1a]	12	1			T340	1		T333	1		T253	2
alert_ping_fail	alert[0x1b]	14	1			T335	2		T334	2		T336	1
alert_ping_fail	alert[0x1c]	6	1			T329	1		T332	1		T342	1
alert_ping_fail	alert[0x1d]	11	1			T8	1		T324	1		T344	1
alert_ping_fail	alert[0x1e]	7	1			T8	1		T334	1		T329	1
alert_ping_fail	alert[0x1f]	10	1			T251	1		T8	1		T329	1
alert_ping_fail	alert[0x20]	16	1			T8	1		T326	1		T98	1
alert_ping_fail	alert[0x21]	9	1			T334	1		T332	1		T255	1
alert_ping_fail	alert[0x22]	13	1			T7	1		T325	1		T34	1
alert_ping_fail	alert[0x23]	9	1			T7	1		T8	1		T329	1
alert_ping_fail	alert[0x24]	6	1			T8	1		T335	1		T255	1
alert_ping_fail	alert[0x25]	12	1			T7	1		T72	1		T98	1
alert_ping_fail	alert[0x26]	10	1			T7	1		T318	1		T342	1
alert_ping_fail	alert[0x27]	6	1			T5	1		T345	1		T346	1
alert_ping_fail	alert[0x28]	9	1			T7	1		T334	1		T318	1
alert_ping_fail	alert[0x29]	11	1			T7	1		T72	1		T98	2
alert_ping_fail	alert[0x2a]	11	1			T3	1		T334	2		T336	1
alert_ping_fail	alert[0x2b]	9	1			T3	1		T329	1		T332	1
alert_ping_fail	alert[0x2c]	17	1			T34	1		T347	2		T342	1
alert_ping_fail	alert[0x2d]	12	1			T5	1		T8	1		T98	1
alert_ping_fail	alert[0x2e]	10	1			T340	1		T333	1		T280	1
alert_ping_fail	alert[0x2f]	9	1			T332	1		T342	1		T336	1
alert_ping_fail	alert[0x30]	12	1			T5	1		T6	2		T333	1
alert_ping_fail	alert[0x31]	8	1			T8	1		T72	1		T332	1
alert_ping_fail	alert[0x32]	11	1			T329	1		T332	1		T340	1
alert_ping_fail	alert[0x33]	16	1			T8	2		T98	1		T334	1
alert_ping_fail	alert[0x34]	4	1			T65	1		T72	1		T336	1
alert_ping_fail	alert[0x35]	10	1			T5	1		T335	1		T253	1
alert_ping_fail	alert[0x36]	16	1			T7	1		T98	2		T336	1
alert_ping_fail	alert[0x37]	10	1			T7	1		T331	1		T340	1
alert_ping_fail	alert[0x38]	9	1			T8	1		T335	1		T72	2
alert_ping_fail	alert[0x39]	13	1			T5	1		T335	1		T72	1
alert_ping_fail	alert[0x3a]	8	1			T5	1		T334	2		T340	1
alert_ping_fail	alert[0x3b]	8	1			T8	1		T332	1		T280	1
alert_ping_fail	alert[0x3c]	5	1			T335	1		T334	1		T332	1
alert_ping_fail	alert[0x3d]	14	1			T335	1		T332	3		T336	1
alert_ping_fail	alert[0x3e]	13	1			T8	1		T335	1		T72	1
alert_ping_fail	alert[0x3f]	5	1			T8	1		T255	1		T348	1
alert_ping_fail	alert[0x40]	3	1			T349	1		T350	1		T351	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	122079	1			T21	6		T13	9		T16	24
alert_integrity_fail	class_i[0x1]	98039	1			T21	25		T75	38		T117	6
alert_integrity_fail	class_i[0x2]	146360	1			T1	1		T20	6		T18	2499
alert_integrity_fail	class_i[0x3]	114037	1			T21	33		T13	10624		T16	7985
alert_ping_fail	class_i[0x0]	146	1			T7	1		T8	4		T335	5
alert_ping_fail	class_i[0x1]	213	1			T3	3		T5	10		T250	1
alert_ping_fail	class_i[0x2]	169	1			T5	1		T7	1		T8	11
alert_ping_fail	class_i[0x3]	151	1			T6	3		T7	8		T335	3