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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.69 99.97 100.00 100.00 99.38 99.56


Total test records in report: 831
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T773 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2568221402 Feb 29 01:35:13 PM PST 24 Feb 29 01:35:15 PM PST 24 8580300 ps
T774 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3000563003 Feb 29 01:35:11 PM PST 24 Feb 29 01:35:30 PM PST 24 247756127 ps
T775 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.827152870 Feb 29 01:35:12 PM PST 24 Feb 29 01:35:20 PM PST 24 101929463 ps
T161 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.465880687 Feb 29 01:35:38 PM PST 24 Feb 29 01:37:19 PM PST 24 2963911892 ps
T776 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1943608695 Feb 29 01:35:40 PM PST 24 Feb 29 01:35:42 PM PST 24 25787105 ps
T777 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2573736879 Feb 29 01:35:35 PM PST 24 Feb 29 01:35:36 PM PST 24 12735605 ps
T778 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.851320537 Feb 29 01:35:35 PM PST 24 Feb 29 01:35:37 PM PST 24 19018911 ps
T779 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.230650378 Feb 29 01:35:35 PM PST 24 Feb 29 01:35:37 PM PST 24 10561196 ps
T162 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.537951702 Feb 29 01:35:04 PM PST 24 Feb 29 01:43:31 PM PST 24 4645165180 ps
T184 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.202098411 Feb 29 01:35:13 PM PST 24 Feb 29 01:35:39 PM PST 24 320463717 ps
T156 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4145778897 Feb 29 01:35:23 PM PST 24 Feb 29 01:52:01 PM PST 24 13860928809 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4105017409 Feb 29 01:34:51 PM PST 24 Feb 29 01:34:53 PM PST 24 7756216 ps
T781 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.784667140 Feb 29 01:35:31 PM PST 24 Feb 29 01:35:50 PM PST 24 252439354 ps
T782 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2967659319 Feb 29 01:35:28 PM PST 24 Feb 29 01:35:36 PM PST 24 32871438 ps
T783 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.566940606 Feb 29 01:34:49 PM PST 24 Feb 29 01:34:53 PM PST 24 93208205 ps
T141 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.592355887 Feb 29 01:35:23 PM PST 24 Feb 29 01:52:09 PM PST 24 12524292705 ps
T784 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3278657414 Feb 29 01:35:38 PM PST 24 Feb 29 01:35:39 PM PST 24 11529980 ps
T785 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3647968064 Feb 29 01:35:36 PM PST 24 Feb 29 01:35:38 PM PST 24 6798528 ps
T786 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2375411948 Feb 29 01:35:24 PM PST 24 Feb 29 01:35:33 PM PST 24 80779399 ps
T787 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4103286502 Feb 29 01:34:58 PM PST 24 Feb 29 01:35:30 PM PST 24 559964107 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.79666467 Feb 29 01:35:14 PM PST 24 Feb 29 01:35:41 PM PST 24 724919701 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.258441185 Feb 29 01:35:36 PM PST 24 Feb 29 01:35:42 PM PST 24 148573510 ps
T790 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.133912862 Feb 29 01:35:39 PM PST 24 Feb 29 01:35:41 PM PST 24 6771372 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.583164292 Feb 29 01:34:59 PM PST 24 Feb 29 01:41:42 PM PST 24 22863456615 ps
T157 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2219966864 Feb 29 01:34:58 PM PST 24 Feb 29 01:38:12 PM PST 24 1627861454 ps
T792 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3257161574 Feb 29 01:35:34 PM PST 24 Feb 29 01:35:36 PM PST 24 9806605 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1178963691 Feb 29 01:34:58 PM PST 24 Feb 29 01:35:07 PM PST 24 1486354368 ps
T794 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1996811181 Feb 29 01:35:02 PM PST 24 Feb 29 01:35:08 PM PST 24 232620938 ps
T795 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3440471314 Feb 29 01:35:33 PM PST 24 Feb 29 01:35:35 PM PST 24 32612764 ps
T796 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2005049118 Feb 29 01:35:28 PM PST 24 Feb 29 01:35:34 PM PST 24 79397516 ps
T181 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.805649348 Feb 29 01:35:25 PM PST 24 Feb 29 01:35:47 PM PST 24 316039540 ps
T797 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3257774876 Feb 29 01:35:38 PM PST 24 Feb 29 01:35:40 PM PST 24 15925108 ps
T798 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1355659236 Feb 29 01:35:38 PM PST 24 Feb 29 01:35:40 PM PST 24 9230439 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.986208076 Feb 29 01:35:16 PM PST 24 Feb 29 01:35:29 PM PST 24 95165569 ps
T167 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.243264802 Feb 29 01:35:24 PM PST 24 Feb 29 01:37:36 PM PST 24 14657474593 ps
T800 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2195857507 Feb 29 01:35:25 PM PST 24 Feb 29 01:35:32 PM PST 24 109936268 ps
T801 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3310350773 Feb 29 01:35:25 PM PST 24 Feb 29 01:35:35 PM PST 24 188598194 ps
T802 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3495310438 Feb 29 01:35:25 PM PST 24 Feb 29 01:35:34 PM PST 24 125708640 ps
T803 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1181206298 Feb 29 01:34:49 PM PST 24 Feb 29 01:34:54 PM PST 24 221663388 ps
T168 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2885623303 Feb 29 01:34:59 PM PST 24 Feb 29 01:42:59 PM PST 24 24460524807 ps
T163 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1084619903 Feb 29 01:35:36 PM PST 24 Feb 29 01:38:32 PM PST 24 14917185317 ps
T804 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3786621876 Feb 29 01:35:36 PM PST 24 Feb 29 01:35:39 PM PST 24 11391778 ps
T805 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3868898219 Feb 29 01:34:59 PM PST 24 Feb 29 01:43:19 PM PST 24 6182236304 ps
T378 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.488510781 Feb 29 01:34:43 PM PST 24 Feb 29 01:40:29 PM PST 24 2224838325 ps
T806 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.806985900 Feb 29 01:35:37 PM PST 24 Feb 29 01:35:39 PM PST 24 14839471 ps
T807 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2911356632 Feb 29 01:35:15 PM PST 24 Feb 29 01:35:21 PM PST 24 71816384 ps
T808 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1261893504 Feb 29 01:35:42 PM PST 24 Feb 29 01:35:44 PM PST 24 13700320 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3714621020 Feb 29 01:35:25 PM PST 24 Feb 29 01:42:12 PM PST 24 8676822133 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2939169859 Feb 29 01:34:50 PM PST 24 Feb 29 01:38:22 PM PST 24 6280747137 ps
T810 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1768908282 Feb 29 01:35:11 PM PST 24 Feb 29 01:35:25 PM PST 24 945995233 ps
T811 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.888858802 Feb 29 01:35:24 PM PST 24 Feb 29 01:35:43 PM PST 24 280678947 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3289748279 Feb 29 01:35:37 PM PST 24 Feb 29 01:35:58 PM PST 24 260129045 ps
T813 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.317636307 Feb 29 01:35:25 PM PST 24 Feb 29 01:35:34 PM PST 24 1254552193 ps
T814 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3420783604 Feb 29 01:34:59 PM PST 24 Feb 29 01:35:14 PM PST 24 1571805443 ps
T160 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3282582027 Feb 29 01:34:58 PM PST 24 Feb 29 01:41:39 PM PST 24 21962698232 ps
T815 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1866914712 Feb 29 01:35:34 PM PST 24 Feb 29 01:35:36 PM PST 24 12926623 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1302248694 Feb 29 01:34:49 PM PST 24 Feb 29 01:35:09 PM PST 24 992380661 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2395993367 Feb 29 01:34:57 PM PST 24 Feb 29 01:35:37 PM PST 24 621521233 ps
T818 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3819904345 Feb 29 01:35:16 PM PST 24 Feb 29 01:35:24 PM PST 24 196387041 ps
T179 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.478380982 Feb 29 01:34:50 PM PST 24 Feb 29 01:35:03 PM PST 24 278858514 ps
T183 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1101083177 Feb 29 01:35:24 PM PST 24 Feb 29 01:36:57 PM PST 24 2698016004 ps
T169 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3338421050 Feb 29 01:34:46 PM PST 24 Feb 29 01:36:08 PM PST 24 711097604 ps
T819 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2861538169 Feb 29 01:35:02 PM PST 24 Feb 29 01:35:12 PM PST 24 109281292 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.284793140 Feb 29 01:34:57 PM PST 24 Feb 29 01:35:05 PM PST 24 46487467 ps
T821 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1824920069 Feb 29 01:35:38 PM PST 24 Feb 29 01:35:40 PM PST 24 6457573 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.935791843 Feb 29 01:35:28 PM PST 24 Feb 29 01:35:42 PM PST 24 153727526 ps
T166 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3215487381 Feb 29 01:35:04 PM PST 24 Feb 29 01:39:51 PM PST 24 15690487899 ps
T180 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2525029277 Feb 29 01:35:38 PM PST 24 Feb 29 01:35:42 PM PST 24 277088450 ps
T191 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4031930417 Feb 29 01:35:29 PM PST 24 Feb 29 01:36:11 PM PST 24 1213005591 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.149798804 Feb 29 01:35:05 PM PST 24 Feb 29 01:35:15 PM PST 24 152477448 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3160274103 Feb 29 01:35:37 PM PST 24 Feb 29 01:35:42 PM PST 24 59448204 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2135976717 Feb 29 01:35:13 PM PST 24 Feb 29 01:35:58 PM PST 24 706233174 ps
T826 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2444221499 Feb 29 01:34:52 PM PST 24 Feb 29 01:36:59 PM PST 24 3223082829 ps
T827 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2132178403 Feb 29 01:35:39 PM PST 24 Feb 29 01:35:41 PM PST 24 13500029 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2732072608 Feb 29 01:35:22 PM PST 24 Feb 29 01:35:34 PM PST 24 130100979 ps
T170 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4192297108 Feb 29 01:34:48 PM PST 24 Feb 29 01:46:47 PM PST 24 5700163249 ps
T829 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.22677741 Feb 29 01:35:34 PM PST 24 Feb 29 01:35:51 PM PST 24 881263783 ps
T830 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.619235580 Feb 29 01:34:52 PM PST 24 Feb 29 01:34:57 PM PST 24 30375585 ps
T165 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4281958725 Feb 29 01:35:25 PM PST 24 Feb 29 01:52:20 PM PST 24 60657923651 ps
T171 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2301360683 Feb 29 01:35:34 PM PST 24 Feb 29 01:37:14 PM PST 24 745708463 ps
T831 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2132837870 Feb 29 01:35:15 PM PST 24 Feb 29 01:35:20 PM PST 24 201848108 ps

Test location /workspace/coverage/default/28.alert_handler_entropy.2565819397
Short name T13
Test name
Test status
Simulation time 145681147772 ps
CPU time 2356.8 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:46:32 PM PST 24
Peak memory 272732 kb
Host smart-18de3526-4d43-40cf-8d18-2305e37f45df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565819397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2565819397
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3078444960
Short name T18
Test name
Test status
Simulation time 871360337632 ps
CPU time 5714.4 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 03:41:43 PM PST 24
Peak memory 369980 kb
Host smart-2b03a293-a11b-417d-9ac5-3aad41bf0368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078444960 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3078444960
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1254896866
Short name T9
Test name
Test status
Simulation time 441018905 ps
CPU time 25.05 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:06:08 PM PST 24
Peak memory 267984 kb
Host smart-77f0f612-e77f-4c23-9d5d-6da4797d8c03
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1254896866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1254896866
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3463568298
Short name T136
Test name
Test status
Simulation time 307624318933 ps
CPU time 1314.6 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:57:20 PM PST 24
Peak memory 273016 kb
Host smart-0da1d1de-23e2-4d95-bc52-c2e85469ebda
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463568298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3463568298
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3060466653
Short name T26
Test name
Test status
Simulation time 45185774217 ps
CPU time 2100.73 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:42:01 PM PST 24
Peak memory 281100 kb
Host smart-71c274cc-cc97-4dfb-9942-c77aba71e0e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060466653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3060466653
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2812951204
Short name T173
Test name
Test status
Simulation time 4673518690 ps
CPU time 68.7 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:36:11 PM PST 24
Peak memory 239576 kb
Host smart-4cd327dc-40ed-40ef-b305-5543ce610c92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2812951204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2812951204
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1299248703
Short name T29
Test name
Test status
Simulation time 211839633603 ps
CPU time 6338.72 seconds
Started Feb 29 02:07:01 PM PST 24
Finished Feb 29 03:52:40 PM PST 24
Peak memory 351916 kb
Host smart-e5c885fb-96b5-4f30-9c6d-135263fb936e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299248703 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1299248703
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2372383764
Short name T27
Test name
Test status
Simulation time 31132915316 ps
CPU time 1760.1 seconds
Started Feb 29 02:09:21 PM PST 24
Finished Feb 29 02:38:41 PM PST 24
Peak memory 269868 kb
Host smart-322a8de6-4f7d-4a44-8692-2ca2dacbaccb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372383764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2372383764
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2071184207
Short name T6
Test name
Test status
Simulation time 483593772060 ps
CPU time 2837.6 seconds
Started Feb 29 02:08:42 PM PST 24
Finished Feb 29 02:56:00 PM PST 24
Peak memory 288248 kb
Host smart-ffa8c50f-aefb-4abe-83ef-e282ec19579b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071184207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2071184207
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2294752409
Short name T28
Test name
Test status
Simulation time 94893630465 ps
CPU time 2863.98 seconds
Started Feb 29 02:06:18 PM PST 24
Finished Feb 29 02:54:02 PM PST 24
Peak memory 289244 kb
Host smart-f9002e3a-8fa1-4402-96c1-6361d9387873
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294752409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2294752409
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2155613991
Short name T149
Test name
Test status
Simulation time 6107208253 ps
CPU time 204.68 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:38:37 PM PST 24
Peak memory 271872 kb
Host smart-6efd3d20-ea7f-4bcf-8150-4cade410c7b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2155613991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2155613991
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.1408252697
Short name T57
Test name
Test status
Simulation time 108425525399 ps
CPU time 3091.61 seconds
Started Feb 29 02:09:37 PM PST 24
Finished Feb 29 03:01:09 PM PST 24
Peak memory 299872 kb
Host smart-c13080fa-2d5c-401f-82f0-66c44463ed2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408252697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.1408252697
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.49240461
Short name T144
Test name
Test status
Simulation time 3869628682 ps
CPU time 284.42 seconds
Started Feb 29 01:35:15 PM PST 24
Finished Feb 29 01:39:59 PM PST 24
Peak memory 265560 kb
Host smart-cba561c7-0c42-425a-a442-f0df825854a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=49240461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors
.49240461
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.838580880
Short name T300
Test name
Test status
Simulation time 380175057816 ps
CPU time 6194.04 seconds
Started Feb 29 02:08:52 PM PST 24
Finished Feb 29 03:52:07 PM PST 24
Peak memory 321020 kb
Host smart-024798bb-68b7-4e36-b25b-3fe2a282c907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838580880 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.838580880
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3913474086
Short name T605
Test name
Test status
Simulation time 80891397638 ps
CPU time 4653.6 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 03:23:04 PM PST 24
Peak memory 303528 kb
Host smart-d647c05a-d48f-4138-8e9a-afa5b08c442d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913474086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3913474086
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1276647832
Short name T148
Test name
Test status
Simulation time 13226828848 ps
CPU time 1052.64 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:52:45 PM PST 24
Peak memory 272928 kb
Host smart-d8cf50eb-8988-43bb-a5a5-a3a9b8d9b27e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276647832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1276647832
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1318077010
Short name T3
Test name
Test status
Simulation time 39572574882 ps
CPU time 2437.88 seconds
Started Feb 29 02:05:56 PM PST 24
Finished Feb 29 02:46:35 PM PST 24
Peak memory 288668 kb
Host smart-fbcf10ff-ebc0-48f0-909f-fb0688e322bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318077010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1318077010
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.290813493
Short name T176
Test name
Test status
Simulation time 8735817 ps
CPU time 1.52 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:27 PM PST 24
Peak memory 235832 kb
Host smart-becfeeec-b3b9-4e8f-8ac3-0d9e8f258922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=290813493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.290813493
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1698895169
Short name T8
Test name
Test status
Simulation time 43988339177 ps
CPU time 480.23 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:13:41 PM PST 24
Peak memory 246932 kb
Host smart-add5ab70-8b22-4304-925f-2c286d6ea6fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698895169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1698895169
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.592355887
Short name T141
Test name
Test status
Simulation time 12524292705 ps
CPU time 1003.61 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:52:09 PM PST 24
Peak memory 271284 kb
Host smart-d7153406-1333-4506-a5f7-4fc9ca86e935
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592355887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.592355887
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3079438486
Short name T17
Test name
Test status
Simulation time 14518887838 ps
CPU time 365.96 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:12:37 PM PST 24
Peak memory 256516 kb
Host smart-6c5bda1c-330b-4a43-bec4-0314f2fd4899
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079438486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3079438486
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3579292879
Short name T324
Test name
Test status
Simulation time 47638239336 ps
CPU time 2940.99 seconds
Started Feb 29 02:05:49 PM PST 24
Finished Feb 29 02:54:50 PM PST 24
Peak memory 284856 kb
Host smart-e2144274-b574-4cb8-9bee-9ed8e297ce72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579292879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3579292879
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3920139925
Short name T48
Test name
Test status
Simulation time 339706275203 ps
CPU time 3429.12 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 03:04:25 PM PST 24
Peak memory 305228 kb
Host smart-c4bf038f-e6a8-4bc3-bbf1-e5d4ef451416
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920139925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3920139925
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.862539875
Short name T135
Test name
Test status
Simulation time 8091807344 ps
CPU time 221.86 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:39:08 PM PST 24
Peak memory 266516 kb
Host smart-556c16f4-132c-4aa8-981e-54dfb825180a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=862539875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.862539875
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.4262526057
Short name T349
Test name
Test status
Simulation time 98074969249 ps
CPU time 525.39 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:14:59 PM PST 24
Peak memory 246988 kb
Host smart-85d9689c-9697-46bd-8233-f514f5dd76c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262526057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.4262526057
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.435114000
Short name T140
Test name
Test status
Simulation time 5012955665 ps
CPU time 335.75 seconds
Started Feb 29 01:34:47 PM PST 24
Finished Feb 29 01:40:23 PM PST 24
Peak memory 265488 kb
Host smart-c9fed9d5-dfd6-45be-83ff-28247d78b9cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=435114000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.435114000
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3489460852
Short name T5
Test name
Test status
Simulation time 18299386739 ps
CPU time 354.68 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:11:37 PM PST 24
Peak memory 247132 kb
Host smart-8b211d7d-9f79-4c67-93aa-cec3696ef885
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489460852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3489460852
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1630408968
Short name T22
Test name
Test status
Simulation time 510126026871 ps
CPU time 2541.34 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 02:51:56 PM PST 24
Peak memory 272176 kb
Host smart-efbfce07-6262-4b4f-8de3-63154de51269
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630408968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1630408968
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.918068084
Short name T273
Test name
Test status
Simulation time 73518792228 ps
CPU time 4954.32 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 03:28:21 PM PST 24
Peak memory 322172 kb
Host smart-39cf9270-5ace-4e13-a01a-d269f4848586
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918068084 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.918068084
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1621359457
Short name T7
Test name
Test status
Simulation time 8635045330 ps
CPU time 376.66 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:13:17 PM PST 24
Peak memory 247092 kb
Host smart-8a936890-f0d0-4d56-82f3-8a08e3d82c73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621359457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1621359457
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.537951702
Short name T162
Test name
Test status
Simulation time 4645165180 ps
CPU time 507.55 seconds
Started Feb 29 01:35:04 PM PST 24
Finished Feb 29 01:43:31 PM PST 24
Peak memory 265416 kb
Host smart-109406e6-e6c1-4da9-8ffe-d19071aac067
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537951702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.537951702
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.300588572
Short name T364
Test name
Test status
Simulation time 92316096653 ps
CPU time 2824.08 seconds
Started Feb 29 02:09:08 PM PST 24
Finished Feb 29 02:56:13 PM PST 24
Peak memory 288600 kb
Host smart-a11ba4c0-a3a5-4734-aec1-edce3390d657
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300588572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.300588572
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3133671173
Short name T59
Test name
Test status
Simulation time 97205558398 ps
CPU time 3239.22 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 03:04:20 PM PST 24
Peak memory 288880 kb
Host smart-d38292d6-706e-4a1f-8a44-8aefc33ec8c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133671173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3133671173
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.865172654
Short name T371
Test name
Test status
Simulation time 8695705 ps
CPU time 1.48 seconds
Started Feb 29 01:35:21 PM PST 24
Finished Feb 29 01:35:23 PM PST 24
Peak memory 236700 kb
Host smart-211b751e-d1f8-414b-9341-84496173901d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=865172654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.865172654
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3324562074
Short name T332
Test name
Test status
Simulation time 55701901169 ps
CPU time 587.96 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:15:14 PM PST 24
Peak memory 247148 kb
Host smart-65c79df7-4965-49f7-b417-f3bea6f6199b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324562074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3324562074
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1113061899
Short name T23
Test name
Test status
Simulation time 902691052 ps
CPU time 48.11 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:06:34 PM PST 24
Peak memory 248360 kb
Host smart-27bf7ed8-b8b8-4577-98c8-bc49591618a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11130
61899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1113061899
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3411245220
Short name T143
Test name
Test status
Simulation time 26087087062 ps
CPU time 1009.49 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:52:14 PM PST 24
Peak memory 265524 kb
Host smart-7564f3b1-b72c-4382-b1a4-53bf40976458
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411245220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3411245220
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4145778897
Short name T156
Test name
Test status
Simulation time 13860928809 ps
CPU time 996.21 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:52:01 PM PST 24
Peak memory 265484 kb
Host smart-837ab6df-7dd4-4eba-9ce2-a7a95827b946
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145778897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4145778897
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.444964232
Short name T365
Test name
Test status
Simulation time 63655876786 ps
CPU time 1926.52 seconds
Started Feb 29 02:05:30 PM PST 24
Finished Feb 29 02:37:37 PM PST 24
Peak memory 272396 kb
Host smart-e8cfda60-5f15-4f9c-934b-760ff174f206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444964232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.444964232
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2401244260
Short name T215
Test name
Test status
Simulation time 327539152365 ps
CPU time 1589.29 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:33:05 PM PST 24
Peak memory 281256 kb
Host smart-5f7862ec-a24b-4718-86b4-bb6540f6684b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401244260 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2401244260
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2840287297
Short name T281
Test name
Test status
Simulation time 12979161362 ps
CPU time 553.31 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:16:29 PM PST 24
Peak memory 246992 kb
Host smart-a79fbeef-d313-4a2b-bcd1-dd3e384052ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840287297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2840287297
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2909864256
Short name T251
Test name
Test status
Simulation time 31845472923 ps
CPU time 1739.29 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:34:43 PM PST 24
Peak memory 272172 kb
Host smart-68dfb5e4-ef2a-414d-aafa-969900bf3aa0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909864256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2909864256
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1313590642
Short name T69
Test name
Test status
Simulation time 214957888 ps
CPU time 24.09 seconds
Started Feb 29 02:05:30 PM PST 24
Finished Feb 29 02:05:55 PM PST 24
Peak memory 254076 kb
Host smart-c3736d6e-ff85-4147-a3b3-501e93a6dec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13135
90642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1313590642
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.458349929
Short name T151
Test name
Test status
Simulation time 2312797397 ps
CPU time 362.96 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:41:15 PM PST 24
Peak memory 265584 kb
Host smart-ea4c4dd3-05c1-4a9e-9864-1bf8da4fc250
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458349929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.458349929
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1336666959
Short name T187
Test name
Test status
Simulation time 348251627 ps
CPU time 42.35 seconds
Started Feb 29 01:35:30 PM PST 24
Finished Feb 29 01:36:13 PM PST 24
Peak memory 240608 kb
Host smart-492ab2aa-ae99-49d6-8429-19c6723ed9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1336666959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1336666959
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.4010266389
Short name T92
Test name
Test status
Simulation time 182748611474 ps
CPU time 3233.79 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 03:00:21 PM PST 24
Peak memory 297508 kb
Host smart-23e3bef1-4530-40eb-9fb7-f3e2dfccd728
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010266389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.4010266389
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.527599375
Short name T76
Test name
Test status
Simulation time 1769112250 ps
CPU time 28.52 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:22 PM PST 24
Peak memory 246700 kb
Host smart-bcea4a5c-21b1-49fe-8199-971efd320605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52759
9375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.527599375
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2013746029
Short name T247
Test name
Test status
Simulation time 36384585 ps
CPU time 3.49 seconds
Started Feb 29 02:05:27 PM PST 24
Finished Feb 29 02:05:31 PM PST 24
Peak memory 248484 kb
Host smart-18bfc5e6-5ddb-46f1-91bf-5ca5d2a71b4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2013746029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2013746029
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.212883108
Short name T235
Test name
Test status
Simulation time 59054001 ps
CPU time 3.03 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:06:14 PM PST 24
Peak memory 248532 kb
Host smart-c0883b9b-51d0-47d7-9e10-0ffef73e86e4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=212883108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.212883108
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2240617238
Short name T237
Test name
Test status
Simulation time 33479588 ps
CPU time 3.2 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:15 PM PST 24
Peak memory 248576 kb
Host smart-3623586c-ee0b-4170-a1b6-31edd26b1af7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2240617238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2240617238
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2081620481
Short name T243
Test name
Test status
Simulation time 35651356 ps
CPU time 3.33 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:16 PM PST 24
Peak memory 248484 kb
Host smart-0502040e-fcea-4345-a6ee-66280c170d46
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2081620481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2081620481
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3949238609
Short name T150
Test name
Test status
Simulation time 3944544808 ps
CPU time 160.1 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:38:06 PM PST 24
Peak memory 265496 kb
Host smart-ebef30aa-1257-4371-bfbe-eacc1fe5a8c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3949238609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3949238609
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.687825799
Short name T743
Test name
Test status
Simulation time 9977511 ps
CPU time 1.6 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:50 PM PST 24
Peak memory 236676 kb
Host smart-5133486a-bc81-4d6b-bc6b-23f132572a2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=687825799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.687825799
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3640156271
Short name T498
Test name
Test status
Simulation time 39912830721 ps
CPU time 989.07 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:22:41 PM PST 24
Peak memory 272308 kb
Host smart-56a3b73a-b14e-4af6-9ad1-bdab32991dca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640156271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3640156271
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1993137889
Short name T354
Test name
Test status
Simulation time 227726102664 ps
CPU time 1844.48 seconds
Started Feb 29 02:07:02 PM PST 24
Finished Feb 29 02:37:46 PM PST 24
Peak memory 271276 kb
Host smart-9bf935e2-957a-46c7-a94e-9fdb3f6aa51f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993137889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1993137889
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.66913345
Short name T286
Test name
Test status
Simulation time 2843401866 ps
CPU time 46.41 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:08:18 PM PST 24
Peak memory 255312 kb
Host smart-7b96e7fa-3914-4cd2-804b-4367a52c863c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66913
345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.66913345
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3714454975
Short name T293
Test name
Test status
Simulation time 185756423037 ps
CPU time 3443.19 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 03:05:05 PM PST 24
Peak memory 300200 kb
Host smart-479800e5-4cb1-467d-8139-c0519ad5f627
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714454975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3714454975
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.478380982
Short name T179
Test name
Test status
Simulation time 278858514 ps
CPU time 12.81 seconds
Started Feb 29 01:34:50 PM PST 24
Finished Feb 29 01:35:03 PM PST 24
Peak memory 237060 kb
Host smart-06649465-3f38-4ac9-a404-9b67ea2a90d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=478380982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.478380982
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1891425719
Short name T12
Test name
Test status
Simulation time 827370222 ps
CPU time 11.8 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:05:41 PM PST 24
Peak memory 240112 kb
Host smart-4b8c9583-8ef2-4cdd-9ed8-a7628f4a6db0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1891425719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1891425719
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1375218869
Short name T154
Test name
Test status
Simulation time 9028084029 ps
CPU time 307.11 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:40:19 PM PST 24
Peak memory 265772 kb
Host smart-38674825-4e91-4c5d-9f49-29bfe10f1857
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375218869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1375218869
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2302251742
Short name T25
Test name
Test status
Simulation time 64504357054 ps
CPU time 1099.85 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 02:24:47 PM PST 24
Peak memory 281252 kb
Host smart-435d701c-5da6-46e2-9146-87c59895b9a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302251742 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2302251742
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.488510781
Short name T378
Test name
Test status
Simulation time 2224838325 ps
CPU time 346.39 seconds
Started Feb 29 01:34:43 PM PST 24
Finished Feb 29 01:40:29 PM PST 24
Peak memory 265576 kb
Host smart-a2c666b2-5377-45e4-9804-a81795064281
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488510781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.488510781
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1497353565
Short name T337
Test name
Test status
Simulation time 54633847884 ps
CPU time 590.79 seconds
Started Feb 29 02:05:27 PM PST 24
Finished Feb 29 02:15:18 PM PST 24
Peak memory 247160 kb
Host smart-3359ca3c-eb13-4dda-add7-3b570d79f387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497353565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1497353565
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.544189516
Short name T614
Test name
Test status
Simulation time 34849391840 ps
CPU time 363.1 seconds
Started Feb 29 02:06:10 PM PST 24
Finished Feb 29 02:12:13 PM PST 24
Peak memory 247196 kb
Host smart-94a1db8b-5de4-48dc-b36e-0e5e682016a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544189516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.544189516
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2586676989
Short name T228
Test name
Test status
Simulation time 174729234 ps
CPU time 22.37 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:34 PM PST 24
Peak memory 254820 kb
Host smart-e4338787-5fe8-4230-8688-b37650c7dd33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25866
76989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2586676989
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1512921226
Short name T297
Test name
Test status
Simulation time 842206139 ps
CPU time 27.3 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:41 PM PST 24
Peak memory 254476 kb
Host smart-1f50e8aa-9c01-4bb7-be9f-8093294c8189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15129
21226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1512921226
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1760158252
Short name T497
Test name
Test status
Simulation time 5105968956 ps
CPU time 66.93 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:07:33 PM PST 24
Peak memory 255952 kb
Host smart-f2c0cfe1-b52a-47a8-bbf4-ea9c1fc299cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17601
58252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1760158252
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1162116253
Short name T316
Test name
Test status
Simulation time 45112446230 ps
CPU time 401.21 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:13:13 PM PST 24
Peak memory 246192 kb
Host smart-a434b858-4aee-4117-82a1-c365a1a2f6cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162116253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1162116253
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3842473304
Short name T339
Test name
Test status
Simulation time 30298748202 ps
CPU time 326.61 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:12:03 PM PST 24
Peak memory 246200 kb
Host smart-83b7e4fa-3d10-47aa-92d4-46518be3e753
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842473304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3842473304
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.3841336654
Short name T115
Test name
Test status
Simulation time 216550529 ps
CPU time 23.56 seconds
Started Feb 29 02:06:42 PM PST 24
Finished Feb 29 02:07:06 PM PST 24
Peak memory 246716 kb
Host smart-4b15ca41-2ed7-46c9-8688-26718a3bfef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38413
36654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.3841336654
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.32403181
Short name T322
Test name
Test status
Simulation time 39635472919 ps
CPU time 2352.72 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:45:50 PM PST 24
Peak memory 288980 kb
Host smart-3440b2d4-93d1-49c3-98f2-188e6aaff36d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32403181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.32403181
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2104751026
Short name T306
Test name
Test status
Simulation time 963852155 ps
CPU time 26.61 seconds
Started Feb 29 02:06:37 PM PST 24
Finished Feb 29 02:07:04 PM PST 24
Peak memory 246560 kb
Host smart-a81e1e13-3f3e-4ac3-9b70-30987fb81a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21047
51026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2104751026
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3607814260
Short name T304
Test name
Test status
Simulation time 23786688088 ps
CPU time 202.29 seconds
Started Feb 29 02:06:49 PM PST 24
Finished Feb 29 02:10:12 PM PST 24
Peak memory 256504 kb
Host smart-e1a07d5a-47e3-4bf3-b17b-ca0392dab21b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607814260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3607814260
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.52316798
Short name T110
Test name
Test status
Simulation time 38856249814 ps
CPU time 4078.72 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 03:15:41 PM PST 24
Peak memory 321548 kb
Host smart-96638a0f-2307-40b3-a244-66f9e7d4767f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52316798 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.52316798
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2418636768
Short name T217
Test name
Test status
Simulation time 22931832434 ps
CPU time 1613.58 seconds
Started Feb 29 02:07:58 PM PST 24
Finished Feb 29 02:34:51 PM PST 24
Peak memory 272496 kb
Host smart-8dd93e6d-27ff-4e15-b562-7a71c87c9111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418636768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2418636768
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3280316900
Short name T198
Test name
Test status
Simulation time 82481931937 ps
CPU time 1770.02 seconds
Started Feb 29 02:08:22 PM PST 24
Finished Feb 29 02:37:53 PM PST 24
Peak memory 284324 kb
Host smart-f1c7cdde-308f-45d9-910f-efe545ce1299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280316900 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3280316900
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3975317668
Short name T302
Test name
Test status
Simulation time 105760223020 ps
CPU time 6562.37 seconds
Started Feb 29 02:08:37 PM PST 24
Finished Feb 29 03:58:00 PM PST 24
Peak memory 354596 kb
Host smart-1073db18-2477-451d-8960-1101b04bd144
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975317668 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3975317668
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3850925409
Short name T320
Test name
Test status
Simulation time 11384426658 ps
CPU time 115.7 seconds
Started Feb 29 02:09:08 PM PST 24
Finished Feb 29 02:11:04 PM PST 24
Peak memory 256288 kb
Host smart-703bf868-512b-47d3-9551-d9dfa24f39d7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850925409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3850925409
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3556568502
Short name T294
Test name
Test status
Simulation time 116196146059 ps
CPU time 2199.51 seconds
Started Feb 29 02:05:51 PM PST 24
Finished Feb 29 02:42:30 PM PST 24
Peak memory 284424 kb
Host smart-7a5092de-eb8a-4efb-ab50-c0f4dd86efc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556568502 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3556568502
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2393110514
Short name T186
Test name
Test status
Simulation time 1842852850 ps
CPU time 62.56 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:36:41 PM PST 24
Peak memory 236796 kb
Host smart-b6edea72-902b-4851-b1da-6333e243f501
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2393110514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2393110514
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2301360683
Short name T171
Test name
Test status
Simulation time 745708463 ps
CPU time 99.62 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:37:14 PM PST 24
Peak memory 257300 kb
Host smart-aefe1fcf-27dc-483a-9db3-a240878a8667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2301360683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2301360683
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1101083177
Short name T183
Test name
Test status
Simulation time 2698016004 ps
CPU time 92.8 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:36:57 PM PST 24
Peak memory 236988 kb
Host smart-d157ad2b-1754-4888-9d8f-880762aeb980
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1101083177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1101083177
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2525029277
Short name T180
Test name
Test status
Simulation time 277088450 ps
CPU time 3.66 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 235792 kb
Host smart-ea25adca-9981-43ac-a054-0f6191c89e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2525029277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2525029277
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3714621020
Short name T158
Test name
Test status
Simulation time 8676822133 ps
CPU time 406.14 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:42:12 PM PST 24
Peak memory 265560 kb
Host smart-6519eeca-cab5-42d4-aae0-3d7c9ae39d55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3714621020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3714621020
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2643837057
Short name T189
Test name
Test status
Simulation time 220001212 ps
CPU time 4.59 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:29 PM PST 24
Peak memory 236700 kb
Host smart-a3091493-41ec-44dc-bfe8-6d8f5e1146a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2643837057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2643837057
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4123857434
Short name T178
Test name
Test status
Simulation time 317896545 ps
CPU time 20.51 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:33 PM PST 24
Peak memory 239680 kb
Host smart-5feab944-1d5b-4c69-908e-ca1c91916dc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4123857434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4123857434
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3044345969
Short name T188
Test name
Test status
Simulation time 31754993 ps
CPU time 2.76 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:15 PM PST 24
Peak memory 236820 kb
Host smart-fbee6088-99b2-4fed-804e-5dde8794bc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3044345969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3044345969
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2270004770
Short name T174
Test name
Test status
Simulation time 156193688 ps
CPU time 3.18 seconds
Started Feb 29 01:35:14 PM PST 24
Finished Feb 29 01:35:17 PM PST 24
Peak memory 237128 kb
Host smart-1867da9e-d543-4c62-95d7-866d45d4d2e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2270004770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2270004770
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2423508359
Short name T185
Test name
Test status
Simulation time 120008338 ps
CPU time 2.03 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:35:27 PM PST 24
Peak memory 236624 kb
Host smart-d90e2482-84aa-405b-b3ec-e34dc02e85f7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2423508359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2423508359
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.805649348
Short name T181
Test name
Test status
Simulation time 316039540 ps
CPU time 21.41 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:47 PM PST 24
Peak memory 240628 kb
Host smart-5370343e-9598-4053-8161-34b651514544
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=805649348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.805649348
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.203598481
Short name T182
Test name
Test status
Simulation time 236631639 ps
CPU time 25.99 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 240612 kb
Host smart-901b9e5c-4443-4113-a929-361141a9f652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=203598481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.203598481
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2587405603
Short name T195
Test name
Test status
Simulation time 299707054 ps
CPU time 30.78 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:29 PM PST 24
Peak memory 240588 kb
Host smart-d222a920-3292-4eb2-b375-112bdda00d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2587405603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2587405603
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2792440408
Short name T190
Test name
Test status
Simulation time 1315880795 ps
CPU time 23.57 seconds
Started Feb 29 01:35:02 PM PST 24
Finished Feb 29 01:35:26 PM PST 24
Peak memory 236952 kb
Host smart-84cb5475-94f1-47a5-a600-3d606a6756a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2792440408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2792440408
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.202098411
Short name T184
Test name
Test status
Simulation time 320463717 ps
CPU time 26.17 seconds
Started Feb 29 01:35:13 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 248784 kb
Host smart-a65dabe5-91a9-416a-bcf8-28606c7ff29c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=202098411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.202098411
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3070462434
Short name T24
Test name
Test status
Simulation time 12769218963 ps
CPU time 1251.01 seconds
Started Feb 29 02:06:58 PM PST 24
Finished Feb 29 02:27:50 PM PST 24
Peak memory 288972 kb
Host smart-76f0f3f8-5daf-4114-a95a-b9d96c924964
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070462434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3070462434
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.530097781
Short name T757
Test name
Test status
Simulation time 1150372584 ps
CPU time 125.38 seconds
Started Feb 29 01:35:05 PM PST 24
Finished Feb 29 01:37:11 PM PST 24
Peak memory 240468 kb
Host smart-1fa48596-dbad-4961-abd1-d68d192504cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=530097781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.530097781
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2860804401
Short name T749
Test name
Test status
Simulation time 8939564579 ps
CPU time 198.89 seconds
Started Feb 29 01:34:51 PM PST 24
Finished Feb 29 01:38:11 PM PST 24
Peak memory 240652 kb
Host smart-5ecd48ba-aea9-49fb-82ea-05167ea530bf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2860804401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2860804401
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2254258262
Short name T737
Test name
Test status
Simulation time 22941814 ps
CPU time 3.96 seconds
Started Feb 29 01:34:50 PM PST 24
Finished Feb 29 01:34:54 PM PST 24
Peak memory 240572 kb
Host smart-d096f540-2c6e-4c86-8752-22de727e4719
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2254258262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2254258262
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1181206298
Short name T803
Test name
Test status
Simulation time 221663388 ps
CPU time 5.01 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:54 PM PST 24
Peak memory 239172 kb
Host smart-0169a199-c49a-4417-bf6e-6c9bb8cb0fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181206298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1181206298
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.566940606
Short name T783
Test name
Test status
Simulation time 93208205 ps
CPU time 4.61 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:53 PM PST 24
Peak memory 240572 kb
Host smart-d3367f33-bb67-4852-99b6-40b4919fd0b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=566940606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.566940606
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2262520646
Short name T766
Test name
Test status
Simulation time 660151718 ps
CPU time 45.86 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:35:35 PM PST 24
Peak memory 248784 kb
Host smart-b20a26e5-a5f2-486c-952c-1d390172f16a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2262520646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2262520646
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3338421050
Short name T169
Test name
Test status
Simulation time 711097604 ps
CPU time 81.74 seconds
Started Feb 29 01:34:46 PM PST 24
Finished Feb 29 01:36:08 PM PST 24
Peak memory 257148 kb
Host smart-e3c16513-8ce9-49c9-b330-f09be42dfff9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3338421050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3338421050
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.800955938
Short name T720
Test name
Test status
Simulation time 249790988 ps
CPU time 16.48 seconds
Started Feb 29 01:34:50 PM PST 24
Finished Feb 29 01:35:06 PM PST 24
Peak memory 254684 kb
Host smart-d8f03783-4e03-4304-a7d1-71e01e939fcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=800955938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.800955938
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3215133057
Short name T722
Test name
Test status
Simulation time 649710360 ps
CPU time 41.09 seconds
Started Feb 29 01:34:48 PM PST 24
Finished Feb 29 01:35:29 PM PST 24
Peak memory 237028 kb
Host smart-6145e21e-c896-40b9-b092-65f34d4428a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3215133057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3215133057
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2444221499
Short name T826
Test name
Test status
Simulation time 3223082829 ps
CPU time 126.32 seconds
Started Feb 29 01:34:52 PM PST 24
Finished Feb 29 01:36:59 PM PST 24
Peak memory 240688 kb
Host smart-d39cb6f5-4250-411c-b675-8546a809a461
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2444221499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2444221499
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.555236770
Short name T222
Test name
Test status
Simulation time 1605198099 ps
CPU time 116.35 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:36:45 PM PST 24
Peak memory 236676 kb
Host smart-37d65c8c-7fb4-4477-8f9d-3ee96740ca68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=555236770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.555236770
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2132837870
Short name T831
Test name
Test status
Simulation time 201848108 ps
CPU time 4.92 seconds
Started Feb 29 01:35:15 PM PST 24
Finished Feb 29 01:35:20 PM PST 24
Peak memory 240456 kb
Host smart-3bde27fb-015e-44ce-a281-9abdad68abca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2132837870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2132837870
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.619235580
Short name T830
Test name
Test status
Simulation time 30375585 ps
CPU time 4.9 seconds
Started Feb 29 01:34:52 PM PST 24
Finished Feb 29 01:34:57 PM PST 24
Peak memory 239412 kb
Host smart-40ab4578-ef42-4bf5-82dd-1ae3f24b6f48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619235580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.619235580
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.3065698513
Short name T210
Test name
Test status
Simulation time 528694467 ps
CPU time 5.46 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:55 PM PST 24
Peak memory 236520 kb
Host smart-85ceb0ba-1c28-4505-938b-1da801e3ffe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3065698513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.3065698513
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.4105017409
Short name T780
Test name
Test status
Simulation time 7756216 ps
CPU time 1.34 seconds
Started Feb 29 01:34:51 PM PST 24
Finished Feb 29 01:34:53 PM PST 24
Peak memory 234860 kb
Host smart-9176ae9f-e17e-4112-87e7-4272188ad519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4105017409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.4105017409
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.315381428
Short name T738
Test name
Test status
Simulation time 192497646 ps
CPU time 25.11 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:35:14 PM PST 24
Peak memory 244804 kb
Host smart-85cae006-9ed7-4424-af65-4648525c4365
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=315381428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.315381428
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.4192297108
Short name T170
Test name
Test status
Simulation time 5700163249 ps
CPU time 719.21 seconds
Started Feb 29 01:34:48 PM PST 24
Finished Feb 29 01:46:47 PM PST 24
Peak memory 273760 kb
Host smart-f20a670c-bdf1-4b30-a13b-75402c86760d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192297108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.4192297108
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2080913754
Short name T714
Test name
Test status
Simulation time 67115713 ps
CPU time 7.5 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:57 PM PST 24
Peak memory 248624 kb
Host smart-bfff6b9e-20a5-4f4b-9eab-c1bea423cc2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2080913754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2080913754
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.908012855
Short name T717
Test name
Test status
Simulation time 141133731 ps
CPU time 10.09 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:32 PM PST 24
Peak memory 253904 kb
Host smart-619621c1-f94d-4898-afce-85892f49b819
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908012855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.908012855
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3310350773
Short name T801
Test name
Test status
Simulation time 188598194 ps
CPU time 9.24 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:35 PM PST 24
Peak memory 236688 kb
Host smart-441c3d65-f4fa-4780-adbc-f01296a3f796
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3310350773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3310350773
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.825293344
Short name T768
Test name
Test status
Simulation time 1022524450 ps
CPU time 21.11 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:46 PM PST 24
Peak memory 244852 kb
Host smart-8068874f-d982-46c7-bd8c-7be2be2f8765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=825293344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.825293344
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.243264802
Short name T167
Test name
Test status
Simulation time 14657474593 ps
CPU time 131.8 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:37:36 PM PST 24
Peak memory 256276 kb
Host smart-68611d91-1451-4b90-93cc-e320a84d9fb3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=243264802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.243264802
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2732072608
Short name T828
Test name
Test status
Simulation time 130100979 ps
CPU time 9.55 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:34 PM PST 24
Peak memory 252480 kb
Host smart-3c43e9dc-0192-4977-b1e8-ccc0971387ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2732072608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2732072608
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2652599914
Short name T223
Test name
Test status
Simulation time 249268390 ps
CPU time 5.96 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 248892 kb
Host smart-7a75a539-f15a-4202-bddf-d7758846d212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652599914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2652599914
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4173130529
Short name T724
Test name
Test status
Simulation time 134651547 ps
CPU time 10.46 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:35 PM PST 24
Peak memory 240744 kb
Host smart-a694d981-7d74-48c3-a6ff-3de8959f24bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4173130529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4173130529
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3501088868
Short name T770
Test name
Test status
Simulation time 8424657 ps
CPU time 1.33 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:25 PM PST 24
Peak memory 235760 kb
Host smart-af6b9873-6285-4826-8331-2b485dd3d698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3501088868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3501088868
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3413227601
Short name T764
Test name
Test status
Simulation time 324123167 ps
CPU time 14.95 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 248728 kb
Host smart-b131b87c-3e43-4dff-9c84-0e2c15545ab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3413227601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3413227601
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3295507121
Short name T147
Test name
Test status
Simulation time 4698801115 ps
CPU time 156.53 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:38:01 PM PST 24
Peak memory 257428 kb
Host smart-9582a510-2405-4bce-8e82-dfed81352d43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3295507121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3295507121
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.888858802
Short name T811
Test name
Test status
Simulation time 280678947 ps
CPU time 18.43 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:43 PM PST 24
Peak memory 251912 kb
Host smart-c7aa8b2e-facb-4d3c-8436-9fb48edb5c75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=888858802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.888858802
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4223586297
Short name T725
Test name
Test status
Simulation time 112223443 ps
CPU time 4.49 seconds
Started Feb 29 01:35:26 PM PST 24
Finished Feb 29 01:35:31 PM PST 24
Peak memory 240124 kb
Host smart-91c7723e-97d1-4577-82e4-7c382f87d1d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223586297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4223586297
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.243744536
Short name T193
Test name
Test status
Simulation time 220606770 ps
CPU time 4.68 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 239676 kb
Host smart-8f18eb9f-1016-41aa-827a-5635a736b512
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=243744536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.243744536
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.784667140
Short name T781
Test name
Test status
Simulation time 252439354 ps
CPU time 18.93 seconds
Started Feb 29 01:35:31 PM PST 24
Finished Feb 29 01:35:50 PM PST 24
Peak memory 244872 kb
Host smart-6540f3c0-28cb-42e4-84a4-1f52031c5122
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=784667140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.784667140
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.301038120
Short name T274
Test name
Test status
Simulation time 302510237 ps
CPU time 17.89 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 248216 kb
Host smart-aba8b909-bfe4-424b-9183-9f57e90fd777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301038120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.301038120
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.935791843
Short name T822
Test name
Test status
Simulation time 153727526 ps
CPU time 13.11 seconds
Started Feb 29 01:35:28 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 249960 kb
Host smart-193dbd79-9566-4c49-82a8-6d16c18eacd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935791843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.935791843
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2195857507
Short name T800
Test name
Test status
Simulation time 109936268 ps
CPU time 5.6 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:32 PM PST 24
Peak memory 236604 kb
Host smart-028b7aa6-50cf-4944-90b1-037ec8401b79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2195857507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2195857507
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3862749341
Short name T721
Test name
Test status
Simulation time 20435721 ps
CPU time 1.93 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:27 PM PST 24
Peak memory 234900 kb
Host smart-9ed8dfc4-500a-4c5a-9e37-67c5a3601cf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3862749341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3862749341
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2575326088
Short name T728
Test name
Test status
Simulation time 7278628076 ps
CPU time 37.44 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:36:02 PM PST 24
Peak memory 240692 kb
Host smart-7c7088ae-b6df-4d88-9f60-0076bc8297b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2575326088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2575326088
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3958240243
Short name T145
Test name
Test status
Simulation time 5074616855 ps
CPU time 629.22 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:45:55 PM PST 24
Peak memory 272612 kb
Host smart-e1a6d3ff-8b48-48f3-a466-26d2614d1347
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958240243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3958240243
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.275169986
Short name T727
Test name
Test status
Simulation time 1031651284 ps
CPU time 19.99 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:45 PM PST 24
Peak memory 247524 kb
Host smart-c40ab37c-4541-4cc3-b673-f18a3cc89e87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=275169986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.275169986
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2375411948
Short name T786
Test name
Test status
Simulation time 80779399 ps
CPU time 8.12 seconds
Started Feb 29 01:35:24 PM PST 24
Finished Feb 29 01:35:33 PM PST 24
Peak memory 240292 kb
Host smart-6a60afc2-d627-46f9-9d0c-7acf3d6692e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375411948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2375411948
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2350447811
Short name T758
Test name
Test status
Simulation time 47901180 ps
CPU time 4.7 seconds
Started Feb 29 01:35:31 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 235788 kb
Host smart-0dfd6d7f-85e4-419e-b76a-e433de8f465d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2350447811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2350447811
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3776743063
Short name T175
Test name
Test status
Simulation time 31534720 ps
CPU time 1.32 seconds
Started Feb 29 01:35:23 PM PST 24
Finished Feb 29 01:35:26 PM PST 24
Peak memory 235816 kb
Host smart-9838d532-c496-4b3c-8b12-6593df2216ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3776743063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3776743063
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.716517737
Short name T752
Test name
Test status
Simulation time 2057801010 ps
CPU time 44.01 seconds
Started Feb 29 01:35:28 PM PST 24
Finished Feb 29 01:36:12 PM PST 24
Peak memory 248840 kb
Host smart-b42dad1d-ad89-4f63-85a1-5c9c7dc3c6a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=716517737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.716517737
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3746741441
Short name T137
Test name
Test status
Simulation time 969431985 ps
CPU time 91.8 seconds
Started Feb 29 01:35:27 PM PST 24
Finished Feb 29 01:36:59 PM PST 24
Peak memory 257264 kb
Host smart-14a394e6-fbd7-450f-b4b3-e93c95b58ee7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3746741441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3746741441
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3495310438
Short name T802
Test name
Test status
Simulation time 125708640 ps
CPU time 8.77 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:34 PM PST 24
Peak memory 252352 kb
Host smart-348535e6-d3da-44ce-ad68-abb8067d3f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3495310438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3495310438
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.4031930417
Short name T191
Test name
Test status
Simulation time 1213005591 ps
CPU time 42.02 seconds
Started Feb 29 01:35:29 PM PST 24
Finished Feb 29 01:36:11 PM PST 24
Peak memory 236920 kb
Host smart-51d85107-32db-4dbb-8cfb-e350dc8572e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4031930417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.4031930417
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3663096864
Short name T376
Test name
Test status
Simulation time 32310254 ps
CPU time 4.89 seconds
Started Feb 29 01:35:22 PM PST 24
Finished Feb 29 01:35:29 PM PST 24
Peak memory 239856 kb
Host smart-795b2c7b-3163-48b9-9353-b1ddfb7e6691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663096864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3663096864
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2967659319
Short name T782
Test name
Test status
Simulation time 32871438 ps
CPU time 7.07 seconds
Started Feb 29 01:35:28 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 236700 kb
Host smart-8088a498-6d1b-44e9-9371-5e27ccde7405
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2967659319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2967659319
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1389114177
Short name T750
Test name
Test status
Simulation time 23757653 ps
CPU time 1.37 seconds
Started Feb 29 01:35:30 PM PST 24
Finished Feb 29 01:35:32 PM PST 24
Peak memory 236692 kb
Host smart-79777faa-349e-4ae3-9989-588b63c4b6f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1389114177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1389114177
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2494047707
Short name T762
Test name
Test status
Simulation time 181588043 ps
CPU time 13 seconds
Started Feb 29 01:35:31 PM PST 24
Finished Feb 29 01:35:44 PM PST 24
Peak memory 239736 kb
Host smart-cf60f878-60ae-44f6-b2db-548ca2a5da64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2494047707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2494047707
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2005049118
Short name T796
Test name
Test status
Simulation time 79397516 ps
CPU time 5.83 seconds
Started Feb 29 01:35:28 PM PST 24
Finished Feb 29 01:35:34 PM PST 24
Peak memory 248888 kb
Host smart-901c3d5a-e38b-47a4-9ad4-030a991a3df8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2005049118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2005049118
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3242296050
Short name T732
Test name
Test status
Simulation time 199828236 ps
CPU time 8.49 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 239108 kb
Host smart-923ef600-8987-44f5-877a-71ec97d0bb21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242296050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3242296050
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2853390635
Short name T212
Test name
Test status
Simulation time 34786672 ps
CPU time 4.21 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 236532 kb
Host smart-0f53f462-9dbc-4c2b-a2aa-b5bf135419ba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2853390635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2853390635
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3257161574
Short name T792
Test name
Test status
Simulation time 9806605 ps
CPU time 1.52 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 236708 kb
Host smart-7a156767-2ffa-46fa-b08a-48a4dd13a4a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3257161574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3257161574
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.360622825
Short name T214
Test name
Test status
Simulation time 1767799171 ps
CPU time 20.33 seconds
Started Feb 29 01:35:33 PM PST 24
Finished Feb 29 01:35:54 PM PST 24
Peak memory 243964 kb
Host smart-4863ef18-dc00-4ac9-b968-793662b5b785
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=360622825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.360622825
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1340949043
Short name T153
Test name
Test status
Simulation time 33559041392 ps
CPU time 149.65 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:37:56 PM PST 24
Peak memory 256812 kb
Host smart-2369263a-5b05-46cb-a833-e0772554a790
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1340949043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1340949043
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4281958725
Short name T165
Test name
Test status
Simulation time 60657923651 ps
CPU time 1014.9 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:52:20 PM PST 24
Peak memory 265548 kb
Host smart-7407741a-aa27-452e-ac78-b1a5047e77ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281958725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4281958725
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.317636307
Short name T813
Test name
Test status
Simulation time 1254552193 ps
CPU time 8.39 seconds
Started Feb 29 01:35:25 PM PST 24
Finished Feb 29 01:35:34 PM PST 24
Peak memory 248868 kb
Host smart-0cea0a28-3f82-4870-b412-1a50f9ed528c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=317636307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.317636307
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.258441185
Short name T789
Test name
Test status
Simulation time 148573510 ps
CPU time 6.15 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 239288 kb
Host smart-cc9a55c7-c1ac-48da-8d73-b3332c92b188
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258441185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.258441185
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3448236223
Short name T194
Test name
Test status
Simulation time 267161759 ps
CPU time 5.58 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 240524 kb
Host smart-b7253cf3-2e88-4668-a612-66d5445fc415
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3448236223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3448236223
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3202461790
Short name T730
Test name
Test status
Simulation time 26069002 ps
CPU time 1.41 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 235760 kb
Host smart-a0897bb5-7d00-4151-ada8-c8351386af6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202461790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3202461790
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3289748279
Short name T812
Test name
Test status
Simulation time 260129045 ps
CPU time 20.98 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:58 PM PST 24
Peak memory 244848 kb
Host smart-af86c056-44ca-464f-99cf-1815b6884447
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3289748279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3289748279
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.1084619903
Short name T163
Test name
Test status
Simulation time 14917185317 ps
CPU time 175.56 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:38:32 PM PST 24
Peak memory 265724 kb
Host smart-44141b6d-0300-4252-9c57-83b7439d5633
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1084619903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.1084619903
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.222491371
Short name T164
Test name
Test status
Simulation time 5241986952 ps
CPU time 264.51 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:39:59 PM PST 24
Peak memory 265708 kb
Host smart-93538d13-6739-4501-afc9-a2d599fd75aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222491371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.222491371
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.22677741
Short name T829
Test name
Test status
Simulation time 881263783 ps
CPU time 16.52 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:51 PM PST 24
Peak memory 248728 kb
Host smart-fd3a3caa-e98c-41c4-9d34-824fec1e2940
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=22677741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.22677741
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.307207646
Short name T716
Test name
Test status
Simulation time 562800309 ps
CPU time 9.3 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:50 PM PST 24
Peak memory 251036 kb
Host smart-ba8b1439-d011-4a1d-9708-f04f9997e13f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307207646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.307207646
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.544587713
Short name T209
Test name
Test status
Simulation time 445088173 ps
CPU time 11.21 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:48 PM PST 24
Peak memory 236680 kb
Host smart-dd0beab2-2e56-4b1f-800f-350138934711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=544587713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.544587713
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3440471314
Short name T795
Test name
Test status
Simulation time 32612764 ps
CPU time 1.32 seconds
Started Feb 29 01:35:33 PM PST 24
Finished Feb 29 01:35:35 PM PST 24
Peak memory 234848 kb
Host smart-72056f8d-7419-4009-bdb7-0fbe2bd37f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3440471314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3440471314
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3653659098
Short name T731
Test name
Test status
Simulation time 176387223 ps
CPU time 21.89 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:59 PM PST 24
Peak memory 243976 kb
Host smart-5cd4e0e4-438f-475b-8bf3-e8ebf3875680
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3653659098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3653659098
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.555879191
Short name T159
Test name
Test status
Simulation time 9213495573 ps
CPU time 293.6 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:40:28 PM PST 24
Peak memory 270160 kb
Host smart-8837eb81-4985-4074-9f87-dc488b8fa8f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555879191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.555879191
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1524055135
Short name T713
Test name
Test status
Simulation time 95392258 ps
CPU time 3.78 seconds
Started Feb 29 01:35:33 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 249628 kb
Host smart-44dc7754-40fe-4559-92f9-72c607014a79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1524055135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1524055135
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3292798728
Short name T772
Test name
Test status
Simulation time 44553741 ps
CPU time 2.28 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 236648 kb
Host smart-1a3f0903-49d6-486b-bbfc-0906929f2e7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3292798728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3292798728
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3160274103
Short name T824
Test name
Test status
Simulation time 59448204 ps
CPU time 4.74 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 241552 kb
Host smart-a3169199-69d7-42d5-8d9e-d704bb4b7a71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160274103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3160274103
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1943528131
Short name T745
Test name
Test status
Simulation time 68095885 ps
CPU time 3.7 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:41 PM PST 24
Peak memory 240452 kb
Host smart-b7bc13ad-4fb8-43f9-be02-3312f085897e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1943528131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1943528131
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1943608695
Short name T776
Test name
Test status
Simulation time 25787105 ps
CPU time 1.54 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 236704 kb
Host smart-ff23ca82-a313-44f6-a0fb-5fbf31f8dd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1943608695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1943608695
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2943802249
Short name T208
Test name
Test status
Simulation time 183466153 ps
CPU time 22.17 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:58 PM PST 24
Peak memory 243856 kb
Host smart-037a39ac-abd6-40dc-8c87-990c75b1886e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2943802249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2943802249
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.465880687
Short name T161
Test name
Test status
Simulation time 2963911892 ps
CPU time 101.25 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:37:19 PM PST 24
Peak memory 266560 kb
Host smart-dba5294d-a28f-41df-b5c1-c7e1667105ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=465880687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.465880687
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.148106823
Short name T138
Test name
Test status
Simulation time 108476073326 ps
CPU time 1153.12 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:54:48 PM PST 24
Peak memory 265556 kb
Host smart-97eab41a-6d7b-4df3-b25c-aa25cada77f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148106823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.148106823
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3780209728
Short name T747
Test name
Test status
Simulation time 118658770 ps
CPU time 8.63 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:43 PM PST 24
Peak memory 248812 kb
Host smart-9d68e029-d8ec-46b1-a306-a96a8007b99e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3780209728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3780209728
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2828723709
Short name T735
Test name
Test status
Simulation time 6587441929 ps
CPU time 111.58 seconds
Started Feb 29 01:34:52 PM PST 24
Finished Feb 29 01:36:44 PM PST 24
Peak memory 240656 kb
Host smart-c4a217d2-5221-408b-bfaa-be143b466f8d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2828723709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2828723709
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2939169859
Short name T809
Test name
Test status
Simulation time 6280747137 ps
CPU time 211.72 seconds
Started Feb 29 01:34:50 PM PST 24
Finished Feb 29 01:38:22 PM PST 24
Peak memory 236716 kb
Host smart-ce6648d0-a43d-47f5-888c-e15efe62dcdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2939169859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2939169859
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3263269176
Short name T765
Test name
Test status
Simulation time 1333050564 ps
CPU time 10.78 seconds
Started Feb 29 01:35:04 PM PST 24
Finished Feb 29 01:35:15 PM PST 24
Peak memory 240468 kb
Host smart-7125307e-81eb-47e5-a5a7-c479ad6e5b2f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3263269176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3263269176
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1859099200
Short name T715
Test name
Test status
Simulation time 62507660 ps
CPU time 6.58 seconds
Started Feb 29 01:35:04 PM PST 24
Finished Feb 29 01:35:11 PM PST 24
Peak memory 240532 kb
Host smart-2c8840ba-de74-4d7e-b88f-05e625c7bc0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859099200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1859099200
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.149798804
Short name T823
Test name
Test status
Simulation time 152477448 ps
CPU time 10.33 seconds
Started Feb 29 01:35:05 PM PST 24
Finished Feb 29 01:35:15 PM PST 24
Peak memory 240468 kb
Host smart-e6fafca1-2673-4718-b11d-8065dafdffda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=149798804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.149798804
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.606129266
Short name T734
Test name
Test status
Simulation time 11106833 ps
CPU time 1.56 seconds
Started Feb 29 01:35:05 PM PST 24
Finished Feb 29 01:35:07 PM PST 24
Peak memory 236560 kb
Host smart-85e6c96e-5ade-430e-ac1a-f0a53d029141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=606129266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.606129266
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.562098587
Short name T754
Test name
Test status
Simulation time 1550360244 ps
CPU time 24.63 seconds
Started Feb 29 01:35:05 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 240456 kb
Host smart-2856bb5d-9393-4738-a279-743d911d00aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=562098587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.562098587
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3215487381
Short name T166
Test name
Test status
Simulation time 15690487899 ps
CPU time 286.39 seconds
Started Feb 29 01:35:04 PM PST 24
Finished Feb 29 01:39:51 PM PST 24
Peak memory 265444 kb
Host smart-4a745c24-a8c6-44dd-971f-3b5bd123b547
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3215487381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3215487381
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.6030007
Short name T142
Test name
Test status
Simulation time 57372019770 ps
CPU time 936.18 seconds
Started Feb 29 01:34:52 PM PST 24
Finished Feb 29 01:50:29 PM PST 24
Peak memory 265572 kb
Host smart-62a22c21-4c74-41ff-993d-5d9853bdbbd3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6030007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_shadow_reg_errors_with_csr_rw.6030007
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1302248694
Short name T816
Test name
Test status
Simulation time 992380661 ps
CPU time 19.22 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:35:09 PM PST 24
Peak memory 249016 kb
Host smart-84f8d747-11d5-401e-87c6-d7c97417f03e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302248694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1302248694
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1184406342
Short name T172
Test name
Test status
Simulation time 105067195 ps
CPU time 2.7 seconds
Started Feb 29 01:34:49 PM PST 24
Finished Feb 29 01:34:52 PM PST 24
Peak memory 235716 kb
Host smart-f5e3f367-ac54-4ad6-9a4d-6f6f8d12247e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1184406342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1184406342
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.230650378
Short name T779
Test name
Test status
Simulation time 10561196 ps
CPU time 1.32 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 234784 kb
Host smart-d669eb6d-b361-47a4-9d1a-6510a9c075bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=230650378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.230650378
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1332023471
Short name T283
Test name
Test status
Simulation time 49853987 ps
CPU time 1.32 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 236668 kb
Host smart-b542df8c-582a-4e8e-ade5-850a272fc14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1332023471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1332023471
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2391351829
Short name T761
Test name
Test status
Simulation time 20035112 ps
CPU time 1.17 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:38 PM PST 24
Peak memory 236720 kb
Host smart-7f96b1f9-c110-4506-8490-345499b31c6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2391351829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2391351829
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2581402339
Short name T755
Test name
Test status
Simulation time 24584592 ps
CPU time 1.5 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 235792 kb
Host smart-04db08b6-7746-4227-a8a6-edecb1637483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2581402339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2581402339
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1768418781
Short name T367
Test name
Test status
Simulation time 14469645 ps
CPU time 1.35 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 234824 kb
Host smart-96603ab8-c89b-444b-b5e8-7905a8048790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1768418781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1768418781
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.405254833
Short name T771
Test name
Test status
Simulation time 17247559 ps
CPU time 1.52 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 236712 kb
Host smart-b66348e3-4bd0-4280-b337-7cb24e5e5b31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=405254833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.405254833
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2740191290
Short name T372
Test name
Test status
Simulation time 33209540 ps
CPU time 1.49 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:38 PM PST 24
Peak memory 236716 kb
Host smart-fb57f560-bc2f-4c10-85a2-8aa0ca0d312d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740191290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2740191290
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2369199895
Short name T369
Test name
Test status
Simulation time 11638723 ps
CPU time 1.52 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 235800 kb
Host smart-2cafec4e-1e0e-4bc1-8563-95cd7f606791
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369199895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2369199895
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3257774876
Short name T797
Test name
Test status
Simulation time 15925108 ps
CPU time 1.31 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 235812 kb
Host smart-4c1b53ff-20d9-4e8a-85c5-2a49da6ad909
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3257774876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3257774876
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.851320537
Short name T778
Test name
Test status
Simulation time 19018911 ps
CPU time 1.46 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 235796 kb
Host smart-a7760171-365a-4da6-be98-3375219063dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=851320537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.851320537
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.390594491
Short name T377
Test name
Test status
Simulation time 1721393043 ps
CPU time 118.6 seconds
Started Feb 29 01:34:57 PM PST 24
Finished Feb 29 01:36:57 PM PST 24
Peak memory 236668 kb
Host smart-01d918af-08f2-4340-800d-1d715e5c9e84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=390594491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.390594491
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2666618044
Short name T718
Test name
Test status
Simulation time 5835560023 ps
CPU time 109.32 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:36:48 PM PST 24
Peak memory 236668 kb
Host smart-64f0080e-05d1-486a-a18e-f4043d66974d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2666618044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2666618044
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.284793140
Short name T820
Test name
Test status
Simulation time 46487467 ps
CPU time 6.68 seconds
Started Feb 29 01:34:57 PM PST 24
Finished Feb 29 01:35:05 PM PST 24
Peak memory 240584 kb
Host smart-da567773-962c-4ee7-89c9-aae0b4cde651
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=284793140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.284793140
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3595068205
Short name T379
Test name
Test status
Simulation time 309303777 ps
CPU time 8.14 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:07 PM PST 24
Peak memory 240484 kb
Host smart-de00e5ec-3d03-48e6-af01-38040287ce88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595068205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3595068205
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2033621889
Short name T211
Test name
Test status
Simulation time 33965573 ps
CPU time 6.98 seconds
Started Feb 29 01:35:05 PM PST 24
Finished Feb 29 01:35:12 PM PST 24
Peak memory 240464 kb
Host smart-930cb71d-5648-4bc9-9b09-ec5ebe9ba577
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2033621889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2033621889
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2303855851
Short name T753
Test name
Test status
Simulation time 16528987 ps
CPU time 1.8 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:35:04 PM PST 24
Peak memory 235904 kb
Host smart-df4a74d1-2b23-4c57-829a-4a7226568519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2303855851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2303855851
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2395993367
Short name T817
Test name
Test status
Simulation time 621521233 ps
CPU time 39.54 seconds
Started Feb 29 01:34:57 PM PST 24
Finished Feb 29 01:35:37 PM PST 24
Peak memory 240344 kb
Host smart-fd84db77-e2e7-44d2-a777-e0a2c0bca0f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2395993367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2395993367
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1389921097
Short name T152
Test name
Test status
Simulation time 1926088453 ps
CPU time 201.49 seconds
Started Feb 29 01:35:03 PM PST 24
Finished Feb 29 01:38:25 PM PST 24
Peak memory 271728 kb
Host smart-2b408650-309e-4dda-8211-5463d28b64a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1389921097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1389921097
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1530628896
Short name T712
Test name
Test status
Simulation time 1015326299 ps
CPU time 19.96 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:19 PM PST 24
Peak memory 248788 kb
Host smart-7ca25fa2-9e33-4f99-abe6-281e8d82e1e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530628896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1530628896
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2089953156
Short name T759
Test name
Test status
Simulation time 6775731 ps
CPU time 1.57 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 236852 kb
Host smart-a60a3026-d473-4c66-9662-0bd5f6d23872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2089953156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2089953156
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1866914712
Short name T815
Test name
Test status
Simulation time 12926623 ps
CPU time 1.36 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 234868 kb
Host smart-05fcd7a7-ec5e-4ab4-8f7b-3c2d06e89a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1866914712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1866914712
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1355659236
Short name T798
Test name
Test status
Simulation time 9230439 ps
CPU time 1.52 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 234916 kb
Host smart-5d003836-5c8c-49b3-af05-2c63f5ffb476
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355659236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1355659236
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2419536004
Short name T741
Test name
Test status
Simulation time 15626350 ps
CPU time 1.51 seconds
Started Feb 29 01:35:34 PM PST 24
Finished Feb 29 01:35:35 PM PST 24
Peak memory 236000 kb
Host smart-5629323d-12d6-4091-9a2e-a1ce81b4c42a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2419536004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2419536004
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3786621876
Short name T804
Test name
Test status
Simulation time 11391778 ps
CPU time 1.69 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 236708 kb
Host smart-9695561e-bbdd-4069-b6d2-d2302572679a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3786621876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3786621876
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2419419530
Short name T370
Test name
Test status
Simulation time 9578615 ps
CPU time 1.6 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 235820 kb
Host smart-757c8625-5fa9-4c5a-902c-36d3c181376f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2419419530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2419419530
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.133912862
Short name T790
Test name
Test status
Simulation time 6771372 ps
CPU time 1.54 seconds
Started Feb 29 01:35:39 PM PST 24
Finished Feb 29 01:35:41 PM PST 24
Peak memory 235856 kb
Host smart-707bc9d7-eaa0-4956-8f9c-59e6ebf399f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=133912862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.133912862
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2573736879
Short name T777
Test name
Test status
Simulation time 12735605 ps
CPU time 1.35 seconds
Started Feb 29 01:35:35 PM PST 24
Finished Feb 29 01:35:36 PM PST 24
Peak memory 235812 kb
Host smart-ea1f7a79-6fb4-4c84-84f4-5cfaaf93a241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2573736879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2573736879
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1134276919
Short name T760
Test name
Test status
Simulation time 13879296 ps
CPU time 1.31 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 235808 kb
Host smart-2539718f-cfc2-4360-85a1-cb8800730cb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1134276919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1134276919
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3647968064
Short name T785
Test name
Test status
Simulation time 6798528 ps
CPU time 1.47 seconds
Started Feb 29 01:35:36 PM PST 24
Finished Feb 29 01:35:38 PM PST 24
Peak memory 235740 kb
Host smart-2d53a584-c8a2-459d-bd17-18237cdd482b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647968064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3647968064
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1520005138
Short name T769
Test name
Test status
Simulation time 13086678410 ps
CPU time 240.72 seconds
Started Feb 29 01:35:02 PM PST 24
Finished Feb 29 01:39:03 PM PST 24
Peak memory 240692 kb
Host smart-f7476b77-4304-4ea6-9ad0-5f7758e82703
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1520005138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1520005138
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.583164292
Short name T791
Test name
Test status
Simulation time 22863456615 ps
CPU time 402.94 seconds
Started Feb 29 01:34:59 PM PST 24
Finished Feb 29 01:41:42 PM PST 24
Peak memory 236648 kb
Host smart-3add6e43-eb76-429c-b486-9cadff8ad8b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=583164292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.583164292
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2861538169
Short name T819
Test name
Test status
Simulation time 109281292 ps
CPU time 9.18 seconds
Started Feb 29 01:35:02 PM PST 24
Finished Feb 29 01:35:12 PM PST 24
Peak memory 240584 kb
Host smart-ecc1460c-4a26-4de5-8681-d7b6bf6404fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2861538169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2861538169
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1178963691
Short name T793
Test name
Test status
Simulation time 1486354368 ps
CPU time 9.49 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:07 PM PST 24
Peak memory 254260 kb
Host smart-8e30df5a-1f11-4703-ab77-169f10ab5fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178963691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1178963691
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1996811181
Short name T794
Test name
Test status
Simulation time 232620938 ps
CPU time 5.32 seconds
Started Feb 29 01:35:02 PM PST 24
Finished Feb 29 01:35:08 PM PST 24
Peak memory 240420 kb
Host smart-5d12e3e9-5572-4897-994b-6ef95eac9a0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1996811181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1996811181
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.560473115
Short name T742
Test name
Test status
Simulation time 12105800 ps
CPU time 1.34 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:34:59 PM PST 24
Peak memory 235808 kb
Host smart-be276507-e665-42c8-959e-13756d2aba17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560473115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.560473115
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3730335751
Short name T746
Test name
Test status
Simulation time 354672850 ps
CPU time 23.13 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:35:25 PM PST 24
Peak memory 240604 kb
Host smart-9c829d42-b6ff-44bb-ac5d-e6b6d20880f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3730335751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3730335751
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3282582027
Short name T160
Test name
Test status
Simulation time 21962698232 ps
CPU time 400.09 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:41:39 PM PST 24
Peak memory 265532 kb
Host smart-8956d07f-df65-4b1e-a008-c2c5ae8ca77b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3282582027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3282582027
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2120517108
Short name T134
Test name
Test status
Simulation time 24522884964 ps
CPU time 499.93 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:43:18 PM PST 24
Peak memory 265580 kb
Host smart-894d83ed-4c69-473e-b8a7-3b924145b4d7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120517108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2120517108
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2570323371
Short name T723
Test name
Test status
Simulation time 279707504 ps
CPU time 12.21 seconds
Started Feb 29 01:34:59 PM PST 24
Finished Feb 29 01:35:11 PM PST 24
Peak memory 248684 kb
Host smart-4e8a08e9-2fc3-4491-a8cd-ced11a3aa857
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2570323371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2570323371
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2907315132
Short name T368
Test name
Test status
Simulation time 14662370 ps
CPU time 1.33 seconds
Started Feb 29 01:35:42 PM PST 24
Finished Feb 29 01:35:44 PM PST 24
Peak memory 235696 kb
Host smart-23ef3ee4-4ac0-4d50-aedb-cbb18d8d99c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2907315132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2907315132
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3023160819
Short name T751
Test name
Test status
Simulation time 9791800 ps
CPU time 1.38 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:42 PM PST 24
Peak memory 234992 kb
Host smart-cbb1b3bc-2b4b-42e3-a760-897b18edc03e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3023160819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3023160819
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3278657414
Short name T784
Test name
Test status
Simulation time 11529980 ps
CPU time 1.41 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 236720 kb
Host smart-ca7b5e91-3130-444a-b57a-ea1ca6908a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3278657414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3278657414
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2132178403
Short name T827
Test name
Test status
Simulation time 13500029 ps
CPU time 1.33 seconds
Started Feb 29 01:35:39 PM PST 24
Finished Feb 29 01:35:41 PM PST 24
Peak memory 235896 kb
Host smart-9080c3b0-6b31-409d-9caa-a5f49cc53d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2132178403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2132178403
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.806985900
Short name T806
Test name
Test status
Simulation time 14839471 ps
CPU time 1.41 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:39 PM PST 24
Peak memory 236696 kb
Host smart-ab49d17c-ca6b-4880-9fdc-c628a84888a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=806985900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.806985900
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.701496726
Short name T767
Test name
Test status
Simulation time 11418792 ps
CPU time 1.22 seconds
Started Feb 29 01:35:37 PM PST 24
Finished Feb 29 01:35:38 PM PST 24
Peak memory 235808 kb
Host smart-39db9976-9d1f-4ec9-b9b5-5026af94a0f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=701496726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.701496726
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1824920069
Short name T821
Test name
Test status
Simulation time 6457573 ps
CPU time 1.39 seconds
Started Feb 29 01:35:38 PM PST 24
Finished Feb 29 01:35:40 PM PST 24
Peak memory 234912 kb
Host smart-1759c0d1-e94c-4521-a3d9-c1ba902a8d02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1824920069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1824920069
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.450978287
Short name T744
Test name
Test status
Simulation time 26601251 ps
CPU time 1.73 seconds
Started Feb 29 01:35:40 PM PST 24
Finished Feb 29 01:35:43 PM PST 24
Peak memory 236580 kb
Host smart-86e0cc9b-7daa-438c-aa33-703c9a1401e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=450978287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.450978287
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1261893504
Short name T808
Test name
Test status
Simulation time 13700320 ps
CPU time 1.54 seconds
Started Feb 29 01:35:42 PM PST 24
Finished Feb 29 01:35:44 PM PST 24
Peak memory 235880 kb
Host smart-530b447c-a2d3-49fe-88d4-9411d079f98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1261893504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1261893504
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2311589145
Short name T373
Test name
Test status
Simulation time 9830275 ps
CPU time 1.64 seconds
Started Feb 29 01:35:41 PM PST 24
Finished Feb 29 01:35:43 PM PST 24
Peak memory 235832 kb
Host smart-5bbab091-a75d-49d2-9e27-e7d5a6ca080d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2311589145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2311589145
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2514058021
Short name T192
Test name
Test status
Simulation time 51242047 ps
CPU time 8.93 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:07 PM PST 24
Peak memory 249832 kb
Host smart-bff65515-5507-4eaf-bf96-06caf3bffe92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514058021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2514058021
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1118458087
Short name T221
Test name
Test status
Simulation time 65632732 ps
CPU time 4.86 seconds
Started Feb 29 01:34:56 PM PST 24
Finished Feb 29 01:35:03 PM PST 24
Peak memory 236648 kb
Host smart-8f13138f-8bb3-46f5-b475-a5818de62ed6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1118458087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1118458087
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.391410307
Short name T748
Test name
Test status
Simulation time 9392514 ps
CPU time 1.55 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:35:04 PM PST 24
Peak memory 235804 kb
Host smart-d63d169f-2e45-48ad-b73f-684e59383ffc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=391410307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.391410307
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2020960728
Short name T213
Test name
Test status
Simulation time 2605651056 ps
CPU time 44.83 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:35:47 PM PST 24
Peak memory 248848 kb
Host smart-0361c9eb-c695-41ad-83b2-a6a45c8169ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2020960728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2020960728
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3123439728
Short name T155
Test name
Test status
Simulation time 940008841 ps
CPU time 127.92 seconds
Started Feb 29 01:35:00 PM PST 24
Finished Feb 29 01:37:10 PM PST 24
Peak memory 266908 kb
Host smart-63950ecf-03b8-40de-993f-f9c1f940b14d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3123439728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3123439728
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3868898219
Short name T805
Test name
Test status
Simulation time 6182236304 ps
CPU time 499.73 seconds
Started Feb 29 01:34:59 PM PST 24
Finished Feb 29 01:43:19 PM PST 24
Peak memory 265564 kb
Host smart-31a88120-47da-48be-9d1f-6aced8bc6f49
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868898219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3868898219
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3420783604
Short name T814
Test name
Test status
Simulation time 1571805443 ps
CPU time 11.97 seconds
Started Feb 29 01:34:59 PM PST 24
Finished Feb 29 01:35:14 PM PST 24
Peak memory 248912 kb
Host smart-7d055ef4-c977-48a9-ae66-f37b3ff1d8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3420783604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3420783604
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1333474546
Short name T763
Test name
Test status
Simulation time 207193313 ps
CPU time 8.97 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:21 PM PST 24
Peak memory 240696 kb
Host smart-a4a4ad29-39ba-4e36-a4bc-c8d1004dbdf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333474546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1333474546
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.797900659
Short name T756
Test name
Test status
Simulation time 20133319 ps
CPU time 3.57 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:16 PM PST 24
Peak memory 239632 kb
Host smart-d6b55949-0f80-4367-b730-b89937e9dd4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=797900659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.797900659
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.367442576
Short name T736
Test name
Test status
Simulation time 6976091 ps
CPU time 1.51 seconds
Started Feb 29 01:35:14 PM PST 24
Finished Feb 29 01:35:16 PM PST 24
Peak memory 236660 kb
Host smart-4be50fba-85ca-4753-a41d-f4b46649695d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=367442576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.367442576
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2135976717
Short name T825
Test name
Test status
Simulation time 706233174 ps
CPU time 44.85 seconds
Started Feb 29 01:35:13 PM PST 24
Finished Feb 29 01:35:58 PM PST 24
Peak memory 248828 kb
Host smart-d6f26be1-000a-42ce-9b0e-ca4ac7d49e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2135976717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2135976717
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2219966864
Short name T157
Test name
Test status
Simulation time 1627861454 ps
CPU time 194.03 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:38:12 PM PST 24
Peak memory 273368 kb
Host smart-7ad49bee-f5be-4f5b-abf2-0ef7b7b66074
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2219966864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2219966864
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2885623303
Short name T168
Test name
Test status
Simulation time 24460524807 ps
CPU time 477.58 seconds
Started Feb 29 01:34:59 PM PST 24
Finished Feb 29 01:42:59 PM PST 24
Peak memory 269456 kb
Host smart-90ffeeec-9042-4764-9375-aa21b68b9127
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885623303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2885623303
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.4103286502
Short name T787
Test name
Test status
Simulation time 559964107 ps
CPU time 31.49 seconds
Started Feb 29 01:34:58 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 248224 kb
Host smart-5e7703f1-d4e1-475a-8ac6-d7dfbfab7046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4103286502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.4103286502
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3819904345
Short name T818
Test name
Test status
Simulation time 196387041 ps
CPU time 8.34 seconds
Started Feb 29 01:35:16 PM PST 24
Finished Feb 29 01:35:24 PM PST 24
Peak memory 240644 kb
Host smart-7ac0cad0-5581-4bca-8c11-a2b95c19cb7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819904345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3819904345
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1083215816
Short name T733
Test name
Test status
Simulation time 131988595 ps
CPU time 5.11 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:17 PM PST 24
Peak memory 235760 kb
Host smart-2f7e3236-a4a7-4dbf-8539-ce810f967a1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1083215816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1083215816
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2568221402
Short name T773
Test name
Test status
Simulation time 8580300 ps
CPU time 1.5 seconds
Started Feb 29 01:35:13 PM PST 24
Finished Feb 29 01:35:15 PM PST 24
Peak memory 235864 kb
Host smart-5c462728-a411-4f60-ba37-2484e6f18076
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2568221402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2568221402
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3000563003
Short name T774
Test name
Test status
Simulation time 247756127 ps
CPU time 18.29 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:30 PM PST 24
Peak memory 240604 kb
Host smart-109f12b4-1513-4b4b-b385-ce42a7118e1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3000563003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3000563003
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2053659117
Short name T740
Test name
Test status
Simulation time 129426207 ps
CPU time 9.58 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:22 PM PST 24
Peak memory 252220 kb
Host smart-a6955ed7-5025-44a2-95b5-dfc37ba2ded9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2053659117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2053659117
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1999696598
Short name T729
Test name
Test status
Simulation time 159934462 ps
CPU time 12.38 seconds
Started Feb 29 01:35:20 PM PST 24
Finished Feb 29 01:35:32 PM PST 24
Peak memory 251280 kb
Host smart-3f61fb8f-4ccf-4786-ab2e-2377b324c14e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999696598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1999696598
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2911356632
Short name T807
Test name
Test status
Simulation time 71816384 ps
CPU time 5.96 seconds
Started Feb 29 01:35:15 PM PST 24
Finished Feb 29 01:35:21 PM PST 24
Peak memory 240592 kb
Host smart-a34b9593-910c-4060-a5b5-a9b1dfbac3db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2911356632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2911356632
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.948978471
Short name T739
Test name
Test status
Simulation time 20965472 ps
CPU time 1.51 seconds
Started Feb 29 01:35:14 PM PST 24
Finished Feb 29 01:35:16 PM PST 24
Peak memory 236700 kb
Host smart-02e82612-4f4c-484d-8c4e-fa43d2f0a6f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=948978471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.948978471
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.986208076
Short name T799
Test name
Test status
Simulation time 95165569 ps
CPU time 12.95 seconds
Started Feb 29 01:35:16 PM PST 24
Finished Feb 29 01:35:29 PM PST 24
Peak memory 244840 kb
Host smart-05e1e82a-f1b8-4bd2-a8ae-7e4b91f14938
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=986208076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.986208076
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.79666467
Short name T788
Test name
Test status
Simulation time 724919701 ps
CPU time 26.57 seconds
Started Feb 29 01:35:14 PM PST 24
Finished Feb 29 01:35:41 PM PST 24
Peak memory 247852 kb
Host smart-749da75c-8f0a-41fc-a2e3-5b3b1585fe3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=79666467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.79666467
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1180339010
Short name T726
Test name
Test status
Simulation time 309144959 ps
CPU time 12.66 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:25 PM PST 24
Peak memory 254532 kb
Host smart-81762bb1-4be7-4469-b278-b3df67f3c7b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180339010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1180339010
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1789782200
Short name T719
Test name
Test status
Simulation time 343227532 ps
CPU time 8.26 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:21 PM PST 24
Peak memory 236680 kb
Host smart-15d061fe-45f2-4102-8875-387c88bdbd73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1789782200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1789782200
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1859130787
Short name T177
Test name
Test status
Simulation time 12058987 ps
CPU time 1.45 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:14 PM PST 24
Peak memory 236704 kb
Host smart-06213f17-a357-49f4-bd32-62106a4da727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1859130787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1859130787
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1768908282
Short name T810
Test name
Test status
Simulation time 945995233 ps
CPU time 13.19 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:35:25 PM PST 24
Peak memory 244848 kb
Host smart-f8a5edc7-f73a-4c9d-a93c-a17ada79bf6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1768908282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1768908282
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3394525336
Short name T139
Test name
Test status
Simulation time 3552620131 ps
CPU time 201.43 seconds
Started Feb 29 01:35:11 PM PST 24
Finished Feb 29 01:38:34 PM PST 24
Peak memory 265464 kb
Host smart-382dbea1-ac34-4f32-88e3-c443ea60314b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3394525336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3394525336
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3157178118
Short name T146
Test name
Test status
Simulation time 27547182916 ps
CPU time 475.77 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:43:08 PM PST 24
Peak memory 265532 kb
Host smart-49aea863-ce1d-448d-ace1-cd5ab2b3045b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157178118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3157178118
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.827152870
Short name T775
Test name
Test status
Simulation time 101929463 ps
CPU time 8.07 seconds
Started Feb 29 01:35:12 PM PST 24
Finished Feb 29 01:35:20 PM PST 24
Peak memory 251644 kb
Host smart-e237a081-a874-49a8-b6e9-b057b3352b1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=827152870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.827152870
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3735375777
Short name T691
Test name
Test status
Simulation time 42544857025 ps
CPU time 2461.48 seconds
Started Feb 29 02:05:26 PM PST 24
Finished Feb 29 02:46:29 PM PST 24
Peak memory 285528 kb
Host smart-d51c5f4e-edff-4aa6-8676-46b27336dbeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735375777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3735375777
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1178920864
Short name T531
Test name
Test status
Simulation time 177096598 ps
CPU time 10.73 seconds
Started Feb 29 02:05:26 PM PST 24
Finished Feb 29 02:05:38 PM PST 24
Peak memory 240024 kb
Host smart-b8431228-2d9e-4e8f-8b7c-b5c0fe451203
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1178920864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1178920864
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.223678300
Short name T669
Test name
Test status
Simulation time 5602012519 ps
CPU time 112.21 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:07:16 PM PST 24
Peak memory 255700 kb
Host smart-4dd87f78-66d2-445c-ba4d-90df1ec4817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22367
8300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.223678300
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1086693693
Short name T126
Test name
Test status
Simulation time 2614776121 ps
CPU time 50.21 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:06:15 PM PST 24
Peak memory 254760 kb
Host smart-a079125f-1430-491b-91ea-8af7f2171b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10866
93693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1086693693
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2437955275
Short name T314
Test name
Test status
Simulation time 42371015251 ps
CPU time 2623.95 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:49:09 PM PST 24
Peak memory 288260 kb
Host smart-eeaab9cb-844a-4959-9720-58b3db622675
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437955275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2437955275
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2951259370
Short name T463
Test name
Test status
Simulation time 145761806109 ps
CPU time 2335.58 seconds
Started Feb 29 02:05:26 PM PST 24
Finished Feb 29 02:44:23 PM PST 24
Peak memory 272536 kb
Host smart-00a5bf96-6f13-47f3-8082-58dc2dd733e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951259370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2951259370
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.4245952912
Short name T414
Test name
Test status
Simulation time 2837186266 ps
CPU time 27.72 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:52 PM PST 24
Peak memory 248544 kb
Host smart-33e5efdb-a5ac-4966-b522-dfa418b68e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42459
52912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.4245952912
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.816922344
Short name T122
Test name
Test status
Simulation time 6262639556 ps
CPU time 41.79 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:06:07 PM PST 24
Peak memory 246960 kb
Host smart-e59eed46-9c82-4b75-b029-9358ebf1e8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81692
2344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.816922344
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2835185815
Short name T11
Test name
Test status
Simulation time 1803864089 ps
CPU time 25.37 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:05:55 PM PST 24
Peak memory 277044 kb
Host smart-fa5cb3ae-64c6-40d0-bf81-d0d016f554cd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2835185815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2835185815
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2326960637
Short name T696
Test name
Test status
Simulation time 256039181 ps
CPU time 27.68 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:51 PM PST 24
Peak memory 253296 kb
Host smart-3368f157-90fd-4930-b87e-bfffda15eb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
60637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2326960637
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2177940317
Short name T624
Test name
Test status
Simulation time 2653895849 ps
CPU time 48.95 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:06:14 PM PST 24
Peak memory 248344 kb
Host smart-9374e215-0992-4a9c-a0a9-98a6b1784b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21779
40317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2177940317
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1479237891
Short name T503
Test name
Test status
Simulation time 71696808588 ps
CPU time 2115.14 seconds
Started Feb 29 02:05:26 PM PST 24
Finished Feb 29 02:40:42 PM PST 24
Peak memory 287592 kb
Host smart-c096fd53-36c4-45a1-8c19-624457b61f1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479237891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1479237891
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1901906610
Short name T242
Test name
Test status
Simulation time 45742963 ps
CPU time 3.97 seconds
Started Feb 29 02:05:28 PM PST 24
Finished Feb 29 02:05:32 PM PST 24
Peak memory 248556 kb
Host smart-6dddbfa9-f304-4d97-a375-6a24395f719b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1901906610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1901906610
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1696024462
Short name T70
Test name
Test status
Simulation time 146157762350 ps
CPU time 2435.93 seconds
Started Feb 29 02:05:26 PM PST 24
Finished Feb 29 02:46:04 PM PST 24
Peak memory 289276 kb
Host smart-f4a57bc7-9c4d-4e1f-979a-80853e4da971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696024462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1696024462
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1856586965
Short name T530
Test name
Test status
Simulation time 19539523 ps
CPU time 3.17 seconds
Started Feb 29 02:05:27 PM PST 24
Finished Feb 29 02:05:31 PM PST 24
Peak memory 238244 kb
Host smart-d91ab075-63cb-44e2-a6f4-73ec95d5bea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18565
86965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1856586965
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1786294192
Short name T38
Test name
Test status
Simulation time 1643247594 ps
CPU time 22.59 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:05:48 PM PST 24
Peak memory 254720 kb
Host smart-469df310-1f93-4d90-abf7-3f7f4472caec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17862
94192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1786294192
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.455748113
Short name T308
Test name
Test status
Simulation time 10515938849 ps
CPU time 854.97 seconds
Started Feb 29 02:05:30 PM PST 24
Finished Feb 29 02:19:45 PM PST 24
Peak memory 272468 kb
Host smart-02c68840-98a7-4458-b017-154bc05dd213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455748113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.455748113
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3680308477
Short name T557
Test name
Test status
Simulation time 1116262034 ps
CPU time 33.11 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:05:59 PM PST 24
Peak memory 248348 kb
Host smart-d0d5665e-f593-43e0-a8ed-690a634e3331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36803
08477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3680308477
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4137910261
Short name T539
Test name
Test status
Simulation time 793608862 ps
CPU time 19.09 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:05:45 PM PST 24
Peak memory 254588 kb
Host smart-c3c67652-95a2-463d-8c85-eeafa938d458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41379
10261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4137910261
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3714937986
Short name T31
Test name
Test status
Simulation time 419709679 ps
CPU time 12.89 seconds
Started Feb 29 02:05:37 PM PST 24
Finished Feb 29 02:05:50 PM PST 24
Peak memory 276392 kb
Host smart-277474d4-323c-4add-ba16-6e28346a1d65
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3714937986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3714937986
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1363015870
Short name T312
Test name
Test status
Simulation time 793095204 ps
CPU time 16.54 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:41 PM PST 24
Peak memory 253828 kb
Host smart-cbe1bc82-7089-4393-b3b5-d36bc2ed157a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
15870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1363015870
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.136965365
Short name T278
Test name
Test status
Simulation time 396051470 ps
CPU time 32.82 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:06:02 PM PST 24
Peak memory 254884 kb
Host smart-a6abcf73-0323-43cf-8455-bc5c80663164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13696
5365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.136965365
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3587862584
Short name T227
Test name
Test status
Simulation time 59649219518 ps
CPU time 5044.29 seconds
Started Feb 29 02:05:35 PM PST 24
Finished Feb 29 03:29:40 PM PST 24
Peak memory 338728 kb
Host smart-a102a575-fdb4-430b-b3ff-7a56f7220469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587862584 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3587862584
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3165311852
Short name T245
Test name
Test status
Simulation time 13193972 ps
CPU time 2.43 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:06:11 PM PST 24
Peak memory 248564 kb
Host smart-f1a7e2fb-bc2e-4b2d-860b-bfc2aa8d7482
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3165311852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3165311852
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3153249102
Short name T689
Test name
Test status
Simulation time 145410623219 ps
CPU time 2377.78 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:45:52 PM PST 24
Peak memory 288824 kb
Host smart-f611b49e-e1ca-4da6-af45-9e91467f5b89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153249102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3153249102
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3249028355
Short name T510
Test name
Test status
Simulation time 3593813895 ps
CPU time 40.24 seconds
Started Feb 29 02:06:10 PM PST 24
Finished Feb 29 02:06:50 PM PST 24
Peak memory 240148 kb
Host smart-3924ac93-221e-4510-b174-c867f6589a72
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3249028355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3249028355
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2410792044
Short name T574
Test name
Test status
Simulation time 1793147813 ps
CPU time 101.37 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:07:53 PM PST 24
Peak memory 255940 kb
Host smart-1c8b5c8d-9fc9-4c2f-a6b5-c67fb7bf0308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24107
92044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2410792044
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.887321752
Short name T656
Test name
Test status
Simulation time 649457742 ps
CPU time 32.83 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:27 PM PST 24
Peak memory 254632 kb
Host smart-b84a8da0-c92a-4355-a161-892287b04512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88732
1752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.887321752
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2747570572
Short name T667
Test name
Test status
Simulation time 23532308070 ps
CPU time 1029.43 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:23:21 PM PST 24
Peak memory 272580 kb
Host smart-4c0d5df5-362f-4dc8-b9b4-03e32ba31cd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747570572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2747570572
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4024101626
Short name T573
Test name
Test status
Simulation time 30125066970 ps
CPU time 1232.51 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:26:45 PM PST 24
Peak memory 284220 kb
Host smart-2752142a-4103-4b8c-b6df-cbd960f517c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024101626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4024101626
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1875038953
Short name T381
Test name
Test status
Simulation time 527514768 ps
CPU time 16.47 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:10 PM PST 24
Peak memory 248196 kb
Host smart-fa0b8b69-610b-4694-af92-b18b18459e5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18750
38953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1875038953
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1608086460
Short name T407
Test name
Test status
Simulation time 182859233 ps
CPU time 15.73 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:06:09 PM PST 24
Peak memory 246504 kb
Host smart-fa011f96-94c6-49ad-be59-24f05a3dce60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
86460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1608086460
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.343991459
Short name T419
Test name
Test status
Simulation time 2133937601 ps
CPU time 21.31 seconds
Started Feb 29 02:05:59 PM PST 24
Finished Feb 29 02:06:21 PM PST 24
Peak memory 248248 kb
Host smart-2e3b0efa-0e38-4f71-a87b-81ae497ef409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
1459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.343991459
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1657189907
Short name T677
Test name
Test status
Simulation time 7338888383 ps
CPU time 802.15 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:19:35 PM PST 24
Peak memory 272880 kb
Host smart-d4042bde-9772-46ec-9d56-824fcf8a8582
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657189907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1657189907
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3465142951
Short name T16
Test name
Test status
Simulation time 11480903994 ps
CPU time 1300.08 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:27:53 PM PST 24
Peak memory 286196 kb
Host smart-e188c93f-1abf-465f-ba34-5d4221afd4c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465142951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3465142951
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2358668315
Short name T473
Test name
Test status
Simulation time 5449341778 ps
CPU time 60.46 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:07:12 PM PST 24
Peak memory 248336 kb
Host smart-d5f6f800-796b-4ad1-a19d-c79ab5b7640a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2358668315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2358668315
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.1108708237
Short name T428
Test name
Test status
Simulation time 15720115852 ps
CPU time 233.66 seconds
Started Feb 29 02:06:14 PM PST 24
Finished Feb 29 02:10:08 PM PST 24
Peak memory 255676 kb
Host smart-a794f495-c8a3-4cd6-a3c1-a6324359b36a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11087
08237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1108708237
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2449413692
Short name T544
Test name
Test status
Simulation time 1223419098 ps
CPU time 64.98 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:07:17 PM PST 24
Peak memory 253948 kb
Host smart-a1c7d987-f0b0-4f32-a167-6db1ee8e62f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
13692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2449413692
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2373477683
Short name T408
Test name
Test status
Simulation time 106749717601 ps
CPU time 2333.49 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:45:06 PM PST 24
Peak memory 288208 kb
Host smart-efc9bf74-5449-4787-abf2-3cb33ff30031
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373477683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2373477683
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1673259577
Short name T561
Test name
Test status
Simulation time 5726780174 ps
CPU time 137.31 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:08:30 PM PST 24
Peak memory 246208 kb
Host smart-4a16522a-d8e0-4251-bf93-651ea1982a3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673259577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1673259577
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.61733732
Short name T420
Test name
Test status
Simulation time 976821584 ps
CPU time 33.75 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:47 PM PST 24
Peak memory 248268 kb
Host smart-b3156ddd-2e08-4446-982a-7ac8028fcc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61733
732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.61733732
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.4207453683
Short name T101
Test name
Test status
Simulation time 455475520 ps
CPU time 40.03 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:06:50 PM PST 24
Peak memory 254692 kb
Host smart-b04c8fa4-c212-4daa-9d76-cab8d9213e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
53683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.4207453683
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2641830910
Short name T102
Test name
Test status
Simulation time 163068905 ps
CPU time 11.3 seconds
Started Feb 29 02:06:15 PM PST 24
Finished Feb 29 02:06:27 PM PST 24
Peak memory 247696 kb
Host smart-829af59b-9d04-4cf3-ae22-64980f629f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
30910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2641830910
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1447451669
Short name T383
Test name
Test status
Simulation time 415575756 ps
CPU time 20.3 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 248260 kb
Host smart-097e2e1a-961b-46b5-8669-328710d03921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14474
51669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1447451669
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2484865217
Short name T662
Test name
Test status
Simulation time 16277833237 ps
CPU time 1741.99 seconds
Started Feb 29 02:06:10 PM PST 24
Finished Feb 29 02:35:13 PM PST 24
Peak memory 288612 kb
Host smart-62e37dd7-3f46-48e2-9f29-a6da1b6960af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484865217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2484865217
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1098946384
Short name T80
Test name
Test status
Simulation time 26495741679 ps
CPU time 1774.14 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:35:46 PM PST 24
Peak memory 272904 kb
Host smart-5e496a43-f806-4517-a1ad-860f22a3d265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098946384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1098946384
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.542387781
Short name T15
Test name
Test status
Simulation time 1027270523 ps
CPU time 14.91 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:27 PM PST 24
Peak memory 240088 kb
Host smart-6cc7c91e-5643-4712-b2e7-578c4860efed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=542387781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.542387781
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3139183047
Short name T563
Test name
Test status
Simulation time 46382304462 ps
CPU time 140.53 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:08:31 PM PST 24
Peak memory 255520 kb
Host smart-adc4e1c9-648e-47bd-aa70-3cb28e103db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31391
83047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3139183047
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.4228642508
Short name T490
Test name
Test status
Simulation time 3448953928 ps
CPU time 52.64 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:07:05 PM PST 24
Peak memory 254132 kb
Host smart-0dc70162-c6f2-4033-9272-60caa394ab33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42286
42508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.4228642508
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.4212651324
Short name T347
Test name
Test status
Simulation time 381558916428 ps
CPU time 3353.78 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 03:02:07 PM PST 24
Peak memory 288896 kb
Host smart-9ecc794e-31ab-43fd-a77c-62a9f1ef437c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212651324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4212651324
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.632370579
Short name T695
Test name
Test status
Simulation time 46733936479 ps
CPU time 2089.16 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:41:02 PM PST 24
Peak memory 288412 kb
Host smart-f0ddc471-881c-42d2-9e79-4cf535bdc003
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632370579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.632370579
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3069863131
Short name T641
Test name
Test status
Simulation time 15644558377 ps
CPU time 510.16 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:14:42 PM PST 24
Peak memory 246236 kb
Host smart-dda326b3-ba54-4bbc-a0c2-7e531a5a73ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069863131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3069863131
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3076802963
Short name T100
Test name
Test status
Simulation time 1067932597 ps
CPU time 37 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:50 PM PST 24
Peak memory 248320 kb
Host smart-e2ba55f5-a5ad-4ef8-806c-5a5eef5ef692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
02963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3076802963
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1009598671
Short name T668
Test name
Test status
Simulation time 93741472 ps
CPU time 7.74 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:06:17 PM PST 24
Peak memory 251644 kb
Host smart-1d05c15e-f128-41ff-86c3-9cbc8918e946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10095
98671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1009598671
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1642877784
Short name T88
Test name
Test status
Simulation time 1384657359 ps
CPU time 46.58 seconds
Started Feb 29 02:06:10 PM PST 24
Finished Feb 29 02:06:56 PM PST 24
Peak memory 254568 kb
Host smart-76bdc1b1-b87b-436d-a975-099506fc99f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16428
77784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1642877784
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3396912056
Short name T403
Test name
Test status
Simulation time 1681108244 ps
CPU time 45.69 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:06:55 PM PST 24
Peak memory 248428 kb
Host smart-fed8ea4f-2b8b-405b-89dd-41ce8f3210f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33969
12056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3396912056
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3157753678
Short name T315
Test name
Test status
Simulation time 153512982665 ps
CPU time 2339.1 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:45:09 PM PST 24
Peak memory 289028 kb
Host smart-5d4f4aec-aa3b-4879-aab9-a868b6c4ab2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157753678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3157753678
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2716802193
Short name T51
Test name
Test status
Simulation time 35991245031 ps
CPU time 3768.86 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 03:09:02 PM PST 24
Peak memory 338428 kb
Host smart-5ad58086-8f70-4029-b820-b4cbb9d1b1c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716802193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2716802193
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1807299839
Short name T58
Test name
Test status
Simulation time 9216216801 ps
CPU time 1117.52 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:24:50 PM PST 24
Peak memory 287656 kb
Host smart-403c3789-fa7d-4279-b065-f4c3682817e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807299839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1807299839
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1689440130
Short name T264
Test name
Test status
Simulation time 933026252 ps
CPU time 6.98 seconds
Started Feb 29 02:06:17 PM PST 24
Finished Feb 29 02:06:24 PM PST 24
Peak memory 240048 kb
Host smart-c309583c-c08f-4129-a133-a286a9b1492a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1689440130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1689440130
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2461800475
Short name T432
Test name
Test status
Simulation time 360598365 ps
CPU time 28.34 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:06:40 PM PST 24
Peak memory 247860 kb
Host smart-222e5465-4fbb-40b7-835b-a63680919f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24618
00475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2461800475
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2896474754
Short name T395
Test name
Test status
Simulation time 2669448759 ps
CPU time 34.38 seconds
Started Feb 29 02:06:10 PM PST 24
Finished Feb 29 02:06:45 PM PST 24
Peak memory 254344 kb
Host smart-41eef0dd-a8b0-4788-b29b-3e575a6e3a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28964
74754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2896474754
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1914304894
Short name T34
Test name
Test status
Simulation time 21180776253 ps
CPU time 1482.54 seconds
Started Feb 29 02:06:14 PM PST 24
Finished Feb 29 02:30:56 PM PST 24
Peak memory 272412 kb
Host smart-3f21e3f3-b308-408e-9652-7e02e857ef10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914304894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1914304894
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2522256121
Short name T518
Test name
Test status
Simulation time 37626133695 ps
CPU time 2518.14 seconds
Started Feb 29 02:06:28 PM PST 24
Finished Feb 29 02:48:27 PM PST 24
Peak memory 288788 kb
Host smart-9648f95f-5460-4772-bb0b-ef0c837b3d58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522256121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2522256121
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2295915294
Short name T344
Test name
Test status
Simulation time 5502533908 ps
CPU time 231.53 seconds
Started Feb 29 02:06:09 PM PST 24
Finished Feb 29 02:10:01 PM PST 24
Peak memory 247008 kb
Host smart-db6d3974-7d15-4c11-b5a9-cf77a1bdae4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295915294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2295915294
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2364277072
Short name T520
Test name
Test status
Simulation time 844079744 ps
CPU time 17.52 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:30 PM PST 24
Peak memory 248240 kb
Host smart-0e21d8a7-bb9d-4f05-84c0-9eb25173153a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23642
77072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2364277072
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1618618194
Short name T103
Test name
Test status
Simulation time 853975564 ps
CPU time 55.21 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:07:08 PM PST 24
Peak memory 254536 kb
Host smart-2c727e6c-b2c4-47c0-b034-e88922a62336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16186
18194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1618618194
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1654628930
Short name T639
Test name
Test status
Simulation time 294641186 ps
CPU time 24.49 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:06:36 PM PST 24
Peak memory 248256 kb
Host smart-0b99ed24-0325-4273-82be-94fcf14640ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16546
28930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1654628930
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3537420511
Short name T207
Test name
Test status
Simulation time 621055426 ps
CPU time 35.18 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:48 PM PST 24
Peak memory 254584 kb
Host smart-8baed4a9-fd2d-4ece-b213-cc85a4b7f8b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537420511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3537420511
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3241379962
Short name T233
Test name
Test status
Simulation time 23873379 ps
CPU time 2.3 seconds
Started Feb 29 02:06:15 PM PST 24
Finished Feb 29 02:06:17 PM PST 24
Peak memory 248536 kb
Host smart-388cde97-3de4-4c0b-8ca6-f530f65a9bc1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3241379962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3241379962
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3217210431
Short name T64
Test name
Test status
Simulation time 5087463808 ps
CPU time 562.07 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:15:35 PM PST 24
Peak memory 264852 kb
Host smart-fca7290a-fc4b-4941-965b-4b3c46daeb46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217210431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3217210431
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3710225095
Short name T522
Test name
Test status
Simulation time 3484922848 ps
CPU time 19.6 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:33 PM PST 24
Peak memory 240120 kb
Host smart-5e799bf0-4873-4d0e-adb7-ad1a6e4402e3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3710225095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3710225095
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3057092511
Short name T418
Test name
Test status
Simulation time 12034755850 ps
CPU time 202.6 seconds
Started Feb 29 02:06:16 PM PST 24
Finished Feb 29 02:09:39 PM PST 24
Peak memory 249328 kb
Host smart-0f42a707-67e2-43a5-ae40-98be33636022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30570
92511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3057092511
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3893332649
Short name T545
Test name
Test status
Simulation time 565095030 ps
CPU time 9.52 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:22 PM PST 24
Peak memory 248844 kb
Host smart-3dd85dda-8917-4cb4-aa59-724f7929259d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38933
32649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3893332649
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2140604135
Short name T604
Test name
Test status
Simulation time 7814757711 ps
CPU time 829.71 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:20:03 PM PST 24
Peak memory 272228 kb
Host smart-44a8c834-c6f6-4abe-ae6f-dfff0c431ebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140604135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2140604135
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.886541694
Short name T513
Test name
Test status
Simulation time 38493896093 ps
CPU time 2254.29 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:43:47 PM PST 24
Peak memory 287804 kb
Host smart-a51ef6cf-c924-4461-84a5-61240d402086
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886541694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.886541694
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2390206629
Short name T569
Test name
Test status
Simulation time 237502341 ps
CPU time 19.06 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:31 PM PST 24
Peak memory 248260 kb
Host smart-913cfbdd-95e8-40c7-a427-21747a7fda1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23902
06629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2390206629
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4227419572
Short name T609
Test name
Test status
Simulation time 4496136148 ps
CPU time 30.25 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:43 PM PST 24
Peak memory 254616 kb
Host smart-07cf37db-bf50-4e8d-9310-d7bcf915b91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42274
19572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4227419572
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.567039448
Short name T636
Test name
Test status
Simulation time 489167169 ps
CPU time 15.05 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:06:28 PM PST 24
Peak memory 246380 kb
Host smart-4402208c-7891-4fca-867c-d200719e5d3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56703
9448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.567039448
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2181837189
Short name T638
Test name
Test status
Simulation time 212178425 ps
CPU time 22.61 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:35 PM PST 24
Peak memory 248260 kb
Host smart-2ccfb8c1-9651-4b17-93a2-8479e2ae59e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21818
37189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2181837189
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3895809171
Short name T427
Test name
Test status
Simulation time 4201728120 ps
CPU time 350.43 seconds
Started Feb 29 02:06:15 PM PST 24
Finished Feb 29 02:12:06 PM PST 24
Peak memory 264652 kb
Host smart-393264d6-ed4f-41ff-b530-15b8320234bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895809171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3895809171
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4048578543
Short name T271
Test name
Test status
Simulation time 23078203504 ps
CPU time 1413.49 seconds
Started Feb 29 02:06:16 PM PST 24
Finished Feb 29 02:29:49 PM PST 24
Peak memory 271960 kb
Host smart-c4c40881-34fa-41fb-84d0-c8d1bd98d47d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048578543 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4048578543
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.794626842
Short name T232
Test name
Test status
Simulation time 182417029 ps
CPU time 3.52 seconds
Started Feb 29 02:06:14 PM PST 24
Finished Feb 29 02:06:18 PM PST 24
Peak memory 248512 kb
Host smart-1c9b10e0-11fb-4457-b976-73e79a40ea64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=794626842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.794626842
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1785031258
Short name T108
Test name
Test status
Simulation time 118881975584 ps
CPU time 1675.24 seconds
Started Feb 29 02:06:14 PM PST 24
Finished Feb 29 02:34:10 PM PST 24
Peak memory 269864 kb
Host smart-2769bd92-9148-46dd-a397-fd62f0fc1d8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785031258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1785031258
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2794449268
Short name T543
Test name
Test status
Simulation time 454859642 ps
CPU time 22.71 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:36 PM PST 24
Peak memory 239984 kb
Host smart-d788bf1b-b372-40e6-b5f6-94056616f41e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2794449268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2794449268
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1609913775
Short name T532
Test name
Test status
Simulation time 2956071700 ps
CPU time 104.09 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:07:58 PM PST 24
Peak memory 254888 kb
Host smart-97e4ac49-22f1-4128-ae45-be8f134f2f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16099
13775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1609913775
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3367790630
Short name T431
Test name
Test status
Simulation time 3927408665 ps
CPU time 21.78 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:35 PM PST 24
Peak memory 248324 kb
Host smart-15cff054-6d1a-4fdb-8bf5-fc76c1db2aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33677
90630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3367790630
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3400937400
Short name T505
Test name
Test status
Simulation time 23239896236 ps
CPU time 1301.21 seconds
Started Feb 29 02:06:15 PM PST 24
Finished Feb 29 02:27:57 PM PST 24
Peak memory 272880 kb
Host smart-1e43976c-3307-4817-9001-7b57b9687a59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400937400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3400937400
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1352275267
Short name T504
Test name
Test status
Simulation time 14938733928 ps
CPU time 1412.74 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:29:46 PM PST 24
Peak memory 288404 kb
Host smart-555ca1a4-eeb1-494b-a5f3-f1ba7093aebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352275267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1352275267
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1719108814
Short name T687
Test name
Test status
Simulation time 4134866113 ps
CPU time 178.07 seconds
Started Feb 29 02:06:12 PM PST 24
Finished Feb 29 02:09:11 PM PST 24
Peak memory 248340 kb
Host smart-4aef69ff-5ea6-43a2-90b4-b9656553f99d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719108814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1719108814
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.321855703
Short name T66
Test name
Test status
Simulation time 9106247748 ps
CPU time 68.84 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:07:22 PM PST 24
Peak memory 248408 kb
Host smart-b554a993-307c-4b1b-abac-4c004547c1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32185
5703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.321855703
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1413800608
Short name T389
Test name
Test status
Simulation time 1741698906 ps
CPU time 38.8 seconds
Started Feb 29 02:06:13 PM PST 24
Finished Feb 29 02:06:52 PM PST 24
Peak memory 254956 kb
Host smart-fcf52778-34c8-495d-82c6-1acc73eec5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14138
00608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1413800608
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2723820025
Short name T260
Test name
Test status
Simulation time 790301591 ps
CPU time 12.32 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:06:23 PM PST 24
Peak memory 252280 kb
Host smart-0f6d72ff-6aec-45da-8510-563ae01197d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27238
20025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2723820025
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.902399265
Short name T388
Test name
Test status
Simulation time 1750433381 ps
CPU time 55.18 seconds
Started Feb 29 02:06:11 PM PST 24
Finished Feb 29 02:07:06 PM PST 24
Peak memory 248272 kb
Host smart-4f08dfc0-4143-44ba-93b8-ace91ee4eaa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90239
9265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.902399265
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3302115626
Short name T272
Test name
Test status
Simulation time 31793485332 ps
CPU time 1064.72 seconds
Started Feb 29 02:06:16 PM PST 24
Finished Feb 29 02:24:01 PM PST 24
Peak memory 271380 kb
Host smart-e3a9c1da-cab1-4f9b-8f36-f8b03e66678f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302115626 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3302115626
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1162740194
Short name T238
Test name
Test status
Simulation time 51499253 ps
CPU time 3.02 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:06:35 PM PST 24
Peak memory 248556 kb
Host smart-440d9612-0d51-4c25-a93e-2e88e396655b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1162740194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1162740194
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.23427402
Short name T502
Test name
Test status
Simulation time 44212004953 ps
CPU time 943.32 seconds
Started Feb 29 02:06:24 PM PST 24
Finished Feb 29 02:22:08 PM PST 24
Peak memory 272080 kb
Host smart-17da0809-846c-4dd4-afe1-f4a9c057e742
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23427402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.23427402
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.980029811
Short name T229
Test name
Test status
Simulation time 3596637756 ps
CPU time 12.45 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:06:38 PM PST 24
Peak memory 240092 kb
Host smart-bd69cc02-8284-4333-98ec-1956d3d3397a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=980029811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.980029811
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.47919028
Short name T559
Test name
Test status
Simulation time 6603233683 ps
CPU time 182.63 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:09:28 PM PST 24
Peak memory 256456 kb
Host smart-0a8671c1-5297-4443-b531-900f775d69b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47919
028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.47919028
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3171624248
Short name T621
Test name
Test status
Simulation time 20248379 ps
CPU time 2.85 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:06:34 PM PST 24
Peak memory 238208 kb
Host smart-5828e8e4-e116-43a3-bbbe-77e0003707bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31716
24248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3171624248
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2462932339
Short name T697
Test name
Test status
Simulation time 26251174943 ps
CPU time 1612.66 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 02:33:25 PM PST 24
Peak memory 272412 kb
Host smart-7069c267-5a7b-4001-8aca-2ca000e5bd0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462932339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2462932339
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2205789476
Short name T307
Test name
Test status
Simulation time 116705560780 ps
CPU time 1738.9 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:35:24 PM PST 24
Peak memory 266780 kb
Host smart-0148f9b6-e64a-4901-83c8-bc13bf082725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205789476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2205789476
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2877199570
Short name T330
Test name
Test status
Simulation time 39246879462 ps
CPU time 241.7 seconds
Started Feb 29 02:06:22 PM PST 24
Finished Feb 29 02:10:24 PM PST 24
Peak memory 246984 kb
Host smart-07c770c7-1f07-434e-8196-23b3296785e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877199570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2877199570
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1581217716
Short name T511
Test name
Test status
Simulation time 47496746 ps
CPU time 5.45 seconds
Started Feb 29 02:06:22 PM PST 24
Finished Feb 29 02:06:28 PM PST 24
Peak memory 251208 kb
Host smart-c1edf081-7ab2-4810-b025-ce1e87ce00ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15812
17716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1581217716
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3193596975
Short name T37
Test name
Test status
Simulation time 1980719331 ps
CPU time 30.33 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 02:06:58 PM PST 24
Peak memory 253188 kb
Host smart-e7514aa3-678a-4d65-99ae-efb4c98c3249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31935
96975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3193596975
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2044634355
Short name T305
Test name
Test status
Simulation time 847362674 ps
CPU time 47.89 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:07:20 PM PST 24
Peak memory 254992 kb
Host smart-2ed76b2a-fc92-47a1-9323-78e0500f52d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20446
34355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2044634355
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4001155869
Short name T650
Test name
Test status
Simulation time 121930721 ps
CPU time 12.16 seconds
Started Feb 29 02:06:14 PM PST 24
Finished Feb 29 02:06:26 PM PST 24
Peak memory 253744 kb
Host smart-74239a12-32ad-4ee3-83d5-cb3c491926ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40011
55869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4001155869
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.348350437
Short name T291
Test name
Test status
Simulation time 74936632424 ps
CPU time 1358.95 seconds
Started Feb 29 02:06:24 PM PST 24
Finished Feb 29 02:29:03 PM PST 24
Peak memory 273068 kb
Host smart-354bbea3-9528-466c-953d-526af183354f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348350437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.348350437
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.886645845
Short name T230
Test name
Test status
Simulation time 30187459 ps
CPU time 2.85 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 02:06:30 PM PST 24
Peak memory 248540 kb
Host smart-aee06142-7936-4890-a2c6-72e18f6ad944
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=886645845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.886645845
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2331964249
Short name T36
Test name
Test status
Simulation time 12474149201 ps
CPU time 1091.99 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 02:24:45 PM PST 24
Peak memory 272740 kb
Host smart-7cb25f62-d726-4f59-8ae4-d634d002eb1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331964249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2331964249
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2237146011
Short name T202
Test name
Test status
Simulation time 221067651 ps
CPU time 13.24 seconds
Started Feb 29 02:06:24 PM PST 24
Finished Feb 29 02:06:37 PM PST 24
Peak memory 240060 kb
Host smart-e040ad12-a4d3-4cb8-a5f5-d036acfba27c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2237146011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2237146011
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.197518757
Short name T405
Test name
Test status
Simulation time 294993910 ps
CPU time 22.38 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 02:06:55 PM PST 24
Peak memory 254424 kb
Host smart-1fc7b24a-386e-4b26-8be5-0ced7c385c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
8757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.197518757
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3636039614
Short name T649
Test name
Test status
Simulation time 35549638690 ps
CPU time 983.92 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:22:50 PM PST 24
Peak memory 272328 kb
Host smart-0565fdbd-8838-4b3c-9af2-b80922f4f626
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636039614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3636039614
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1635606410
Short name T4
Test name
Test status
Simulation time 10884363502 ps
CPU time 1102.8 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:24:54 PM PST 24
Peak memory 271440 kb
Host smart-64812e53-14ab-47f5-83cd-2c49cc7e9a08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635606410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1635606410
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1960345304
Short name T318
Test name
Test status
Simulation time 10400121920 ps
CPU time 212.88 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:09:59 PM PST 24
Peak memory 247012 kb
Host smart-18629202-7d8e-4cc6-a892-4415caa1a1c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960345304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1960345304
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1855752110
Short name T440
Test name
Test status
Simulation time 515700355 ps
CPU time 34.34 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:06:58 PM PST 24
Peak memory 248348 kb
Host smart-f30876b3-0b84-4f71-9e3e-6596d6c40e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18557
52110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1855752110
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.635215437
Short name T598
Test name
Test status
Simulation time 4344021129 ps
CPU time 68.08 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:07:31 PM PST 24
Peak memory 254852 kb
Host smart-e36701a7-ef92-43f7-a540-ee1c4e6c02b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63521
5437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.635215437
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.397207746
Short name T635
Test name
Test status
Simulation time 224615987 ps
CPU time 18.1 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:06:41 PM PST 24
Peak memory 248284 kb
Host smart-1575a9d0-7d60-49d8-b416-4300ce9010a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39720
7746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.397207746
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.945260221
Short name T417
Test name
Test status
Simulation time 707889929 ps
CPU time 41.11 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 02:07:08 PM PST 24
Peak memory 256412 kb
Host smart-be196854-3b3d-4aa2-a78c-673cb136be28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94526
0221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.945260221
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4075238401
Short name T239
Test name
Test status
Simulation time 41568342 ps
CPU time 3.82 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 248556 kb
Host smart-239ddfaf-69e4-4f9e-842f-dd2f8db29d60
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4075238401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4075238401
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.689072632
Short name T568
Test name
Test status
Simulation time 138015996152 ps
CPU time 2398.2 seconds
Started Feb 29 02:06:27 PM PST 24
Finished Feb 29 02:46:26 PM PST 24
Peak memory 288448 kb
Host smart-7105656b-2992-453a-872f-d947f825e582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689072632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.689072632
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3642141184
Short name T374
Test name
Test status
Simulation time 591036464 ps
CPU time 17 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:06:40 PM PST 24
Peak memory 248416 kb
Host smart-43b6e309-db57-4b72-ac6d-74456c9c73c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3642141184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3642141184
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2143445856
Short name T406
Test name
Test status
Simulation time 6580795701 ps
CPU time 134.78 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:08:41 PM PST 24
Peak memory 256552 kb
Host smart-a7e6e5e6-80a1-478a-b324-ef6f6b744867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21434
45856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2143445856
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2463379599
Short name T86
Test name
Test status
Simulation time 4676107669 ps
CPU time 68.54 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:07:32 PM PST 24
Peak memory 254324 kb
Host smart-613151c6-6769-4193-8980-9182e2e30899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24633
79599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2463379599
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1473507236
Short name T256
Test name
Test status
Simulation time 31421290856 ps
CPU time 1455.94 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:30:42 PM PST 24
Peak memory 285964 kb
Host smart-3a1f5d6f-d84f-4870-98df-718b9bafe268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473507236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1473507236
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1305248385
Short name T488
Test name
Test status
Simulation time 15271525771 ps
CPU time 1029.56 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:23:36 PM PST 24
Peak memory 270576 kb
Host smart-5b0fd10b-5c29-4764-8f80-24ab597af0b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305248385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1305248385
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.478222738
Short name T255
Test name
Test status
Simulation time 30098956154 ps
CPU time 593.06 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 02:16:26 PM PST 24
Peak memory 247208 kb
Host smart-cbe6c176-0dea-49a3-a26a-525cfdabcf88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478222738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.478222738
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2441037481
Short name T263
Test name
Test status
Simulation time 1019655891 ps
CPU time 47.97 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:07:19 PM PST 24
Peak memory 254924 kb
Host smart-14bfddb9-57ab-4575-8d49-f0095734c7f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24410
37481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2441037481
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3916363914
Short name T121
Test name
Test status
Simulation time 1042285244 ps
CPU time 67.63 seconds
Started Feb 29 02:06:23 PM PST 24
Finished Feb 29 02:07:30 PM PST 24
Peak memory 253956 kb
Host smart-72b65d3b-d974-4713-bd63-d04f27968014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39163
63914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3916363914
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.839861732
Short name T285
Test name
Test status
Simulation time 1090888219 ps
CPU time 16.11 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:06:42 PM PST 24
Peak memory 251384 kb
Host smart-b91ae110-3e3a-4199-bb2b-589973467e2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83986
1732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.839861732
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1588760270
Short name T509
Test name
Test status
Simulation time 402701159 ps
CPU time 18.34 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:06:43 PM PST 24
Peak memory 248208 kb
Host smart-6e1b2bf3-fafd-4f8f-9752-85c1e3956f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15887
60270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1588760270
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.292340388
Short name T112
Test name
Test status
Simulation time 93372653469 ps
CPU time 2845.93 seconds
Started Feb 29 02:06:24 PM PST 24
Finished Feb 29 02:53:50 PM PST 24
Peak memory 301872 kb
Host smart-dbf3714b-f0df-4e1d-a691-ef224871f0dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292340388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.292340388
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2326500591
Short name T123
Test name
Test status
Simulation time 56739128932 ps
CPU time 3297.22 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 03:01:30 PM PST 24
Peak memory 289324 kb
Host smart-797ee6d3-6507-4083-adf0-057348131d4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326500591 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2326500591
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2443286793
Short name T248
Test name
Test status
Simulation time 13516189 ps
CPU time 2.39 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 248568 kb
Host smart-7db8cb30-5922-4526-9fcf-9c90d2ada345
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2443286793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2443286793
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2603813415
Short name T619
Test name
Test status
Simulation time 7242086865 ps
CPU time 676.06 seconds
Started Feb 29 02:06:32 PM PST 24
Finished Feb 29 02:17:49 PM PST 24
Peak memory 264672 kb
Host smart-cd435fb4-ae2b-47ec-b636-763ca00df1a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603813415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2603813415
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3085670105
Short name T607
Test name
Test status
Simulation time 181004858 ps
CPU time 10.27 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:06:37 PM PST 24
Peak memory 251988 kb
Host smart-01b19f9e-6f10-40fa-b747-7d930a98a441
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3085670105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3085670105
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2607999607
Short name T433
Test name
Test status
Simulation time 7468801752 ps
CPU time 236.84 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:10:22 PM PST 24
Peak memory 256676 kb
Host smart-5f915a03-ef03-40cc-8b19-ec41d8dfeee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26079
99607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2607999607
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3723582988
Short name T204
Test name
Test status
Simulation time 223828880 ps
CPU time 13.22 seconds
Started Feb 29 02:06:33 PM PST 24
Finished Feb 29 02:06:46 PM PST 24
Peak memory 248184 kb
Host smart-ca1c0991-c435-4cc9-afc5-08e031c9f791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
82988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3723582988
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1999258136
Short name T309
Test name
Test status
Simulation time 23021276522 ps
CPU time 1163.51 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:25:49 PM PST 24
Peak memory 272856 kb
Host smart-0dd089ee-5c4b-4995-acc0-f7f8437bbdfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999258136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1999258136
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1176444958
Short name T484
Test name
Test status
Simulation time 45640132870 ps
CPU time 1255.97 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:27:22 PM PST 24
Peak memory 264396 kb
Host smart-95394881-de7c-40f4-91ab-7d8bd1878f6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176444958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1176444958
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.755899095
Short name T542
Test name
Test status
Simulation time 206105366 ps
CPU time 7.51 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:06:34 PM PST 24
Peak memory 248268 kb
Host smart-2511a6ea-8445-42aa-a65e-6c1df1f66d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75589
9095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.755899095
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1165993250
Short name T425
Test name
Test status
Simulation time 625151692 ps
CPU time 38.83 seconds
Started Feb 29 02:06:26 PM PST 24
Finished Feb 29 02:07:06 PM PST 24
Peak memory 254568 kb
Host smart-b39309c0-b77e-4910-ad8f-9990654be41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11659
93250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1165993250
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2188579479
Short name T613
Test name
Test status
Simulation time 1016428399 ps
CPU time 26.13 seconds
Started Feb 29 02:06:31 PM PST 24
Finished Feb 29 02:06:58 PM PST 24
Peak memory 255020 kb
Host smart-99d60a93-6427-431e-b91a-c4a42009c692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21885
79479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2188579479
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2391780472
Short name T524
Test name
Test status
Simulation time 690722286 ps
CPU time 23.99 seconds
Started Feb 29 02:06:25 PM PST 24
Finished Feb 29 02:06:49 PM PST 24
Peak memory 255432 kb
Host smart-2c64a183-71a8-4a38-aa7f-56ebe250862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23917
80472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2391780472
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.356499267
Short name T231
Test name
Test status
Simulation time 14565340 ps
CPU time 2.56 seconds
Started Feb 29 02:05:34 PM PST 24
Finished Feb 29 02:05:37 PM PST 24
Peak memory 248500 kb
Host smart-2c22daeb-6fd1-47a2-8749-63e137178a37
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=356499267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.356499267
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1618355002
Short name T456
Test name
Test status
Simulation time 13216776966 ps
CPU time 1242.92 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:26:13 PM PST 24
Peak memory 288296 kb
Host smart-f4c5e6f2-e03d-4f59-a222-a5f06089bbce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618355002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1618355002
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.306919603
Short name T671
Test name
Test status
Simulation time 310057075 ps
CPU time 9.95 seconds
Started Feb 29 02:05:31 PM PST 24
Finished Feb 29 02:05:41 PM PST 24
Peak memory 240216 kb
Host smart-ec130795-b5a0-4430-a73f-e9bedf8e85d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306919603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.306919603
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.567476000
Short name T394
Test name
Test status
Simulation time 1150523466 ps
CPU time 27.61 seconds
Started Feb 29 02:05:28 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 247788 kb
Host smart-6732873e-e44c-4e5a-9491-e0c7753eab8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56747
6000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.567476000
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.952758357
Short name T710
Test name
Test status
Simulation time 3960480846 ps
CPU time 67.23 seconds
Started Feb 29 02:05:30 PM PST 24
Finished Feb 29 02:06:38 PM PST 24
Peak memory 254236 kb
Host smart-f6c076fd-9a90-478f-b8c1-765685de19bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95275
8357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.952758357
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2434821283
Short name T647
Test name
Test status
Simulation time 285575856419 ps
CPU time 2756.64 seconds
Started Feb 29 02:05:36 PM PST 24
Finished Feb 29 02:51:33 PM PST 24
Peak memory 288724 kb
Host smart-285ed16b-8bdd-484b-bec0-8cc5d6b831d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434821283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2434821283
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3790607924
Short name T686
Test name
Test status
Simulation time 17282553699 ps
CPU time 349.88 seconds
Started Feb 29 02:05:31 PM PST 24
Finished Feb 29 02:11:21 PM PST 24
Peak memory 247204 kb
Host smart-4a88ba54-2b23-4641-8689-4ddfded6b4c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790607924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3790607924
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3222759957
Short name T68
Test name
Test status
Simulation time 128184167 ps
CPU time 16.12 seconds
Started Feb 29 02:05:30 PM PST 24
Finished Feb 29 02:05:46 PM PST 24
Peak memory 248344 kb
Host smart-8d27775d-3eba-453a-bb95-f23a94ee05f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32227
59957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3222759957
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2056520657
Short name T402
Test name
Test status
Simulation time 145092781 ps
CPU time 5.43 seconds
Started Feb 29 02:05:32 PM PST 24
Finished Feb 29 02:05:38 PM PST 24
Peak memory 246524 kb
Host smart-6893d8bb-d390-4644-87b5-e9c7abf5a99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
20657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2056520657
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2724463467
Short name T10
Test name
Test status
Simulation time 3328669289 ps
CPU time 56.61 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:06:27 PM PST 24
Peak memory 264136 kb
Host smart-bf7975b0-e3e9-492d-a94b-6d84d5ab2f7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2724463467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2724463467
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.618611699
Short name T443
Test name
Test status
Simulation time 778917269 ps
CPU time 17.7 seconds
Started Feb 29 02:05:34 PM PST 24
Finished Feb 29 02:05:52 PM PST 24
Peak memory 254608 kb
Host smart-d50d9f76-3978-48a1-8fba-a24c4c660c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61861
1699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.618611699
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2009244703
Short name T478
Test name
Test status
Simulation time 234012475 ps
CPU time 20.31 seconds
Started Feb 29 02:05:36 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 248472 kb
Host smart-f22f1796-fe7c-4dc0-b327-8b56943a5412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20092
44703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2009244703
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.495483006
Short name T637
Test name
Test status
Simulation time 86226911969 ps
CPU time 1810.28 seconds
Started Feb 29 02:05:35 PM PST 24
Finished Feb 29 02:35:46 PM PST 24
Peak memory 288012 kb
Host smart-4e86e29e-61a0-435f-8c35-04a46f601b9b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495483006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.495483006
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.283417085
Short name T646
Test name
Test status
Simulation time 26435082332 ps
CPU time 1552.49 seconds
Started Feb 29 02:06:37 PM PST 24
Finished Feb 29 02:32:30 PM PST 24
Peak memory 272228 kb
Host smart-f23475c6-4950-4976-b4b6-ed2b97f10a74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283417085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.283417085
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.416172598
Short name T571
Test name
Test status
Simulation time 5132436993 ps
CPU time 130.72 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:08:47 PM PST 24
Peak memory 255812 kb
Host smart-f23aead3-7c1d-4b2e-9bc0-69128236bc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41617
2598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.416172598
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1105325513
Short name T400
Test name
Test status
Simulation time 313495130 ps
CPU time 17.86 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:06:55 PM PST 24
Peak memory 254900 kb
Host smart-0f9588d9-bab7-4f6e-9a0c-1422f8051036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11053
25513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1105325513
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1573819175
Short name T257
Test name
Test status
Simulation time 14026229318 ps
CPU time 1211.82 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:26:49 PM PST 24
Peak memory 288184 kb
Host smart-56a80714-a8a5-4070-a2e5-ced68d968df0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573819175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1573819175
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1173392122
Short name T653
Test name
Test status
Simulation time 6551163751 ps
CPU time 655.27 seconds
Started Feb 29 02:06:37 PM PST 24
Finished Feb 29 02:17:33 PM PST 24
Peak memory 264900 kb
Host smart-34e44029-4da0-4318-aad1-c9756a627feb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173392122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1173392122
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3360184404
Short name T664
Test name
Test status
Simulation time 1558610563 ps
CPU time 33.61 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:07:09 PM PST 24
Peak memory 248284 kb
Host smart-653ed66b-605a-400b-bc7f-c66a07ff5ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33601
84404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3360184404
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.2444503736
Short name T644
Test name
Test status
Simulation time 5221428789 ps
CPU time 38.69 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:07:14 PM PST 24
Peak memory 253500 kb
Host smart-c60c8216-4b32-4bb3-8111-528a4ba208fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24445
03736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.2444503736
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.2143812177
Short name T206
Test name
Test status
Simulation time 714414012 ps
CPU time 15.27 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:06:51 PM PST 24
Peak memory 248260 kb
Host smart-e0b28ea3-5c93-4281-92fd-3d94c06b03e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21438
12177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.2143812177
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.1646356951
Short name T75
Test name
Test status
Simulation time 353659212904 ps
CPU time 1439.18 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:30:35 PM PST 24
Peak memory 265012 kb
Host smart-65c22f36-5390-46c9-9c11-63e4f9f8c1fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646356951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1646356951
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3632922929
Short name T94
Test name
Test status
Simulation time 2157885727 ps
CPU time 168.92 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:09:25 PM PST 24
Peak memory 255836 kb
Host smart-51840b8a-9e1b-4718-a7c7-45a8b116fd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36329
22929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3632922929
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.276014377
Short name T632
Test name
Test status
Simulation time 3005665351 ps
CPU time 40.31 seconds
Started Feb 29 02:06:34 PM PST 24
Finished Feb 29 02:07:15 PM PST 24
Peak memory 254856 kb
Host smart-c6868407-f944-4f69-a834-1cd12ef37c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27601
4377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.276014377
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1945815792
Short name T360
Test name
Test status
Simulation time 15924368141 ps
CPU time 725.76 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:18:43 PM PST 24
Peak memory 264696 kb
Host smart-41b5b26f-ed45-4ecf-a92a-3cce5aea2405
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945815792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1945815792
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1075769868
Short name T453
Test name
Test status
Simulation time 451536563466 ps
CPU time 1914.01 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:38:30 PM PST 24
Peak memory 288484 kb
Host smart-c448c942-8843-4ace-a047-f2e603246ec3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075769868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1075769868
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3533666744
Short name T253
Test name
Test status
Simulation time 40667695596 ps
CPU time 425.37 seconds
Started Feb 29 02:06:36 PM PST 24
Finished Feb 29 02:13:43 PM PST 24
Peak memory 246992 kb
Host smart-fbb1f82c-36c5-4c48-a02d-b5bfa19e7eec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533666744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3533666744
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2015024219
Short name T633
Test name
Test status
Simulation time 330484385 ps
CPU time 9.49 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:06:45 PM PST 24
Peak memory 248248 kb
Host smart-9f660a70-1e42-4af6-a44c-36253483b6ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150
24219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2015024219
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1990489480
Short name T20
Test name
Test status
Simulation time 737857991 ps
CPU time 47.49 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:07:23 PM PST 24
Peak memory 254024 kb
Host smart-4afe6aab-7bd3-46da-be34-b3446f74e2cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
89480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1990489480
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.72066527
Short name T556
Test name
Test status
Simulation time 1320910863 ps
CPU time 67.13 seconds
Started Feb 29 02:06:35 PM PST 24
Finished Feb 29 02:07:43 PM PST 24
Peak memory 255028 kb
Host smart-67544357-19ce-4352-b0a6-15432fb473f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72066
527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.72066527
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.736388032
Short name T97
Test name
Test status
Simulation time 49989619364 ps
CPU time 1440.92 seconds
Started Feb 29 02:06:43 PM PST 24
Finished Feb 29 02:30:44 PM PST 24
Peak memory 289304 kb
Host smart-f2922072-935e-4845-960c-92ebb005d092
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736388032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.736388032
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3583423818
Short name T225
Test name
Test status
Simulation time 147249382104 ps
CPU time 1426.22 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 02:30:34 PM PST 24
Peak memory 288572 kb
Host smart-9e24bf3b-91a1-459b-8b77-50ff0aa9607d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583423818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3583423818
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3111274113
Short name T43
Test name
Test status
Simulation time 17551023229 ps
CPU time 268.54 seconds
Started Feb 29 02:06:49 PM PST 24
Finished Feb 29 02:11:18 PM PST 24
Peak memory 256104 kb
Host smart-8206dfe8-bffc-4f81-aa8b-ac51330df80a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112
74113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3111274113
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4267586577
Short name T680
Test name
Test status
Simulation time 2090091676 ps
CPU time 58.3 seconds
Started Feb 29 02:06:50 PM PST 24
Finished Feb 29 02:07:49 PM PST 24
Peak memory 254604 kb
Host smart-991c6d72-3565-42ac-a75f-6ee55ecc3810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42675
86577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4267586577
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2196000779
Short name T596
Test name
Test status
Simulation time 22615260083 ps
CPU time 1131.61 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:25:41 PM PST 24
Peak memory 272168 kb
Host smart-b62bbbf6-4798-4526-a9d8-43bdfd1f3eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196000779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2196000779
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2774198196
Short name T692
Test name
Test status
Simulation time 115376459702 ps
CPU time 1792.47 seconds
Started Feb 29 02:06:49 PM PST 24
Finished Feb 29 02:36:42 PM PST 24
Peak memory 272464 kb
Host smart-a5adab82-8e6f-4e0e-99bd-948907eb3e92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774198196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2774198196
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1887824561
Short name T334
Test name
Test status
Simulation time 27595169902 ps
CPU time 577.92 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 02:16:25 PM PST 24
Peak memory 247228 kb
Host smart-0d7c8627-6967-44df-97ff-2bdf94f1f959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887824561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1887824561
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2577646775
Short name T321
Test name
Test status
Simulation time 390531842 ps
CPU time 14.56 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:07:02 PM PST 24
Peak memory 248248 kb
Host smart-4f3821a9-0169-4d18-9afd-4dc2bfb94358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25776
46775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2577646775
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3709195490
Short name T480
Test name
Test status
Simulation time 2015878839 ps
CPU time 34.17 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:07:23 PM PST 24
Peak memory 254736 kb
Host smart-67ddcad7-9da9-41ff-ac57-8d05aa845e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37091
95490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3709195490
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3223614505
Short name T560
Test name
Test status
Simulation time 508438094 ps
CPU time 37.24 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:07:26 PM PST 24
Peak memory 248224 kb
Host smart-e5a57269-e77d-4a61-a8b8-c40ff024bfc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32236
14505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3223614505
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2127261610
Short name T489
Test name
Test status
Simulation time 763880713 ps
CPU time 8.34 seconds
Started Feb 29 02:06:49 PM PST 24
Finished Feb 29 02:06:58 PM PST 24
Peak memory 248276 kb
Host smart-b9d60db8-2140-4034-9aeb-94bef83890f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21272
61610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2127261610
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3320227954
Short name T617
Test name
Test status
Simulation time 46761960659 ps
CPU time 3563.14 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 03:06:10 PM PST 24
Peak memory 301092 kb
Host smart-374fe57e-ec86-405b-8389-5bb11aafb7b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320227954 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3320227954
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2862223800
Short name T49
Test name
Test status
Simulation time 13716610104 ps
CPU time 1303.57 seconds
Started Feb 29 02:06:51 PM PST 24
Finished Feb 29 02:28:35 PM PST 24
Peak memory 289280 kb
Host smart-b56e0b0f-83b7-4ce3-a8d8-c7420c524c34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862223800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2862223800
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1500928457
Short name T219
Test name
Test status
Simulation time 4726150853 ps
CPU time 76.53 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:08:04 PM PST 24
Peak memory 255912 kb
Host smart-021a883f-541c-4fa2-b92f-da14b8f12796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
28457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1500928457
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1850561825
Short name T567
Test name
Test status
Simulation time 1596847975 ps
CPU time 39.13 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:07:28 PM PST 24
Peak memory 254704 kb
Host smart-9ce95c88-8fc3-4cdc-930e-b0c060f551bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
61825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1850561825
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2622266169
Short name T325
Test name
Test status
Simulation time 13197948891 ps
CPU time 1087.67 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:24:56 PM PST 24
Peak memory 272880 kb
Host smart-bb5c010b-a382-4dd3-8c87-c92881b3230b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622266169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2622266169
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.354149707
Short name T651
Test name
Test status
Simulation time 59041262308 ps
CPU time 1851.78 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 02:37:39 PM PST 24
Peak memory 272800 kb
Host smart-3eef6446-ba18-4ba7-9c97-25723601ae20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354149707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.354149707
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.840333105
Short name T350
Test name
Test status
Simulation time 25584498993 ps
CPU time 525.05 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:15:34 PM PST 24
Peak memory 246120 kb
Host smart-c9fb43ab-5010-495e-93ee-f4cbed91b888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840333105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.840333105
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.371765664
Short name T249
Test name
Test status
Simulation time 4095105954 ps
CPU time 56.77 seconds
Started Feb 29 02:06:49 PM PST 24
Finished Feb 29 02:07:46 PM PST 24
Peak memory 248412 kb
Host smart-6cfbcb5d-92d7-45e2-bd73-7cbf832d88dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37176
5664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.371765664
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.169499260
Short name T535
Test name
Test status
Simulation time 1500934895 ps
CPU time 26.02 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 02:07:14 PM PST 24
Peak memory 247620 kb
Host smart-dfd44bec-fea7-4161-95cd-cc1838053c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
9260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.169499260
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1980081462
Short name T424
Test name
Test status
Simulation time 988423040 ps
CPU time 64.27 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:07:53 PM PST 24
Peak memory 254456 kb
Host smart-58ee650c-32b5-4ffe-90b5-5841805855b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19800
81462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1980081462
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2932637658
Short name T529
Test name
Test status
Simulation time 394293236 ps
CPU time 9.71 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:06:59 PM PST 24
Peak memory 253140 kb
Host smart-27c26af0-a42a-4185-89c5-ea5f1c5bc121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29326
37658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2932637658
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3200606140
Short name T296
Test name
Test status
Simulation time 190503748561 ps
CPU time 2882.03 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 02:54:50 PM PST 24
Peak memory 297128 kb
Host smart-72868cac-3d53-40a0-abd0-ffd7bf1dc2b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200606140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3200606140
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.4166131089
Short name T282
Test name
Test status
Simulation time 115357873958 ps
CPU time 6331.59 seconds
Started Feb 29 02:06:48 PM PST 24
Finished Feb 29 03:52:21 PM PST 24
Peak memory 337736 kb
Host smart-1b507ca4-03c1-44e0-a995-d7af4e27f6f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166131089 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.4166131089
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1063614152
Short name T626
Test name
Test status
Simulation time 15063493408 ps
CPU time 1453.27 seconds
Started Feb 29 02:06:59 PM PST 24
Finished Feb 29 02:31:13 PM PST 24
Peak memory 288420 kb
Host smart-6e343b8b-c51b-4791-8c49-4640177b57ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063614152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1063614152
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1025955254
Short name T588
Test name
Test status
Simulation time 4441848732 ps
CPU time 80.63 seconds
Started Feb 29 02:06:59 PM PST 24
Finished Feb 29 02:08:20 PM PST 24
Peak memory 256584 kb
Host smart-326dcfc7-732e-4d1c-9990-dd6fff1e1eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10259
55254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1025955254
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1687396224
Short name T434
Test name
Test status
Simulation time 603033687 ps
CPU time 11.25 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:11 PM PST 24
Peak memory 252300 kb
Host smart-95cae4b8-8953-4b19-96bb-cd9662e91c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
96224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1687396224
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2802913947
Short name T266
Test name
Test status
Simulation time 49510930982 ps
CPU time 1440.64 seconds
Started Feb 29 02:07:02 PM PST 24
Finished Feb 29 02:31:03 PM PST 24
Peak memory 288744 kb
Host smart-906ddb60-aa4f-4e66-8b01-5523c12cd03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802913947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2802913947
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1415351508
Short name T527
Test name
Test status
Simulation time 350278935 ps
CPU time 23.31 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:23 PM PST 24
Peak memory 248444 kb
Host smart-0a8fe971-700a-445d-b409-1f64052b0f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14153
51508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1415351508
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2723344150
Short name T47
Test name
Test status
Simulation time 3502002422 ps
CPU time 28.71 seconds
Started Feb 29 02:07:02 PM PST 24
Finished Feb 29 02:07:31 PM PST 24
Peak memory 255888 kb
Host smart-99fc5833-5b31-4564-916c-5918ff458b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
44150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2723344150
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2006274244
Short name T654
Test name
Test status
Simulation time 318349207 ps
CPU time 20.42 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:20 PM PST 24
Peak memory 248448 kb
Host smart-c10ffb16-8657-4ba9-8b33-132933e94223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20062
74244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2006274244
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1656068409
Short name T471
Test name
Test status
Simulation time 443806699 ps
CPU time 15.3 seconds
Started Feb 29 02:06:47 PM PST 24
Finished Feb 29 02:07:02 PM PST 24
Peak memory 248296 kb
Host smart-3de3aa97-ec47-43bb-a7df-57a88912da2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16560
68409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1656068409
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3750259329
Short name T622
Test name
Test status
Simulation time 35614937186 ps
CPU time 2374.56 seconds
Started Feb 29 02:07:01 PM PST 24
Finished Feb 29 02:46:35 PM PST 24
Peak memory 289264 kb
Host smart-40fb9501-b01c-4360-a5b7-d419f4c9bd52
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750259329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3750259329
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3734506953
Short name T676
Test name
Test status
Simulation time 374654923378 ps
CPU time 2925.67 seconds
Started Feb 29 02:06:58 PM PST 24
Finished Feb 29 02:55:44 PM PST 24
Peak memory 319532 kb
Host smart-62aa5edc-40e1-4c9f-a898-d9b83290d048
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734506953 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3734506953
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.225105967
Short name T385
Test name
Test status
Simulation time 1691143006 ps
CPU time 127.8 seconds
Started Feb 29 02:07:01 PM PST 24
Finished Feb 29 02:09:09 PM PST 24
Peak memory 255892 kb
Host smart-a41be96c-799b-40d9-92b8-7740d8089467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
5967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.225105967
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3257566081
Short name T670
Test name
Test status
Simulation time 947991365 ps
CPU time 34.97 seconds
Started Feb 29 02:06:59 PM PST 24
Finished Feb 29 02:07:34 PM PST 24
Peak memory 254000 kb
Host smart-5374eeaf-2621-4dbc-ac3c-958f030f9b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32575
66081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3257566081
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2211800664
Short name T363
Test name
Test status
Simulation time 53783246994 ps
CPU time 3104.73 seconds
Started Feb 29 02:06:59 PM PST 24
Finished Feb 29 02:58:45 PM PST 24
Peak memory 285788 kb
Host smart-848a07a7-b3dd-47f1-be64-7f0c57387869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211800664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2211800664
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.68260070
Short name T581
Test name
Test status
Simulation time 34980475810 ps
CPU time 2557.47 seconds
Started Feb 29 02:07:06 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 288752 kb
Host smart-bca26ae8-adee-4796-b185-9a1a65413dad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68260070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.68260070
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3525240789
Short name T336
Test name
Test status
Simulation time 11533631785 ps
CPU time 484.56 seconds
Started Feb 29 02:07:05 PM PST 24
Finished Feb 29 02:15:11 PM PST 24
Peak memory 246224 kb
Host smart-b8ac1d78-c047-48af-b387-c0e64676ba7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525240789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3525240789
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.4066699872
Short name T681
Test name
Test status
Simulation time 1261870719 ps
CPU time 25.91 seconds
Started Feb 29 02:07:01 PM PST 24
Finished Feb 29 02:07:27 PM PST 24
Peak memory 248244 kb
Host smart-7a66ff41-9619-4540-a2df-c0595c7aff6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40666
99872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.4066699872
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3856838133
Short name T516
Test name
Test status
Simulation time 222808541 ps
CPU time 16.99 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:17 PM PST 24
Peak memory 253864 kb
Host smart-defa44eb-341f-43a6-b61a-9779bc43e360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38568
38133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3856838133
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2457528042
Short name T124
Test name
Test status
Simulation time 2999002538 ps
CPU time 50.02 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:50 PM PST 24
Peak memory 254736 kb
Host smart-581030f0-cc5f-44f4-853b-36b51d0268ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24575
28042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2457528042
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2421245429
Short name T591
Test name
Test status
Simulation time 435110874 ps
CPU time 10.61 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:11 PM PST 24
Peak memory 248336 kb
Host smart-9cb09528-dd19-4089-802d-9d200201633d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24212
45429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2421245429
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.419884244
Short name T60
Test name
Test status
Simulation time 17946198476 ps
CPU time 1068.51 seconds
Started Feb 29 02:07:06 PM PST 24
Finished Feb 29 02:24:55 PM PST 24
Peak memory 272504 kb
Host smart-88c84145-57db-4536-a6cc-229fc386d3b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419884244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.419884244
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.23113140
Short name T93
Test name
Test status
Simulation time 9184119724 ps
CPU time 160.4 seconds
Started Feb 29 02:07:05 PM PST 24
Finished Feb 29 02:09:47 PM PST 24
Peak memory 255672 kb
Host smart-58594312-e0cb-43ff-ae91-2ac94633e733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.23113140
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3296093795
Short name T74
Test name
Test status
Simulation time 309026164 ps
CPU time 26.97 seconds
Started Feb 29 02:07:02 PM PST 24
Finished Feb 29 02:07:29 PM PST 24
Peak memory 254136 kb
Host smart-afe21412-2aa7-4fb0-a602-19bb341d51e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32960
93795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3296093795
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.222040036
Short name T326
Test name
Test status
Simulation time 19053005411 ps
CPU time 1195.22 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:27:09 PM PST 24
Peak memory 264720 kb
Host smart-ccbd383b-3db8-4102-a668-2a8c2d64be26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222040036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.222040036
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2437391886
Short name T398
Test name
Test status
Simulation time 28051681725 ps
CPU time 1518.65 seconds
Started Feb 29 02:07:23 PM PST 24
Finished Feb 29 02:32:42 PM PST 24
Peak memory 288436 kb
Host smart-44f00583-dfcf-4d07-a314-4c7f362e1411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437391886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2437391886
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2597608258
Short name T523
Test name
Test status
Simulation time 472393709 ps
CPU time 21.1 seconds
Started Feb 29 02:07:04 PM PST 24
Finished Feb 29 02:07:25 PM PST 24
Peak memory 255088 kb
Host smart-810da5cb-cda1-491e-b36f-f479fd7b66a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25976
08258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2597608258
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.323639075
Short name T130
Test name
Test status
Simulation time 263278805 ps
CPU time 16.4 seconds
Started Feb 29 02:06:59 PM PST 24
Finished Feb 29 02:07:16 PM PST 24
Peak memory 247812 kb
Host smart-53610034-0092-419a-af33-ed3c1ad451dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32363
9075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.323639075
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1831230334
Short name T690
Test name
Test status
Simulation time 3160498623 ps
CPU time 56.65 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:57 PM PST 24
Peak memory 254752 kb
Host smart-a6c86b82-4c61-4999-a6ee-02a04bc00ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18312
30334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1831230334
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2567907191
Short name T311
Test name
Test status
Simulation time 1985385162 ps
CPU time 20.2 seconds
Started Feb 29 02:07:00 PM PST 24
Finished Feb 29 02:07:20 PM PST 24
Peak memory 248244 kb
Host smart-3711c7ac-574f-48a5-ae5e-c4671a075bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25679
07191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2567907191
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.646898883
Short name T601
Test name
Test status
Simulation time 20827339183 ps
CPU time 1651.51 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:34:47 PM PST 24
Peak memory 289144 kb
Host smart-47288761-c35d-4dca-8f20-fc748e5f1529
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646898883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.646898883
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3081490398
Short name T288
Test name
Test status
Simulation time 42183670326 ps
CPU time 3206.85 seconds
Started Feb 29 02:07:16 PM PST 24
Finished Feb 29 03:00:43 PM PST 24
Peak memory 289000 kb
Host smart-5243dbd1-2261-40d2-b3be-d7751e75ed71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081490398 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3081490398
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.287406231
Short name T455
Test name
Test status
Simulation time 161890232720 ps
CPU time 2517.58 seconds
Started Feb 29 02:07:16 PM PST 24
Finished Feb 29 02:49:16 PM PST 24
Peak memory 288632 kb
Host smart-1f1609d7-12b2-45b5-b7e7-c7900bd12214
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287406231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.287406231
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.265302101
Short name T698
Test name
Test status
Simulation time 2733368871 ps
CPU time 168.92 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:10:04 PM PST 24
Peak memory 255668 kb
Host smart-d71939b5-e6e8-461e-9d0f-70a5739eef12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26530
2101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.265302101
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2735105185
Short name T707
Test name
Test status
Simulation time 26805793 ps
CPU time 3.43 seconds
Started Feb 29 02:07:13 PM PST 24
Finished Feb 29 02:07:16 PM PST 24
Peak memory 238348 kb
Host smart-a24e3f9f-10dc-4964-b796-c04902688b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27351
05185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2735105185
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3366220877
Short name T254
Test name
Test status
Simulation time 40194430291 ps
CPU time 1285.81 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:28:41 PM PST 24
Peak memory 271540 kb
Host smart-e0e59f94-e990-4fb8-914b-de77f692a8a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366220877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3366220877
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3479247655
Short name T536
Test name
Test status
Simulation time 33739406286 ps
CPU time 2118.75 seconds
Started Feb 29 02:07:16 PM PST 24
Finished Feb 29 02:42:37 PM PST 24
Peak memory 288608 kb
Host smart-05731f69-7621-429e-b5e1-3ed5ef874dfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479247655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3479247655
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2288547753
Short name T331
Test name
Test status
Simulation time 5299952060 ps
CPU time 214.89 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:10:50 PM PST 24
Peak memory 247212 kb
Host smart-b2f7005c-c034-4aea-84e2-d7954ba657e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288547753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2288547753
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2124365510
Short name T655
Test name
Test status
Simulation time 986053879 ps
CPU time 68.98 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:08:24 PM PST 24
Peak memory 248276 kb
Host smart-4922c755-2690-43d7-8378-04da78cdd14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21243
65510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2124365510
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3005785329
Short name T526
Test name
Test status
Simulation time 4358051781 ps
CPU time 56.23 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:08:11 PM PST 24
Peak memory 247816 kb
Host smart-89436b10-23bb-4320-88f7-6aa033ea573d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30057
85329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3005785329
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3514076222
Short name T445
Test name
Test status
Simulation time 156106848 ps
CPU time 13.13 seconds
Started Feb 29 02:07:12 PM PST 24
Finished Feb 29 02:07:26 PM PST 24
Peak memory 255832 kb
Host smart-7b461109-6b32-41ca-a430-6a45fd7ba4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35140
76222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3514076222
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.746446267
Short name T564
Test name
Test status
Simulation time 1394569132 ps
CPU time 27.11 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:07:41 PM PST 24
Peak memory 248220 kb
Host smart-1e45bc16-040a-48fd-8703-0c0b98af16f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74644
6267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.746446267
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.380427410
Short name T310
Test name
Test status
Simulation time 93822178183 ps
CPU time 895.74 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:22:11 PM PST 24
Peak memory 273040 kb
Host smart-58b4eeef-5142-43b7-9080-d07fcb53a75f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380427410 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.380427410
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1902404051
Short name T584
Test name
Test status
Simulation time 24658838405 ps
CPU time 111.81 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:09:07 PM PST 24
Peak memory 247768 kb
Host smart-c7934810-036e-4e99-8e42-cb59c5830168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19024
04051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1902404051
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2057544544
Short name T82
Test name
Test status
Simulation time 1274772172 ps
CPU time 43.65 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:07:58 PM PST 24
Peak memory 254996 kb
Host smart-62f4c874-eb12-496f-821d-6cd6db0e934f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20575
44544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2057544544
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1604208938
Short name T359
Test name
Test status
Simulation time 20236963331 ps
CPU time 1399.11 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:30:35 PM PST 24
Peak memory 287276 kb
Host smart-abb14592-251f-4db5-8582-396132d6465b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604208938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1604208938
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2434699925
Short name T555
Test name
Test status
Simulation time 107997507314 ps
CPU time 1476.74 seconds
Started Feb 29 02:07:16 PM PST 24
Finished Feb 29 02:31:53 PM PST 24
Peak memory 288516 kb
Host smart-6c337b16-a443-4024-93dd-4b7d4ceee571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434699925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2434699925
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1648067
Short name T580
Test name
Test status
Simulation time 43901039656 ps
CPU time 310.23 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:12:25 PM PST 24
Peak memory 247172 kb
Host smart-f0418ac8-45e8-489d-a410-be7c5e65c83e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1648067
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2073099512
Short name T500
Test name
Test status
Simulation time 1067082634 ps
CPU time 28.05 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:07:43 PM PST 24
Peak memory 248272 kb
Host smart-b713a394-7e37-41f6-9cb5-abb3a1d8bcb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20730
99512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2073099512
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.822250856
Short name T673
Test name
Test status
Simulation time 802954703 ps
CPU time 16.12 seconds
Started Feb 29 02:07:12 PM PST 24
Finished Feb 29 02:07:28 PM PST 24
Peak memory 247832 kb
Host smart-39ab8af2-bdef-4768-a4be-c874b8f99fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82225
0856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.822250856
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2227021667
Short name T118
Test name
Test status
Simulation time 829262173 ps
CPU time 28.86 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:07:44 PM PST 24
Peak memory 255564 kb
Host smart-7555a1b5-4fba-4c08-a84d-662f3c808ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22270
21667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2227021667
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1622056048
Short name T261
Test name
Test status
Simulation time 1106349461 ps
CPU time 24.69 seconds
Started Feb 29 02:07:15 PM PST 24
Finished Feb 29 02:07:40 PM PST 24
Peak memory 248316 kb
Host smart-f3cdfc45-52c9-405c-99cb-a2cb5e110482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16220
56048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1622056048
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3478716152
Short name T78
Test name
Test status
Simulation time 2630971560 ps
CPU time 249.68 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:11:24 PM PST 24
Peak memory 256504 kb
Host smart-34849ff5-c206-466b-bd55-bafb5dd87f64
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478716152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3478716152
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1466459768
Short name T128
Test name
Test status
Simulation time 160835757918 ps
CPU time 1025.85 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:24:38 PM PST 24
Peak memory 272604 kb
Host smart-8a7963e1-0c32-4ff5-ade6-726fccc101a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466459768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1466459768
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3014230317
Short name T660
Test name
Test status
Simulation time 4296793685 ps
CPU time 96.86 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:09:08 PM PST 24
Peak memory 255780 kb
Host smart-e6eb8e02-710b-4307-9cf5-42e65ea1b0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
30317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3014230317
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1045314737
Short name T412
Test name
Test status
Simulation time 178639400 ps
CPU time 6.78 seconds
Started Feb 29 02:07:13 PM PST 24
Finished Feb 29 02:07:20 PM PST 24
Peak memory 247848 kb
Host smart-21f27c6b-dbfb-4691-ae91-85f0d06db989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10453
14737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1045314737
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.411460894
Short name T317
Test name
Test status
Simulation time 35447573824 ps
CPU time 846.15 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:21:38 PM PST 24
Peak memory 272060 kb
Host smart-82220fbd-b6ad-4194-9d78-c8eb9beb46b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411460894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.411460894
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3504919497
Short name T661
Test name
Test status
Simulation time 12527272521 ps
CPU time 1267.25 seconds
Started Feb 29 02:07:30 PM PST 24
Finished Feb 29 02:28:40 PM PST 24
Peak memory 288884 kb
Host smart-bcc12a1c-e1d1-49b1-be88-32cfe3cec678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504919497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3504919497
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4217260307
Short name T341
Test name
Test status
Simulation time 8628771963 ps
CPU time 153.2 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:10:05 PM PST 24
Peak memory 247152 kb
Host smart-dadf090f-b84c-40c8-a90f-cef68c0f5b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217260307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4217260307
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.994293374
Short name T401
Test name
Test status
Simulation time 323007451 ps
CPU time 27.26 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:07:41 PM PST 24
Peak memory 255188 kb
Host smart-0df00999-ded2-4c2d-8483-ac35c33c096b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99429
3374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.994293374
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2923731256
Short name T127
Test name
Test status
Simulation time 66478136 ps
CPU time 3.43 seconds
Started Feb 29 02:07:14 PM PST 24
Finished Feb 29 02:07:17 PM PST 24
Peak memory 238220 kb
Host smart-60de0834-0667-49ca-baa4-e105cdf7ec62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29237
31256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2923731256
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2701357926
Short name T216
Test name
Test status
Simulation time 812654462 ps
CPU time 59.4 seconds
Started Feb 29 02:07:09 PM PST 24
Finished Feb 29 02:08:09 PM PST 24
Peak memory 248252 kb
Host smart-077b2af1-ef06-4612-bd73-e265c6722298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27013
57926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2701357926
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1991924606
Short name T113
Test name
Test status
Simulation time 43833671040 ps
CPU time 1290.88 seconds
Started Feb 29 02:07:27 PM PST 24
Finished Feb 29 02:29:02 PM PST 24
Peak memory 289148 kb
Host smart-07109f43-4b41-43ae-97e1-9359d759587d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991924606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1991924606
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3572631417
Short name T298
Test name
Test status
Simulation time 10718178857 ps
CPU time 1103.23 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:25:56 PM PST 24
Peak memory 285564 kb
Host smart-aadb004a-2562-4a1b-b7e2-f2590f911b83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572631417 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3572631417
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.3021778698
Short name T236
Test name
Test status
Simulation time 184865233 ps
CPU time 3.38 seconds
Started Feb 29 02:05:33 PM PST 24
Finished Feb 29 02:05:37 PM PST 24
Peak memory 248520 kb
Host smart-70d6c0a7-5e44-447d-a362-0bd105b587e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3021778698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.3021778698
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3621074109
Short name T120
Test name
Test status
Simulation time 170967419852 ps
CPU time 1426.67 seconds
Started Feb 29 02:05:35 PM PST 24
Finished Feb 29 02:29:22 PM PST 24
Peak memory 263704 kb
Host smart-f798409b-096c-49b3-ba22-4367af3b7d76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621074109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3621074109
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.669220081
Short name T201
Test name
Test status
Simulation time 490794261 ps
CPU time 23.96 seconds
Started Feb 29 02:05:32 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 248232 kb
Host smart-da79818b-a033-48cd-9454-15e690c2c296
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=669220081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.669220081
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2936632587
Short name T265
Test name
Test status
Simulation time 643757709 ps
CPU time 17.77 seconds
Started Feb 29 02:05:33 PM PST 24
Finished Feb 29 02:05:51 PM PST 24
Peak memory 255024 kb
Host smart-51da5345-31cc-48ae-badb-83f73535af33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29366
32587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2936632587
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.467697378
Short name T73
Test name
Test status
Simulation time 169499677 ps
CPU time 7.43 seconds
Started Feb 29 02:05:35 PM PST 24
Finished Feb 29 02:05:43 PM PST 24
Peak memory 249112 kb
Host smart-81a86e94-4b94-453d-9894-e917f38e82fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46769
7378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.467697378
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.1925284644
Short name T357
Test name
Test status
Simulation time 86793638177 ps
CPU time 2684.13 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:50:14 PM PST 24
Peak memory 288892 kb
Host smart-7bb48188-d9b0-43bb-aee1-aeae6ff7030e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925284644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1925284644
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2834178072
Short name T39
Test name
Test status
Simulation time 190464076519 ps
CPU time 2579.88 seconds
Started Feb 29 02:05:33 PM PST 24
Finished Feb 29 02:48:33 PM PST 24
Peak memory 281052 kb
Host smart-9ca68f7a-96f9-498d-ab99-710226b913cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834178072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2834178072
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3393931702
Short name T280
Test name
Test status
Simulation time 51991429444 ps
CPU time 558.25 seconds
Started Feb 29 02:05:34 PM PST 24
Finished Feb 29 02:14:53 PM PST 24
Peak memory 247152 kb
Host smart-697b0ec3-131d-4bee-833f-eecf134b06a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393931702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3393931702
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2168031028
Short name T99
Test name
Test status
Simulation time 2311248972 ps
CPU time 18.6 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:05:48 PM PST 24
Peak memory 248340 kb
Host smart-551068d2-4eec-492f-b8d6-fc07e4f9dbb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21680
31028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2168031028
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3290117697
Short name T275
Test name
Test status
Simulation time 87253536 ps
CPU time 7.1 seconds
Started Feb 29 02:05:33 PM PST 24
Finished Feb 29 02:05:40 PM PST 24
Peak memory 250960 kb
Host smart-144c13d5-e945-43a3-91ab-59c0c1796a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
17697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3290117697
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4232322175
Short name T40
Test name
Test status
Simulation time 1192842492 ps
CPU time 32.08 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:06:02 PM PST 24
Peak memory 248260 kb
Host smart-f07f6383-d288-472e-a3b6-67cf2b9d3c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42323
22175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4232322175
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3138016097
Short name T109
Test name
Test status
Simulation time 186971390723 ps
CPU time 2532.42 seconds
Started Feb 29 02:05:33 PM PST 24
Finished Feb 29 02:47:46 PM PST 24
Peak memory 289128 kb
Host smart-9598b310-ce57-44b2-a461-e1d1b20d9a94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138016097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3138016097
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2924241239
Short name T197
Test name
Test status
Simulation time 51634970434 ps
CPU time 4724.06 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 03:24:27 PM PST 24
Peak memory 314016 kb
Host smart-8e3c165e-13ef-44cf-b09b-d8e22c7ef244
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924241239 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2924241239
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4051914510
Short name T62
Test name
Test status
Simulation time 58140202435 ps
CPU time 1505.18 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:32:53 PM PST 24
Peak memory 288604 kb
Host smart-938d5549-07f3-4fc7-ab6a-422dd2b0bda8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051914510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4051914510
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1998407191
Short name T410
Test name
Test status
Simulation time 2953951503 ps
CPU time 157.69 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:10:25 PM PST 24
Peak memory 249420 kb
Host smart-df557af1-99a8-45fa-8781-69b4e0a445b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19984
07191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1998407191
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2797281146
Short name T203
Test name
Test status
Simulation time 2862502554 ps
CPU time 39.18 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:08:11 PM PST 24
Peak memory 254184 kb
Host smart-b63c3cd4-be87-4ad0-bbd2-992101c9f9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27972
81146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2797281146
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2467053478
Short name T353
Test name
Test status
Simulation time 205517045230 ps
CPU time 1349.83 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:30:17 PM PST 24
Peak memory 272404 kb
Host smart-57cfcf6b-8886-44f0-b4b0-af0bad0ecd9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467053478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2467053478
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1589592256
Short name T515
Test name
Test status
Simulation time 187613460510 ps
CPU time 2283.88 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:45:35 PM PST 24
Peak memory 287456 kb
Host smart-0001be89-296e-4cc4-b2f9-1ede3bbcce52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589592256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1589592256
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1093495163
Short name T340
Test name
Test status
Simulation time 7541016811 ps
CPU time 299.92 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:12:47 PM PST 24
Peak memory 247028 kb
Host smart-a3fefb9f-f1c1-4b05-b7b8-c0c265388c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093495163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1093495163
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1689040056
Short name T578
Test name
Test status
Simulation time 249530331 ps
CPU time 23.1 seconds
Started Feb 29 02:07:30 PM PST 24
Finished Feb 29 02:07:56 PM PST 24
Peak memory 248316 kb
Host smart-54f5d894-e806-4481-ba06-0c0c30afb2d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16890
40056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1689040056
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2302705874
Short name T472
Test name
Test status
Simulation time 61563137 ps
CPU time 5.49 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:07:37 PM PST 24
Peak memory 238184 kb
Host smart-f424ec58-a6b9-4ed5-857f-252cd74994a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23027
05874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2302705874
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.164611012
Short name T224
Test name
Test status
Simulation time 769308656 ps
CPU time 35.53 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:08:23 PM PST 24
Peak memory 253440 kb
Host smart-371456ea-e470-4a44-857a-cfc9c7ec28a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461
1012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.164611012
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2870563775
Short name T700
Test name
Test status
Simulation time 118306841 ps
CPU time 12.67 seconds
Started Feb 29 02:07:27 PM PST 24
Finished Feb 29 02:07:44 PM PST 24
Peak memory 248200 kb
Host smart-d4d2d141-4cfb-41c2-903d-de6afd4d829b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28705
63775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2870563775
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1540243919
Short name T106
Test name
Test status
Simulation time 47283225635 ps
CPU time 3110.33 seconds
Started Feb 29 02:07:31 PM PST 24
Finished Feb 29 02:59:23 PM PST 24
Peak memory 298516 kb
Host smart-5cd85f68-ccc5-4976-8e52-163b8bb8f515
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540243919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1540243919
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1575449696
Short name T199
Test name
Test status
Simulation time 17397062372 ps
CPU time 2261.77 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:45:14 PM PST 24
Peak memory 305764 kb
Host smart-5b1f5ace-7692-4577-beff-012e2dc72a33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575449696 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1575449696
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2136531906
Short name T438
Test name
Test status
Simulation time 53150588439 ps
CPU time 1369.34 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:30:21 PM PST 24
Peak memory 288728 kb
Host smart-53470266-4932-4f82-bfd5-b20f2929d348
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136531906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2136531906
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3840429201
Short name T19
Test name
Test status
Simulation time 688471605 ps
CPU time 63.54 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:08:51 PM PST 24
Peak memory 255824 kb
Host smart-67808342-9379-4936-b10a-e6afda80c9e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38404
29201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3840429201
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.988739083
Short name T422
Test name
Test status
Simulation time 3285024287 ps
CPU time 48.35 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:08:36 PM PST 24
Peak memory 254300 kb
Host smart-4db409de-57d2-431e-987d-b7e8a7e2a6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98873
9083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.988739083
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.779358430
Short name T358
Test name
Test status
Simulation time 59365832786 ps
CPU time 1651.21 seconds
Started Feb 29 02:07:27 PM PST 24
Finished Feb 29 02:35:02 PM PST 24
Peak memory 272160 kb
Host smart-01a4cfcb-f5ae-48ab-b31e-4fe9567d358d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779358430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.779358430
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2530990696
Short name T657
Test name
Test status
Simulation time 66748950042 ps
CPU time 2140.57 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:43:13 PM PST 24
Peak memory 271984 kb
Host smart-27c655d3-d294-4b90-b7f1-c897899b365c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530990696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2530990696
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3259482806
Short name T72
Test name
Test status
Simulation time 104570444532 ps
CPU time 467.55 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:15:19 PM PST 24
Peak memory 247096 kb
Host smart-9372823a-3aaf-47cb-8ceb-63a9fe6ea129
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259482806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3259482806
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2794417197
Short name T672
Test name
Test status
Simulation time 3320595099 ps
CPU time 54.25 seconds
Started Feb 29 02:07:47 PM PST 24
Finished Feb 29 02:08:42 PM PST 24
Peak memory 248400 kb
Host smart-822dec12-a466-42a2-a48d-66021c9cd314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
17197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2794417197
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1837495184
Short name T566
Test name
Test status
Simulation time 1035119401 ps
CPU time 33.93 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:08:05 PM PST 24
Peak memory 246996 kb
Host smart-42bc6559-50de-4f67-93b8-2cf9103369dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18374
95184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1837495184
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.4264662885
Short name T50
Test name
Test status
Simulation time 3407250905 ps
CPU time 57.09 seconds
Started Feb 29 02:07:27 PM PST 24
Finished Feb 29 02:08:28 PM PST 24
Peak memory 246648 kb
Host smart-408397b1-e3b7-41dd-9abc-af7be95531f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
62885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4264662885
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2591086941
Short name T441
Test name
Test status
Simulation time 438181934 ps
CPU time 18.75 seconds
Started Feb 29 02:07:28 PM PST 24
Finished Feb 29 02:07:50 PM PST 24
Peak memory 248268 kb
Host smart-6a6c9ae1-229c-4f3a-bce9-fd77774e7ac0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25910
86941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2591086941
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3389210362
Short name T470
Test name
Test status
Simulation time 489538020702 ps
CPU time 2346.41 seconds
Started Feb 29 02:07:29 PM PST 24
Finished Feb 29 02:46:39 PM PST 24
Peak memory 284808 kb
Host smart-ebc1128d-82ee-4b2d-909e-4499daa2332c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389210362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3389210362
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.678078500
Short name T590
Test name
Test status
Simulation time 12386140790 ps
CPU time 1495.27 seconds
Started Feb 29 02:07:44 PM PST 24
Finished Feb 29 02:32:40 PM PST 24
Peak memory 305572 kb
Host smart-5e5dc935-b963-4f07-9829-cdce20b9e9df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678078500 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.678078500
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1644799502
Short name T327
Test name
Test status
Simulation time 42083865675 ps
CPU time 1066.02 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:25:28 PM PST 24
Peak memory 273052 kb
Host smart-05323da9-642c-4152-90c3-093d5fb24af1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644799502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1644799502
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2032106425
Short name T514
Test name
Test status
Simulation time 6731769673 ps
CPU time 173.58 seconds
Started Feb 29 02:07:43 PM PST 24
Finished Feb 29 02:10:36 PM PST 24
Peak memory 255764 kb
Host smart-dcf542e6-65f1-46c6-ba3b-aafa8ae4079d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
06425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2032106425
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2392097793
Short name T404
Test name
Test status
Simulation time 150763494 ps
CPU time 14.02 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:07:56 PM PST 24
Peak memory 252296 kb
Host smart-d3e8ab79-78df-4c8d-9add-b71c584320ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23920
97793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2392097793
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4185701969
Short name T352
Test name
Test status
Simulation time 14153994860 ps
CPU time 1368.4 seconds
Started Feb 29 02:07:39 PM PST 24
Finished Feb 29 02:30:28 PM PST 24
Peak memory 288716 kb
Host smart-eae35cc6-ca72-4353-9721-83a4239fc261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185701969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4185701969
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1844139275
Short name T615
Test name
Test status
Simulation time 50636216709 ps
CPU time 1389.85 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:30:52 PM PST 24
Peak memory 271924 kb
Host smart-a9d6b145-96e7-4ad7-8b23-a27300d06d4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844139275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1844139275
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2780139526
Short name T348
Test name
Test status
Simulation time 14014896834 ps
CPU time 559.9 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:17:02 PM PST 24
Peak memory 246216 kb
Host smart-99627d77-93b0-480c-ba32-882b634c1e1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780139526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2780139526
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1591125191
Short name T538
Test name
Test status
Simulation time 1311044763 ps
CPU time 24.84 seconds
Started Feb 29 02:07:39 PM PST 24
Finished Feb 29 02:08:04 PM PST 24
Peak memory 248268 kb
Host smart-1c518879-a6b8-4319-95ea-c40e874f0a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
25191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1591125191
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1888686504
Short name T52
Test name
Test status
Simulation time 1343616569 ps
CPU time 46.03 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:08:28 PM PST 24
Peak memory 254672 kb
Host smart-41afced3-4c56-4c31-8484-266b9bb7e3b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18886
86504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1888686504
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3775621901
Short name T87
Test name
Test status
Simulation time 823894805 ps
CPU time 13.94 seconds
Started Feb 29 02:07:43 PM PST 24
Finished Feb 29 02:07:57 PM PST 24
Peak memory 246528 kb
Host smart-a2ac912e-976b-4c82-b56b-f22e67bc6175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37756
21901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3775621901
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1873171758
Short name T468
Test name
Test status
Simulation time 20732219695 ps
CPU time 57.53 seconds
Started Feb 29 02:07:45 PM PST 24
Finished Feb 29 02:08:43 PM PST 24
Peak memory 248292 kb
Host smart-89af1902-513e-4893-95fa-2b3b7202f18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18731
71758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1873171758
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2010071474
Short name T477
Test name
Test status
Simulation time 17611479612 ps
CPU time 1432.58 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:31:34 PM PST 24
Peak memory 281124 kb
Host smart-697b1260-9277-4a43-a592-58dc393fc4b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010071474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2010071474
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.325985414
Short name T628
Test name
Test status
Simulation time 4009502290 ps
CPU time 227.65 seconds
Started Feb 29 02:07:39 PM PST 24
Finished Feb 29 02:11:27 PM PST 24
Peak memory 255824 kb
Host smart-f282fa4d-4d01-4894-86a9-cd6b3534a2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32598
5414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.325985414
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.51046718
Short name T413
Test name
Test status
Simulation time 75225528 ps
CPU time 9.31 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:07:51 PM PST 24
Peak memory 251052 kb
Host smart-be2cb33f-7f73-4c6c-9a1b-05d3b75be493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51046
718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.51046718
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2263993560
Short name T623
Test name
Test status
Simulation time 14199138646 ps
CPU time 712.47 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:19:34 PM PST 24
Peak memory 264732 kb
Host smart-fa4aea84-4d1e-4dcd-b5d5-7962452cbddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263993560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2263993560
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3516127180
Short name T583
Test name
Test status
Simulation time 132971409439 ps
CPU time 2906.75 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:56:09 PM PST 24
Peak memory 284980 kb
Host smart-eea20236-a0e0-4322-9ed6-be2b676cc125
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516127180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3516127180
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.823846358
Short name T335
Test name
Test status
Simulation time 31963785014 ps
CPU time 318.69 seconds
Started Feb 29 02:07:39 PM PST 24
Finished Feb 29 02:12:58 PM PST 24
Peak memory 247216 kb
Host smart-7064afe1-e31a-49e9-beb7-9d5bfd4b72ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823846358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.823846358
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1997953670
Short name T534
Test name
Test status
Simulation time 1694521834 ps
CPU time 29.19 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:08:12 PM PST 24
Peak memory 248296 kb
Host smart-f59fe1cc-9225-4c52-acad-9f70a63264d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19979
53670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1997953670
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.4250219183
Short name T449
Test name
Test status
Simulation time 741489399 ps
CPU time 50.41 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:08:32 PM PST 24
Peak memory 254552 kb
Host smart-a52e37e2-7f92-485d-b4dd-a37a516b0ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
19183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4250219183
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1169861641
Short name T131
Test name
Test status
Simulation time 738954510 ps
CPU time 16.08 seconds
Started Feb 29 02:07:40 PM PST 24
Finished Feb 29 02:07:57 PM PST 24
Peak memory 254716 kb
Host smart-dfec7e09-d8d8-404f-933f-3d3415ff9dc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11698
61641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1169861641
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1781251076
Short name T678
Test name
Test status
Simulation time 709279116 ps
CPU time 29.84 seconds
Started Feb 29 02:07:39 PM PST 24
Finished Feb 29 02:08:09 PM PST 24
Peak memory 248244 kb
Host smart-c52cdaf6-2eca-4ccd-9d58-22007aa6f419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17812
51076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1781251076
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4031440136
Short name T587
Test name
Test status
Simulation time 1120734307 ps
CPU time 23.77 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:08:06 PM PST 24
Peak memory 248276 kb
Host smart-a5e13fd3-1044-423d-88c1-3b020752c127
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031440136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4031440136
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3295829798
Short name T56
Test name
Test status
Simulation time 155944889876 ps
CPU time 4587.24 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 03:24:09 PM PST 24
Peak memory 337876 kb
Host smart-a13ac266-80c9-430f-90ef-54875f9c33c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295829798 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3295829798
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2442070077
Short name T464
Test name
Test status
Simulation time 64173877764 ps
CPU time 650.24 seconds
Started Feb 29 02:07:59 PM PST 24
Finished Feb 29 02:18:49 PM PST 24
Peak memory 265768 kb
Host smart-89f6b010-fcb2-4741-af8e-8fcee75f69e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442070077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2442070077
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3848218448
Short name T606
Test name
Test status
Simulation time 86598931155 ps
CPU time 275.84 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:12:19 PM PST 24
Peak memory 255800 kb
Host smart-3ecc7cd8-2f6e-41dc-af63-8a6e648bd263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38482
18448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3848218448
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3971801635
Short name T125
Test name
Test status
Simulation time 405946392 ps
CPU time 43.15 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:08:26 PM PST 24
Peak memory 255008 kb
Host smart-88f04a4f-3253-45d8-8cfd-9ae418d1359f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
01635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3971801635
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3596241623
Short name T2
Test name
Test status
Simulation time 114680248475 ps
CPU time 2152.19 seconds
Started Feb 29 02:07:58 PM PST 24
Finished Feb 29 02:43:50 PM PST 24
Peak memory 283312 kb
Host smart-f5f205dc-2381-4432-a807-2e0d55840443
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596241623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3596241623
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1842107138
Short name T699
Test name
Test status
Simulation time 29946178726 ps
CPU time 353.66 seconds
Started Feb 29 02:07:57 PM PST 24
Finished Feb 29 02:13:51 PM PST 24
Peak memory 246992 kb
Host smart-ca16e8ba-112a-475c-b772-e410f794b7b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842107138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1842107138
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2165614594
Short name T450
Test name
Test status
Simulation time 32333569 ps
CPU time 3.46 seconds
Started Feb 29 02:07:41 PM PST 24
Finished Feb 29 02:07:45 PM PST 24
Peak memory 240072 kb
Host smart-c148f4e6-e374-4ee5-b5ba-16b9876c2db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21656
14594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2165614594
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.278796194
Short name T258
Test name
Test status
Simulation time 10359946149 ps
CPU time 29.65 seconds
Started Feb 29 02:07:45 PM PST 24
Finished Feb 29 02:08:16 PM PST 24
Peak memory 254480 kb
Host smart-e1e3792a-f52f-43b5-933a-7345dc160a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27879
6194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.278796194
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2778346481
Short name T289
Test name
Test status
Simulation time 8384332916 ps
CPU time 67.77 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:08:50 PM PST 24
Peak memory 254744 kb
Host smart-923cc3f1-8095-4954-be26-c54b4d0bdb00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
46481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2778346481
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1493965128
Short name T701
Test name
Test status
Simulation time 1505544064 ps
CPU time 29.59 seconds
Started Feb 29 02:07:42 PM PST 24
Finished Feb 29 02:08:12 PM PST 24
Peak memory 248196 kb
Host smart-730411ad-b1fa-464c-9e6a-7e4adc7dace7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14939
65128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1493965128
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1707623394
Short name T684
Test name
Test status
Simulation time 2361618723 ps
CPU time 137.32 seconds
Started Feb 29 02:07:58 PM PST 24
Finished Feb 29 02:10:16 PM PST 24
Peak memory 256516 kb
Host smart-43959cf2-98a4-4cc3-8483-9901b8a8b6bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707623394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1707623394
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2299958058
Short name T107
Test name
Test status
Simulation time 110563639878 ps
CPU time 1744.3 seconds
Started Feb 29 02:08:05 PM PST 24
Finished Feb 29 02:37:10 PM PST 24
Peak memory 283004 kb
Host smart-fb0cbb46-d341-4fa5-b840-72a237c84c69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299958058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2299958058
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2968968306
Short name T475
Test name
Test status
Simulation time 10830025107 ps
CPU time 186.75 seconds
Started Feb 29 02:07:58 PM PST 24
Finished Feb 29 02:11:05 PM PST 24
Peak memory 256540 kb
Host smart-aa41331b-7d67-4318-aa3d-c53bdeeb704a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29689
68306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2968968306
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2222110698
Short name T129
Test name
Test status
Simulation time 67005786 ps
CPU time 7.99 seconds
Started Feb 29 02:08:00 PM PST 24
Finished Feb 29 02:08:09 PM PST 24
Peak memory 251824 kb
Host smart-dc31becc-41a7-40d5-8f03-4adc6e7af3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
10698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2222110698
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2532208243
Short name T361
Test name
Test status
Simulation time 13264164265 ps
CPU time 1032.14 seconds
Started Feb 29 02:07:59 PM PST 24
Finished Feb 29 02:25:11 PM PST 24
Peak memory 268988 kb
Host smart-c0e9a1d1-1f28-486c-894a-e7d9566644c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532208243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2532208243
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3536078183
Short name T105
Test name
Test status
Simulation time 33837579944 ps
CPU time 2047.14 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:42:29 PM PST 24
Peak memory 271944 kb
Host smart-d3496913-6654-4931-b595-aeda3e8e4bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536078183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3536078183
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3136656593
Short name T345
Test name
Test status
Simulation time 44459749016 ps
CPU time 397.91 seconds
Started Feb 29 02:07:58 PM PST 24
Finished Feb 29 02:14:36 PM PST 24
Peak memory 247232 kb
Host smart-d59e9a08-b43d-482c-a6b2-e53ab394cbaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136656593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3136656593
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2707022866
Short name T558
Test name
Test status
Simulation time 639733617 ps
CPU time 31.99 seconds
Started Feb 29 02:07:59 PM PST 24
Finished Feb 29 02:08:31 PM PST 24
Peak memory 248248 kb
Host smart-420348e1-4485-483a-baf4-099d72c57d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27070
22866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2707022866
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1867180817
Short name T674
Test name
Test status
Simulation time 1331867324 ps
CPU time 40.69 seconds
Started Feb 29 02:07:57 PM PST 24
Finished Feb 29 02:08:38 PM PST 24
Peak memory 247148 kb
Host smart-e08c9ba9-901b-4400-b2c9-cb2565068821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18671
80817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1867180817
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2027977093
Short name T1
Test name
Test status
Simulation time 1093146231 ps
CPU time 36.9 seconds
Started Feb 29 02:07:59 PM PST 24
Finished Feb 29 02:08:36 PM PST 24
Peak memory 247224 kb
Host smart-c70adb96-2822-49dc-a297-5bc5637d1615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20279
77093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2027977093
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.471805558
Short name T63
Test name
Test status
Simulation time 616694393 ps
CPU time 36.11 seconds
Started Feb 29 02:07:57 PM PST 24
Finished Feb 29 02:08:34 PM PST 24
Peak memory 248204 kb
Host smart-ca0879e6-8ad0-48f0-a49a-c82c16b9ef24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47180
5558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.471805558
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1731654012
Short name T104
Test name
Test status
Simulation time 108372729368 ps
CPU time 3204.97 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 03:01:46 PM PST 24
Peak memory 288252 kb
Host smart-f8bc96f4-8e93-4c1d-9dfc-e7544935fff2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731654012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1731654012
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1612008310
Short name T572
Test name
Test status
Simulation time 102937820933 ps
CPU time 5215.45 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 03:35:16 PM PST 24
Peak memory 321736 kb
Host smart-15150323-10c1-48f2-9675-618a8772e5cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612008310 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1612008310
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3480540935
Short name T479
Test name
Test status
Simulation time 32993821370 ps
CPU time 1946.6 seconds
Started Feb 29 02:08:23 PM PST 24
Finished Feb 29 02:40:50 PM PST 24
Peak memory 283360 kb
Host smart-5df96d44-9871-4a2b-81ec-ff34720c630b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480540935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3480540935
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3604361482
Short name T688
Test name
Test status
Simulation time 2742962182 ps
CPU time 177.4 seconds
Started Feb 29 02:08:25 PM PST 24
Finished Feb 29 02:11:23 PM PST 24
Peak memory 249504 kb
Host smart-e1f4d024-1642-4447-8d19-6234710c6fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36043
61482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3604361482
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2584905396
Short name T200
Test name
Test status
Simulation time 641035230 ps
CPU time 23.92 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:08:45 PM PST 24
Peak memory 254656 kb
Host smart-a68415a7-84d9-4430-9f3a-9cf792c73610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25849
05396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2584905396
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.648861661
Short name T355
Test name
Test status
Simulation time 14677787269 ps
CPU time 1370.25 seconds
Started Feb 29 02:08:23 PM PST 24
Finished Feb 29 02:31:14 PM PST 24
Peak memory 288800 kb
Host smart-5b0f211f-b774-4bed-8139-be056f2c54ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648861661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.648861661
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2011064743
Short name T608
Test name
Test status
Simulation time 34984509482 ps
CPU time 2020.55 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:42:02 PM PST 24
Peak memory 272404 kb
Host smart-dfa4c4a4-0a62-46c5-94e9-4e1b9e6807a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011064743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2011064743
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2250860673
Short name T342
Test name
Test status
Simulation time 5427704010 ps
CPU time 216.93 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:11:58 PM PST 24
Peak memory 247252 kb
Host smart-48b2bc00-9130-42ee-b40c-cce17d3598bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250860673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2250860673
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1547582830
Short name T319
Test name
Test status
Simulation time 708896761 ps
CPU time 52.05 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:09:12 PM PST 24
Peak memory 255472 kb
Host smart-0b9f6a66-56e5-4ab4-9dac-711f25583372
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
82830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1547582830
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3631956722
Short name T625
Test name
Test status
Simulation time 1251367758 ps
CPU time 24.77 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:08:46 PM PST 24
Peak memory 254712 kb
Host smart-0a1d60d3-2caf-42bb-b6a9-9cbff1d27ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36319
56722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3631956722
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2205451929
Short name T42
Test name
Test status
Simulation time 1966292424 ps
CPU time 56.47 seconds
Started Feb 29 02:08:23 PM PST 24
Finished Feb 29 02:09:20 PM PST 24
Peak memory 254420 kb
Host smart-1c08bbf3-1544-4aa3-88e4-c69fb7d50d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22054
51929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2205451929
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3188180461
Short name T268
Test name
Test status
Simulation time 510017042 ps
CPU time 11.85 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:08:32 PM PST 24
Peak memory 248272 kb
Host smart-1d87b810-1b5c-4017-a832-357e26e8d3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31881
80461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3188180461
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.404734169
Short name T666
Test name
Test status
Simulation time 38810769240 ps
CPU time 1983.33 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:41:25 PM PST 24
Peak memory 272184 kb
Host smart-bb5a7a8c-26f6-4bfb-bf4d-5aabfaff20c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404734169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.404734169
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1244228042
Short name T575
Test name
Test status
Simulation time 67197091172 ps
CPU time 1216.93 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:28:37 PM PST 24
Peak memory 264820 kb
Host smart-76a709ca-a4f5-4ee0-ae1e-1e99aba1761b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244228042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1244228042
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3454570991
Short name T391
Test name
Test status
Simulation time 2322105625 ps
CPU time 37.4 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:08:59 PM PST 24
Peak memory 255444 kb
Host smart-c3a90139-73c9-4d4c-8d22-2cc02cca564f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34545
70991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3454570991
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2930535974
Short name T85
Test name
Test status
Simulation time 878183636 ps
CPU time 45.66 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:09:06 PM PST 24
Peak memory 254332 kb
Host smart-6810a7c6-3a06-40dd-98d6-27009f0d78a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29305
35974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2930535974
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2055586434
Short name T323
Test name
Test status
Simulation time 13263999518 ps
CPU time 774.35 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:21:16 PM PST 24
Peak memory 271324 kb
Host smart-feecc5a7-ee20-4ac8-8508-5e4ca018393d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055586434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2055586434
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2086775648
Short name T133
Test name
Test status
Simulation time 51497535765 ps
CPU time 1509.56 seconds
Started Feb 29 02:08:22 PM PST 24
Finished Feb 29 02:33:32 PM PST 24
Peak memory 264712 kb
Host smart-9ce64239-07c0-4ed1-9c3b-5e121c350fa9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086775648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2086775648
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3948576277
Short name T577
Test name
Test status
Simulation time 18353788604 ps
CPU time 296.36 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:13:18 PM PST 24
Peak memory 246256 kb
Host smart-02bbb798-8e95-4807-b1ba-2e5e9b6b0bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948576277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3948576277
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3041490368
Short name T380
Test name
Test status
Simulation time 807700546 ps
CPU time 34.76 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:08:55 PM PST 24
Peak memory 248264 kb
Host smart-1a370384-2c19-4beb-9a07-45dd8b00c4b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30414
90368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3041490368
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1965615380
Short name T491
Test name
Test status
Simulation time 269064238 ps
CPU time 16.34 seconds
Started Feb 29 02:08:21 PM PST 24
Finished Feb 29 02:08:38 PM PST 24
Peak memory 247740 kb
Host smart-3e0a23b1-853d-4def-9b3c-30002bb5b0d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
15380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1965615380
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.4240104260
Short name T287
Test name
Test status
Simulation time 102254466 ps
CPU time 18.8 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:08:39 PM PST 24
Peak memory 254544 kb
Host smart-10becd52-cb49-48af-bce3-9eb478512954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42401
04260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.4240104260
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2810608966
Short name T610
Test name
Test status
Simulation time 868075550 ps
CPU time 52.19 seconds
Started Feb 29 02:08:25 PM PST 24
Finished Feb 29 02:09:17 PM PST 24
Peak memory 248220 kb
Host smart-b86e77be-e8ca-463d-a811-df8cf4de0b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28106
08966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2810608966
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.1596312905
Short name T303
Test name
Test status
Simulation time 10995699878 ps
CPU time 168.32 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:11:09 PM PST 24
Peak memory 256524 kb
Host smart-6df69a3d-3c62-46a8-90e5-bcf61460c45c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596312905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.1596312905
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2806663740
Short name T390
Test name
Test status
Simulation time 10531358801 ps
CPU time 1377.53 seconds
Started Feb 29 02:08:39 PM PST 24
Finished Feb 29 02:31:37 PM PST 24
Peak memory 289112 kb
Host smart-4fb081c3-8a6e-446e-a5e5-d2a74dce93b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806663740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2806663740
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2490779706
Short name T533
Test name
Test status
Simulation time 1628012797 ps
CPU time 107.99 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:10:26 PM PST 24
Peak memory 249300 kb
Host smart-a65deee8-23ba-4f9f-a1ea-cbc685b9883a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24907
79706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2490779706
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.755836350
Short name T279
Test name
Test status
Simulation time 2428035063 ps
CPU time 50.6 seconds
Started Feb 29 02:08:41 PM PST 24
Finished Feb 29 02:09:31 PM PST 24
Peak memory 255480 kb
Host smart-b2327792-95b9-4cbe-a5be-2d3a1c02bb8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75583
6350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.755836350
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2716056694
Short name T423
Test name
Test status
Simulation time 116214182540 ps
CPU time 1661.33 seconds
Started Feb 29 02:08:37 PM PST 24
Finished Feb 29 02:36:19 PM PST 24
Peak memory 271764 kb
Host smart-e025cb02-112f-4b59-8478-51f12e3743d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716056694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2716056694
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3307078024
Short name T338
Test name
Test status
Simulation time 4922018476 ps
CPU time 142.87 seconds
Started Feb 29 02:08:42 PM PST 24
Finished Feb 29 02:11:05 PM PST 24
Peak memory 246980 kb
Host smart-afa34831-5e2f-4ed9-bc4c-218df235ead6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307078024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3307078024
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1519193653
Short name T457
Test name
Test status
Simulation time 934613470 ps
CPU time 21.85 seconds
Started Feb 29 02:08:23 PM PST 24
Finished Feb 29 02:08:45 PM PST 24
Peak memory 248224 kb
Host smart-e9106600-f28b-410f-a89e-69422cb27547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191
93653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1519193653
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3861250905
Short name T276
Test name
Test status
Simulation time 706121544 ps
CPU time 18.72 seconds
Started Feb 29 02:08:25 PM PST 24
Finished Feb 29 02:08:45 PM PST 24
Peak memory 254104 kb
Host smart-7ac617b8-5d5d-4db8-af08-4e7cf997787e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38612
50905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3861250905
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3165663419
Short name T658
Test name
Test status
Simulation time 54084603 ps
CPU time 3.46 seconds
Started Feb 29 02:08:37 PM PST 24
Finished Feb 29 02:08:41 PM PST 24
Peak memory 238384 kb
Host smart-b158739e-0443-4bd5-84d5-96a665b68ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31656
63419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3165663419
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3941468884
Short name T565
Test name
Test status
Simulation time 3132895048 ps
CPU time 51.4 seconds
Started Feb 29 02:08:20 PM PST 24
Finished Feb 29 02:09:11 PM PST 24
Peak memory 248268 kb
Host smart-3d3aba65-96f8-4f3a-a5f0-869ec69642e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39414
68884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3941468884
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1547866412
Short name T259
Test name
Test status
Simulation time 139513443380 ps
CPU time 2386.52 seconds
Started Feb 29 02:08:40 PM PST 24
Finished Feb 29 02:48:27 PM PST 24
Peak memory 288432 kb
Host smart-b501bee7-8730-4cc8-85bd-63052e8651d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547866412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1547866412
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1845722993
Short name T96
Test name
Test status
Simulation time 42240723800 ps
CPU time 3905.67 seconds
Started Feb 29 02:08:39 PM PST 24
Finished Feb 29 03:13:45 PM PST 24
Peak memory 322184 kb
Host smart-089284e3-95f0-4c61-bb8e-75d4ace37406
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845722993 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1845722993
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.358988107
Short name T111
Test name
Test status
Simulation time 151534025971 ps
CPU time 2594.86 seconds
Started Feb 29 02:08:43 PM PST 24
Finished Feb 29 02:51:58 PM PST 24
Peak memory 289080 kb
Host smart-37885292-8195-4938-92ba-4f362f5c83fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358988107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.358988107
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2041455039
Short name T429
Test name
Test status
Simulation time 9600962312 ps
CPU time 138.03 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:10:56 PM PST 24
Peak memory 256480 kb
Host smart-e325ab4d-8356-4a72-97d6-6288716a9943
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20414
55039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2041455039
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1766106590
Short name T548
Test name
Test status
Simulation time 5182368856 ps
CPU time 73.6 seconds
Started Feb 29 02:08:41 PM PST 24
Finished Feb 29 02:09:55 PM PST 24
Peak memory 254684 kb
Host smart-45bb75dd-cd85-4e7e-9fb3-ef0abf98509a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17661
06590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1766106590
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3028059524
Short name T356
Test name
Test status
Simulation time 80362091031 ps
CPU time 1397.63 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:31:56 PM PST 24
Peak memory 264732 kb
Host smart-8002e32c-fd9e-4aeb-b8ca-e64cbcd8d495
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028059524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3028059524
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.307912032
Short name T277
Test name
Test status
Simulation time 78987705163 ps
CPU time 2376.78 seconds
Started Feb 29 02:08:37 PM PST 24
Finished Feb 29 02:48:15 PM PST 24
Peak memory 289184 kb
Host smart-1def5b81-7763-4a98-a12c-68f48ab64337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307912032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.307912032
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1175240747
Short name T482
Test name
Test status
Simulation time 48766302485 ps
CPU time 515.47 seconds
Started Feb 29 02:08:39 PM PST 24
Finished Feb 29 02:17:15 PM PST 24
Peak memory 247184 kb
Host smart-3994b4a7-9665-4129-89c4-14b91a767418
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175240747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1175240747
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2450380539
Short name T506
Test name
Test status
Simulation time 311283517 ps
CPU time 25.34 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:09:04 PM PST 24
Peak memory 248200 kb
Host smart-68c3dcf9-fb68-4168-86d5-ce006b77236c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24503
80539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2450380539
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2389987064
Short name T79
Test name
Test status
Simulation time 968737810 ps
CPU time 30.21 seconds
Started Feb 29 02:08:42 PM PST 24
Finished Feb 29 02:09:12 PM PST 24
Peak memory 247776 kb
Host smart-0811dee9-7f97-4a83-8b43-c17d83170db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899
87064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2389987064
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.846125971
Short name T81
Test name
Test status
Simulation time 187721391 ps
CPU time 29.63 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:09:08 PM PST 24
Peak memory 254824 kb
Host smart-2eb14262-6a49-4ed0-ac70-3760dc5072ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84612
5971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.846125971
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1811292977
Short name T576
Test name
Test status
Simulation time 88602879 ps
CPU time 10.31 seconds
Started Feb 29 02:08:36 PM PST 24
Finished Feb 29 02:08:47 PM PST 24
Peak memory 248268 kb
Host smart-7f17e748-6eb5-4204-9d0b-974a7325f2cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18112
92977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1811292977
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1692219263
Short name T709
Test name
Test status
Simulation time 69718314775 ps
CPU time 2465.17 seconds
Started Feb 29 02:08:39 PM PST 24
Finished Feb 29 02:49:44 PM PST 24
Peak memory 288368 kb
Host smart-6b3a3873-0e07-44f6-8736-beddc9117253
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692219263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1692219263
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2100596601
Short name T241
Test name
Test status
Simulation time 44577009 ps
CPU time 3.38 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:05:47 PM PST 24
Peak memory 248544 kb
Host smart-ce5b7979-64e0-4cda-8fa0-b2dc5a713731
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2100596601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2100596601
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1509030095
Short name T132
Test name
Test status
Simulation time 35761951570 ps
CPU time 835.73 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:19:37 PM PST 24
Peak memory 264732 kb
Host smart-1389695e-9437-4aa4-a7f9-9430f230c81e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509030095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1509030095
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1394161557
Short name T469
Test name
Test status
Simulation time 1501825069 ps
CPU time 18.22 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:06:00 PM PST 24
Peak memory 240080 kb
Host smart-c8bab4e6-a010-4fee-83c0-12571a1e994c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1394161557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1394161557
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2485185263
Short name T416
Test name
Test status
Simulation time 4584609603 ps
CPU time 259.33 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:10:00 PM PST 24
Peak memory 254628 kb
Host smart-12c272a2-f030-4baa-91d1-0c820d107ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24851
85263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2485185263
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2557991183
Short name T599
Test name
Test status
Simulation time 865485311 ps
CPU time 26.89 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:06:08 PM PST 24
Peak memory 255104 kb
Host smart-97fe6f98-7e3e-43fd-ad65-af9178017e7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25579
91183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2557991183
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.743242185
Short name T551
Test name
Test status
Simulation time 214606004185 ps
CPU time 1175.66 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:25:18 PM PST 24
Peak memory 272984 kb
Host smart-0f1dbe61-d6ef-4cea-8026-ac0e24a1ab55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743242185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.743242185
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3789733715
Short name T53
Test name
Test status
Simulation time 4743861596 ps
CPU time 54.41 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:06:35 PM PST 24
Peak memory 256456 kb
Host smart-93314f5a-794e-496f-892c-dd7ba435b0b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37897
33715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3789733715
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3051079446
Short name T454
Test name
Test status
Simulation time 120543304 ps
CPU time 16.03 seconds
Started Feb 29 02:05:40 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 254736 kb
Host smart-61b586f2-ee49-4d6c-88e0-c38511181ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
79446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3051079446
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2138414828
Short name T32
Test name
Test status
Simulation time 830862398 ps
CPU time 12.87 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 264740 kb
Host smart-ac91f55a-a205-47b1-9644-cf7de60df1ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2138414828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2138414828
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1155484871
Short name T495
Test name
Test status
Simulation time 1691280198 ps
CPU time 53.78 seconds
Started Feb 29 02:05:49 PM PST 24
Finished Feb 29 02:06:43 PM PST 24
Peak memory 248432 kb
Host smart-48fc24c5-ae48-4d08-b3ee-b4a46b467457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11554
84871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1155484871
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.66343415
Short name T439
Test name
Test status
Simulation time 1387073831 ps
CPU time 46.54 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 248280 kb
Host smart-75ef594d-42bb-43a0-af18-614b97bfcd8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66343
415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.66343415
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.769235135
Short name T474
Test name
Test status
Simulation time 57364233511 ps
CPU time 1295.79 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:27:20 PM PST 24
Peak memory 284108 kb
Host smart-a028ce15-4bad-489c-a635-a82dc556a5bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769235135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.769235135
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.795706905
Short name T84
Test name
Test status
Simulation time 34361689081 ps
CPU time 1979.53 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:38:47 PM PST 24
Peak memory 289552 kb
Host smart-cf055ebb-c619-4223-869a-e89dd81ba451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795706905 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.795706905
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1334285330
Short name T55
Test name
Test status
Simulation time 16181700299 ps
CPU time 1148.41 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:28:03 PM PST 24
Peak memory 271792 kb
Host smart-fed70429-00c3-4201-a4fc-b0009f9eb7fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334285330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1334285330
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3811480308
Short name T541
Test name
Test status
Simulation time 172408234 ps
CPU time 4.74 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:08:59 PM PST 24
Peak memory 238180 kb
Host smart-b9e53124-abda-44a0-b41e-8d9648e88e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
80308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3811480308
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.4102488840
Short name T409
Test name
Test status
Simulation time 231688686 ps
CPU time 20.37 seconds
Started Feb 29 02:08:42 PM PST 24
Finished Feb 29 02:09:03 PM PST 24
Peak memory 253928 kb
Host smart-a6144cf4-1aec-4a59-8202-e7e625dc913d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41024
88840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4102488840
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.667386753
Short name T205
Test name
Test status
Simulation time 54788703719 ps
CPU time 3143.93 seconds
Started Feb 29 02:08:58 PM PST 24
Finished Feb 29 03:01:22 PM PST 24
Peak memory 288796 kb
Host smart-bb9effc1-88fd-4867-ae52-6002d1551787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667386753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.667386753
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3042680278
Short name T485
Test name
Test status
Simulation time 13149180338 ps
CPU time 1496.26 seconds
Started Feb 29 02:08:53 PM PST 24
Finished Feb 29 02:33:50 PM PST 24
Peak memory 288664 kb
Host smart-df213aa2-270f-4313-9136-5b580e38d53e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042680278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3042680278
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2707655640
Short name T329
Test name
Test status
Simulation time 27852522343 ps
CPU time 291.82 seconds
Started Feb 29 02:08:56 PM PST 24
Finished Feb 29 02:13:49 PM PST 24
Peak memory 247240 kb
Host smart-296a22dc-22e0-4c1f-afd6-0396af0da9df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707655640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2707655640
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3130740496
Short name T629
Test name
Test status
Simulation time 322187625 ps
CPU time 17.75 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:08:56 PM PST 24
Peak memory 255252 kb
Host smart-28a3a719-9cd0-4c8d-9fc9-2aa86b410e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31307
40496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3130740496
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3298940011
Short name T384
Test name
Test status
Simulation time 68362053 ps
CPU time 7.04 seconds
Started Feb 29 02:08:39 PM PST 24
Finished Feb 29 02:08:46 PM PST 24
Peak memory 247732 kb
Host smart-fec510f1-7a85-4c01-88cc-f00e2fd15676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32989
40011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3298940011
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3389488027
Short name T447
Test name
Test status
Simulation time 297577763 ps
CPU time 15.44 seconds
Started Feb 29 02:08:52 PM PST 24
Finished Feb 29 02:09:07 PM PST 24
Peak memory 253164 kb
Host smart-31b3aef1-82a5-4d47-94fc-16bd0ddd30f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33894
88027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3389488027
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1384252381
Short name T448
Test name
Test status
Simulation time 378806236 ps
CPU time 34.79 seconds
Started Feb 29 02:08:38 PM PST 24
Finished Feb 29 02:09:13 PM PST 24
Peak memory 248260 kb
Host smart-59ec4a10-d2c5-4e0f-8798-556fdafaf1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13842
52381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1384252381
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4065007642
Short name T706
Test name
Test status
Simulation time 11553685455 ps
CPU time 1177.27 seconds
Started Feb 29 02:08:53 PM PST 24
Finished Feb 29 02:28:31 PM PST 24
Peak memory 288200 kb
Host smart-90d075fb-3d43-4de8-9bbc-075ad683f9fe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065007642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4065007642
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3664727253
Short name T399
Test name
Test status
Simulation time 68524532819 ps
CPU time 1432.87 seconds
Started Feb 29 02:08:56 PM PST 24
Finished Feb 29 02:32:50 PM PST 24
Peak memory 289160 kb
Host smart-77d9b1e5-0575-492d-b569-09d94addbc81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664727253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3664727253
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.64479334
Short name T387
Test name
Test status
Simulation time 2476728857 ps
CPU time 137.9 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:11:12 PM PST 24
Peak memory 256008 kb
Host smart-1102b3ac-2253-4aca-95e9-7d060e256fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64479
334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.64479334
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3268562707
Short name T528
Test name
Test status
Simulation time 221349221 ps
CPU time 28.96 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:09:23 PM PST 24
Peak memory 254724 kb
Host smart-a2a4b402-8b7d-4ab4-b139-972f52b07ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32685
62707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3268562707
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1065156596
Short name T71
Test name
Test status
Simulation time 110688132460 ps
CPU time 1299.78 seconds
Started Feb 29 02:08:55 PM PST 24
Finished Feb 29 02:30:36 PM PST 24
Peak memory 287984 kb
Host smart-c4cc291b-d38e-4583-8d21-acdf2e7052b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065156596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1065156596
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2459431357
Short name T44
Test name
Test status
Simulation time 554720455004 ps
CPU time 2727.02 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:54:21 PM PST 24
Peak memory 281132 kb
Host smart-bd8bcf22-5a4a-4abd-86bc-9858d3441d67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459431357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2459431357
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.447164286
Short name T549
Test name
Test status
Simulation time 19646021779 ps
CPU time 433.81 seconds
Started Feb 29 02:08:53 PM PST 24
Finished Feb 29 02:16:07 PM PST 24
Peak memory 248304 kb
Host smart-c197c1a3-5c5a-43ee-a07b-02f1bbef6f90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447164286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.447164286
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.485280087
Short name T269
Test name
Test status
Simulation time 277183084 ps
CPU time 27.26 seconds
Started Feb 29 02:08:53 PM PST 24
Finished Feb 29 02:09:21 PM PST 24
Peak memory 255108 kb
Host smart-2ccf8174-2f19-40f4-84bb-2d7fae8c0f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48528
0087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.485280087
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1614303986
Short name T620
Test name
Test status
Simulation time 434541408 ps
CPU time 28.04 seconds
Started Feb 29 02:08:58 PM PST 24
Finished Feb 29 02:09:26 PM PST 24
Peak memory 246928 kb
Host smart-ff3a6e6f-69a0-40f7-a834-387bf0adb6ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
03986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1614303986
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1086820789
Short name T270
Test name
Test status
Simulation time 241241283 ps
CPU time 9.43 seconds
Started Feb 29 02:08:58 PM PST 24
Finished Feb 29 02:09:08 PM PST 24
Peak memory 248284 kb
Host smart-6462a47f-e771-430d-9d78-dce6ebfb3b8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10868
20789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1086820789
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2323040326
Short name T267
Test name
Test status
Simulation time 958104566 ps
CPU time 20.94 seconds
Started Feb 29 02:08:54 PM PST 24
Finished Feb 29 02:09:15 PM PST 24
Peak memory 248240 kb
Host smart-a5b1630a-9b72-4015-b6e2-cc163cecea45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23230
40326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2323040326
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3396679604
Short name T41
Test name
Test status
Simulation time 27827378238 ps
CPU time 1333.83 seconds
Started Feb 29 02:08:55 PM PST 24
Finished Feb 29 02:31:09 PM PST 24
Peak memory 287820 kb
Host smart-f226885c-27f4-45f4-9f0f-27b4313e92c1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396679604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3396679604
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.674336006
Short name T600
Test name
Test status
Simulation time 120767132420 ps
CPU time 1229.4 seconds
Started Feb 29 02:09:07 PM PST 24
Finished Feb 29 02:29:37 PM PST 24
Peak memory 272916 kb
Host smart-1efd03ca-7a16-470e-a636-02b6010c2f64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674336006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.674336006
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2767234061
Short name T512
Test name
Test status
Simulation time 7338683358 ps
CPU time 248 seconds
Started Feb 29 02:09:07 PM PST 24
Finished Feb 29 02:13:15 PM PST 24
Peak memory 256560 kb
Host smart-ffd9227c-0821-4526-9c8c-fc6837c63fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
34061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2767234061
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2191144826
Short name T451
Test name
Test status
Simulation time 814057331 ps
CPU time 52.69 seconds
Started Feb 29 02:09:02 PM PST 24
Finished Feb 29 02:09:56 PM PST 24
Peak memory 247640 kb
Host smart-eef05f93-afd5-4ebe-946f-56e2bfab1486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21911
44826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2191144826
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2836291406
Short name T582
Test name
Test status
Simulation time 80082017199 ps
CPU time 1711.91 seconds
Started Feb 29 02:09:07 PM PST 24
Finished Feb 29 02:37:40 PM PST 24
Peak memory 271932 kb
Host smart-80b42016-0ed5-4271-b49b-2ffcf4a35f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836291406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2836291406
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.833230770
Short name T705
Test name
Test status
Simulation time 8605079735 ps
CPU time 121.61 seconds
Started Feb 29 02:09:08 PM PST 24
Finished Feb 29 02:11:10 PM PST 24
Peak memory 247192 kb
Host smart-f309d703-f928-4b21-abb7-d4b0608ae913
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833230770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.833230770
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.99746218
Short name T525
Test name
Test status
Simulation time 441775454 ps
CPU time 14.22 seconds
Started Feb 29 02:09:11 PM PST 24
Finished Feb 29 02:09:26 PM PST 24
Peak memory 248264 kb
Host smart-0fa6d1df-cd07-435f-a7a0-ce8f323106bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99746
218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.99746218
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3099539703
Short name T540
Test name
Test status
Simulation time 3463064457 ps
CPU time 38.5 seconds
Started Feb 29 02:09:11 PM PST 24
Finished Feb 29 02:09:50 PM PST 24
Peak memory 246852 kb
Host smart-497615cd-6c6d-4a0b-abdb-02470741295b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30995
39703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3099539703
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2613214341
Short name T21
Test name
Test status
Simulation time 555036261 ps
CPU time 35.4 seconds
Started Feb 29 02:09:08 PM PST 24
Finished Feb 29 02:09:44 PM PST 24
Peak memory 254856 kb
Host smart-103d8da5-b1fb-4322-821a-b7c7250eacd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26132
14341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2613214341
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.317944775
Short name T507
Test name
Test status
Simulation time 272949119 ps
CPU time 23.29 seconds
Started Feb 29 02:08:53 PM PST 24
Finished Feb 29 02:09:17 PM PST 24
Peak memory 248340 kb
Host smart-2a5a36dc-fb0a-44da-8a85-9ae5e972645f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31794
4775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.317944775
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.43347151
Short name T61
Test name
Test status
Simulation time 254755936918 ps
CPU time 3895.35 seconds
Started Feb 29 02:09:06 PM PST 24
Finished Feb 29 03:14:02 PM PST 24
Peak memory 305556 kb
Host smart-0f1317cc-07bf-42f5-9a60-caad748aade8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43347151 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.43347151
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3262595286
Short name T452
Test name
Test status
Simulation time 8756204730 ps
CPU time 86.03 seconds
Started Feb 29 02:09:25 PM PST 24
Finished Feb 29 02:10:51 PM PST 24
Peak memory 255820 kb
Host smart-27dfaab4-09ac-4286-9d2f-b62d064a77ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32625
95286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3262595286
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1937954849
Short name T442
Test name
Test status
Simulation time 127423136 ps
CPU time 6.36 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:09:27 PM PST 24
Peak memory 248764 kb
Host smart-54ac64cf-8809-46ba-94ba-2b8bd2cb0648
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
54849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1937954849
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3127891365
Short name T366
Test name
Test status
Simulation time 12791101194 ps
CPU time 871.94 seconds
Started Feb 29 02:09:25 PM PST 24
Finished Feb 29 02:23:57 PM PST 24
Peak memory 268344 kb
Host smart-49fec8d5-a47b-4811-9af7-541e6b1b9eba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127891365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3127891365
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1375405514
Short name T392
Test name
Test status
Simulation time 15245010710 ps
CPU time 1305.37 seconds
Started Feb 29 02:09:25 PM PST 24
Finished Feb 29 02:31:11 PM PST 24
Peak memory 288668 kb
Host smart-aed96b40-e301-4e42-8c69-f98154fe37fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375405514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1375405514
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2641976622
Short name T665
Test name
Test status
Simulation time 52398646246 ps
CPU time 276.58 seconds
Started Feb 29 02:09:25 PM PST 24
Finished Feb 29 02:14:02 PM PST 24
Peak memory 247000 kb
Host smart-a8f4af92-d3ba-47b8-8919-42f6eee66b4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641976622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2641976622
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.1802592795
Short name T585
Test name
Test status
Simulation time 1654025122 ps
CPU time 23.06 seconds
Started Feb 29 02:09:11 PM PST 24
Finished Feb 29 02:09:35 PM PST 24
Peak memory 256460 kb
Host smart-60af3429-be21-49f4-8bad-0f3cd9febaa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
92795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.1802592795
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.504308304
Short name T467
Test name
Test status
Simulation time 696618974 ps
CPU time 42.57 seconds
Started Feb 29 02:09:21 PM PST 24
Finished Feb 29 02:10:04 PM PST 24
Peak memory 254240 kb
Host smart-cd89a783-9dbf-4f76-897a-2b569287107b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50430
8304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.504308304
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1738823819
Short name T119
Test name
Test status
Simulation time 180874611 ps
CPU time 5.05 seconds
Started Feb 29 02:09:19 PM PST 24
Finished Feb 29 02:09:24 PM PST 24
Peak memory 238424 kb
Host smart-8d3d5fdc-1b8a-45fa-bf4f-50af14a876a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17388
23819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1738823819
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.166716118
Short name T415
Test name
Test status
Simulation time 9414612899 ps
CPU time 46.19 seconds
Started Feb 29 02:09:07 PM PST 24
Finished Feb 29 02:09:54 PM PST 24
Peak memory 248380 kb
Host smart-c2dcab73-62ea-41c9-953f-8d1fc4d178e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16671
6118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.166716118
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2719989534
Short name T702
Test name
Test status
Simulation time 67240233470 ps
CPU time 2537.3 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:51:37 PM PST 24
Peak memory 289020 kb
Host smart-44f170d7-da06-4b23-aaf7-3b8ada6a5aa0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719989534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2719989534
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2374630042
Short name T554
Test name
Test status
Simulation time 52457469220 ps
CPU time 1735.2 seconds
Started Feb 29 02:09:32 PM PST 24
Finished Feb 29 02:38:29 PM PST 24
Peak memory 288468 kb
Host smart-4ab35a3e-5efe-4f3a-b70c-bf62334bafeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374630042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2374630042
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1735945705
Short name T592
Test name
Test status
Simulation time 3253694464 ps
CPU time 191.15 seconds
Started Feb 29 02:09:21 PM PST 24
Finished Feb 29 02:12:33 PM PST 24
Peak memory 249284 kb
Host smart-6a2038c7-a72e-45de-ab66-f1be7fb55575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17359
45705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1735945705
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2955438321
Short name T675
Test name
Test status
Simulation time 1375497078 ps
CPU time 26.9 seconds
Started Feb 29 02:09:21 PM PST 24
Finished Feb 29 02:09:48 PM PST 24
Peak memory 253260 kb
Host smart-da8f6e85-eec6-4a56-9d61-f08bd6729438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29554
38321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2955438321
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.729937726
Short name T362
Test name
Test status
Simulation time 117114912904 ps
CPU time 1707.4 seconds
Started Feb 29 02:09:32 PM PST 24
Finished Feb 29 02:38:02 PM PST 24
Peak memory 288696 kb
Host smart-19b837cb-0a97-4631-9392-e4ef086060c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729937726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.729937726
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3227908147
Short name T483
Test name
Test status
Simulation time 215751326611 ps
CPU time 3537.41 seconds
Started Feb 29 02:09:39 PM PST 24
Finished Feb 29 03:08:37 PM PST 24
Peak memory 288884 kb
Host smart-8154f9f4-3768-4774-ac91-ad03ca70e715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227908147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3227908147
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.893000088
Short name T550
Test name
Test status
Simulation time 17156717601 ps
CPU time 121.84 seconds
Started Feb 29 02:09:34 PM PST 24
Finished Feb 29 02:11:37 PM PST 24
Peak memory 247008 kb
Host smart-eb59bec1-4448-471d-aa4c-24b3c7c54387
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893000088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.893000088
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3797038521
Short name T611
Test name
Test status
Simulation time 180228322 ps
CPU time 11.52 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:09:32 PM PST 24
Peak memory 248212 kb
Host smart-10a6c885-d262-4152-948f-af990e9c336e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
38521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3797038521
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2378785061
Short name T421
Test name
Test status
Simulation time 498234845 ps
CPU time 8.83 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:09:28 PM PST 24
Peak memory 249656 kb
Host smart-2da01bff-e2b6-4c39-ad29-bc50ae556acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
85061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2378785061
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.768905377
Short name T301
Test name
Test status
Simulation time 566192748 ps
CPU time 41.6 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:10:02 PM PST 24
Peak memory 253992 kb
Host smart-2c74fa2c-d36f-49e3-aafe-9759d3106153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76890
5377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.768905377
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1316550794
Short name T586
Test name
Test status
Simulation time 2171156331 ps
CPU time 19.11 seconds
Started Feb 29 02:09:20 PM PST 24
Finished Feb 29 02:09:39 PM PST 24
Peak memory 248360 kb
Host smart-3a7ec246-dc57-4e11-a725-5a1c0fd49866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13165
50794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1316550794
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3323633501
Short name T295
Test name
Test status
Simulation time 208896039889 ps
CPU time 2532.29 seconds
Started Feb 29 02:09:32 PM PST 24
Finished Feb 29 02:51:47 PM PST 24
Peak memory 289040 kb
Host smart-a7fa3170-100b-44a9-88a5-90718887db1e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323633501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3323633501
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2930029130
Short name T643
Test name
Test status
Simulation time 86896166638 ps
CPU time 3779.18 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 03:12:34 PM PST 24
Peak memory 305924 kb
Host smart-7584fece-9e71-4247-bc75-b905a6d6cc72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930029130 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2930029130
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3776541733
Short name T594
Test name
Test status
Simulation time 27016651091 ps
CPU time 1844.28 seconds
Started Feb 29 02:09:35 PM PST 24
Finished Feb 29 02:40:19 PM PST 24
Peak memory 281944 kb
Host smart-5c4283a3-cbd3-46cb-b277-7c9e15940767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776541733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3776541733
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1380824660
Short name T493
Test name
Test status
Simulation time 242588027 ps
CPU time 32.91 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 02:10:07 PM PST 24
Peak memory 246544 kb
Host smart-171e517d-3377-4953-ac95-29a67c0e19a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13808
24660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1380824660
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.4030221935
Short name T262
Test name
Test status
Simulation time 2322466590 ps
CPU time 38.9 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 02:10:13 PM PST 24
Peak memory 254792 kb
Host smart-02fb662b-2279-4a79-bfe6-22854825ccce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40302
21935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4030221935
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2373254947
Short name T640
Test name
Test status
Simulation time 63038353276 ps
CPU time 3101.1 seconds
Started Feb 29 02:09:36 PM PST 24
Finished Feb 29 03:01:18 PM PST 24
Peak memory 288916 kb
Host smart-b3d19380-a473-45c0-b699-281f8aa8d969
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373254947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2373254947
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1651977926
Short name T694
Test name
Test status
Simulation time 7762988726 ps
CPU time 156.72 seconds
Started Feb 29 02:09:35 PM PST 24
Finished Feb 29 02:12:12 PM PST 24
Peak memory 247136 kb
Host smart-fd6627ec-9e4d-4407-a746-09806cfbd735
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651977926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1651977926
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2403521592
Short name T426
Test name
Test status
Simulation time 491792290 ps
CPU time 38.04 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 02:10:12 PM PST 24
Peak memory 248344 kb
Host smart-60f29e72-e096-4c2b-9708-8881ab3a3fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24035
21592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2403521592
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1104900454
Short name T693
Test name
Test status
Simulation time 1013840444 ps
CPU time 13.33 seconds
Started Feb 29 02:09:33 PM PST 24
Finished Feb 29 02:09:47 PM PST 24
Peak memory 254324 kb
Host smart-6ea8502b-964a-4667-9aa6-079b635900c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11049
00454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1104900454
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.785234491
Short name T226
Test name
Test status
Simulation time 161006541 ps
CPU time 11.51 seconds
Started Feb 29 02:09:37 PM PST 24
Finished Feb 29 02:09:48 PM PST 24
Peak memory 253580 kb
Host smart-ca227923-47f5-4f0a-a7ef-906a8008bc33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78523
4491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.785234491
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3352129250
Short name T252
Test name
Test status
Simulation time 221522602 ps
CPU time 22.91 seconds
Started Feb 29 02:09:36 PM PST 24
Finished Feb 29 02:09:59 PM PST 24
Peak memory 248388 kb
Host smart-5ec9016b-16c5-4678-84b9-a85163417902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33521
29250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3352129250
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1211373681
Short name T679
Test name
Test status
Simulation time 82767592083 ps
CPU time 1617.7 seconds
Started Feb 29 02:09:48 PM PST 24
Finished Feb 29 02:36:46 PM PST 24
Peak memory 272200 kb
Host smart-d700c60c-1dec-4dfd-91f1-56802f52afd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211373681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1211373681
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2625560292
Short name T612
Test name
Test status
Simulation time 8013513859 ps
CPU time 117.15 seconds
Started Feb 29 02:09:49 PM PST 24
Finished Feb 29 02:11:47 PM PST 24
Peak memory 247744 kb
Host smart-c1d56e6b-0cf0-4db0-96cc-e3b99a19557d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26255
60292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2625560292
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1800521565
Short name T91
Test name
Test status
Simulation time 958939993 ps
CPU time 37.85 seconds
Started Feb 29 02:09:47 PM PST 24
Finished Feb 29 02:10:25 PM PST 24
Peak memory 246524 kb
Host smart-cbf485cf-3fbc-4197-ab2e-e2f6d39b05b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18005
21565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1800521565
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3229863592
Short name T476
Test name
Test status
Simulation time 26253454919 ps
CPU time 1363.41 seconds
Started Feb 29 02:10:03 PM PST 24
Finished Feb 29 02:32:47 PM PST 24
Peak memory 272332 kb
Host smart-6b1d254d-f19e-4332-9b7d-3ad417189ef8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229863592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3229863592
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1741375310
Short name T460
Test name
Test status
Simulation time 76543063975 ps
CPU time 2594.88 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 02:53:19 PM PST 24
Peak memory 288500 kb
Host smart-efe43f4b-a85c-431b-afde-1e82394f1886
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741375310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1741375310
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.778233045
Short name T553
Test name
Test status
Simulation time 6634817545 ps
CPU time 138.68 seconds
Started Feb 29 02:09:47 PM PST 24
Finished Feb 29 02:12:06 PM PST 24
Peak memory 247184 kb
Host smart-a84ddede-d5a3-40ba-91dc-477c6ec689ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778233045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.778233045
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3717287392
Short name T435
Test name
Test status
Simulation time 1463187855 ps
CPU time 40.67 seconds
Started Feb 29 02:09:49 PM PST 24
Finished Feb 29 02:10:29 PM PST 24
Peak memory 248268 kb
Host smart-5881bfd3-5b8b-4152-9dbb-7e89be73990b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37172
87392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3717287392
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.208008951
Short name T437
Test name
Test status
Simulation time 983284510 ps
CPU time 26.74 seconds
Started Feb 29 02:09:48 PM PST 24
Finished Feb 29 02:10:15 PM PST 24
Peak memory 246444 kb
Host smart-b0202f26-c521-4de9-bd44-d9beb94e4b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20800
8951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.208008951
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2743332717
Short name T290
Test name
Test status
Simulation time 1026968874 ps
CPU time 29.75 seconds
Started Feb 29 02:09:48 PM PST 24
Finished Feb 29 02:10:18 PM PST 24
Peak memory 254960 kb
Host smart-e5cc460a-a48f-4385-a403-5cb5278b2a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27433
32717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2743332717
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3761117558
Short name T652
Test name
Test status
Simulation time 339158246 ps
CPU time 21.34 seconds
Started Feb 29 02:09:48 PM PST 24
Finished Feb 29 02:10:09 PM PST 24
Peak memory 248240 kb
Host smart-02377c70-869f-44af-bd10-4290bdf874f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37611
17558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3761117558
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2957988856
Short name T284
Test name
Test status
Simulation time 78936932170 ps
CPU time 2988.09 seconds
Started Feb 29 02:10:07 PM PST 24
Finished Feb 29 02:59:56 PM PST 24
Peak memory 288588 kb
Host smart-f82ddf7e-c9d9-4a67-9fe0-64b287efd0ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957988856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2957988856
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1728004635
Short name T501
Test name
Test status
Simulation time 94625957534 ps
CPU time 2692.72 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:54:58 PM PST 24
Peak memory 285544 kb
Host smart-ff00861c-7fa7-4905-8705-11e9850241b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728004635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1728004635
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.2697492880
Short name T499
Test name
Test status
Simulation time 326555058 ps
CPU time 25.28 seconds
Started Feb 29 02:10:02 PM PST 24
Finished Feb 29 02:10:28 PM PST 24
Peak memory 255404 kb
Host smart-8b70f4da-5d3c-48c6-985b-79c4015a5eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26974
92880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.2697492880
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.2413356213
Short name T83
Test name
Test status
Simulation time 180766338 ps
CPU time 20.65 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 02:10:24 PM PST 24
Peak memory 254548 kb
Host smart-47c89be1-bf6c-4b48-aa04-0ac1e96f0dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24133
56213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.2413356213
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1826699515
Short name T46
Test name
Test status
Simulation time 134702741017 ps
CPU time 1981.87 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:43:07 PM PST 24
Peak memory 272856 kb
Host smart-06ed493a-1207-4c09-b38c-482ce670c404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826699515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1826699515
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3157425550
Short name T552
Test name
Test status
Simulation time 209472061725 ps
CPU time 2017.82 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 02:43:42 PM PST 24
Peak memory 289112 kb
Host smart-ccdd38ae-7b62-46ae-8fbe-b75e22f5dc43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157425550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3157425550
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.789161648
Short name T98
Test name
Test status
Simulation time 39984123239 ps
CPU time 424.35 seconds
Started Feb 29 02:10:06 PM PST 24
Finished Feb 29 02:17:10 PM PST 24
Peak memory 247224 kb
Host smart-d1a5800b-1e2f-4f19-ae98-516c15585b5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789161648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.789161648
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.276488301
Short name T486
Test name
Test status
Simulation time 36857676 ps
CPU time 4.25 seconds
Started Feb 29 02:10:07 PM PST 24
Finished Feb 29 02:10:12 PM PST 24
Peak memory 240068 kb
Host smart-5cbe4b7d-2f77-443a-ad2c-6ef394cb29a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27648
8301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.276488301
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3564081703
Short name T682
Test name
Test status
Simulation time 1387972622 ps
CPU time 23.46 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:10:29 PM PST 24
Peak memory 246584 kb
Host smart-9692d086-cffd-4d01-8e89-401041578592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35640
81703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3564081703
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1965629176
Short name T393
Test name
Test status
Simulation time 1247018840 ps
CPU time 48.36 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:10:53 PM PST 24
Peak memory 255104 kb
Host smart-5dcbeb4c-b5e9-4f84-8a70-232f37e05f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
29176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1965629176
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3433418990
Short name T114
Test name
Test status
Simulation time 94350106 ps
CPU time 9.36 seconds
Started Feb 29 02:10:06 PM PST 24
Finished Feb 29 02:10:15 PM PST 24
Peak memory 248268 kb
Host smart-cca21f44-b7cd-4273-a27c-aad38d3f5286
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34334
18990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3433418990
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2573012989
Short name T508
Test name
Test status
Simulation time 180910778814 ps
CPU time 3282.21 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 03:04:47 PM PST 24
Peak memory 297444 kb
Host smart-1d345754-c85f-422b-9cfc-09f0746cfb2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573012989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2573012989
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.728202304
Short name T328
Test name
Test status
Simulation time 38926724240 ps
CPU time 2356.22 seconds
Started Feb 29 02:10:18 PM PST 24
Finished Feb 29 02:49:35 PM PST 24
Peak memory 288492 kb
Host smart-f1ba0037-9f9d-433d-a0c3-8e2ad24dc5c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728202304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.728202304
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.734485480
Short name T465
Test name
Test status
Simulation time 1863371218 ps
CPU time 73.32 seconds
Started Feb 29 02:10:21 PM PST 24
Finished Feb 29 02:11:35 PM PST 24
Peak memory 255532 kb
Host smart-f76cdcc4-2964-4bd8-84b0-f02343fb27f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73448
5480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.734485480
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2524077104
Short name T116
Test name
Test status
Simulation time 907794168 ps
CPU time 58.45 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:11:03 PM PST 24
Peak memory 254720 kb
Host smart-99a40b14-a7b6-43cc-ae13-31bd95f2972d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25240
77104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2524077104
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.298743717
Short name T313
Test name
Test status
Simulation time 100412417238 ps
CPU time 1855.71 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 02:41:16 PM PST 24
Peak memory 270036 kb
Host smart-533c9781-351a-4dd1-b5b0-333b90e9f3da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298743717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.298743717
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2862603508
Short name T570
Test name
Test status
Simulation time 143609773059 ps
CPU time 1116.73 seconds
Started Feb 29 02:10:18 PM PST 24
Finished Feb 29 02:28:55 PM PST 24
Peak memory 272796 kb
Host smart-12526452-0e3d-4d77-88c3-065bf321b8ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862603508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2862603508
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1960624662
Short name T333
Test name
Test status
Simulation time 79686437965 ps
CPU time 169.11 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 02:13:10 PM PST 24
Peak memory 246856 kb
Host smart-5d1744a5-6710-446f-8161-5139450a318a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960624662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1960624662
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1717591688
Short name T494
Test name
Test status
Simulation time 1188964284 ps
CPU time 43.72 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 02:10:48 PM PST 24
Peak memory 248364 kb
Host smart-3240a51f-2336-4daa-b828-51bd8047bf8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17175
91688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1717591688
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.293637461
Short name T386
Test name
Test status
Simulation time 231723773 ps
CPU time 5.28 seconds
Started Feb 29 02:10:04 PM PST 24
Finished Feb 29 02:10:10 PM PST 24
Peak memory 238360 kb
Host smart-59f1689a-95fb-4389-a643-f27673f725f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
7461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.293637461
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1944905840
Short name T603
Test name
Test status
Simulation time 1159072520 ps
CPU time 64.99 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 02:11:25 PM PST 24
Peak memory 247684 kb
Host smart-f8c2598f-8f33-40ea-98d3-386a103bcc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19449
05840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1944905840
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.4264797657
Short name T659
Test name
Test status
Simulation time 295571400 ps
CPU time 32.98 seconds
Started Feb 29 02:10:05 PM PST 24
Finished Feb 29 02:10:38 PM PST 24
Peak memory 248216 kb
Host smart-796dcf50-66ad-4d5a-b581-9cdb16d64371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42647
97657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.4264797657
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3755829114
Short name T30
Test name
Test status
Simulation time 55625823454 ps
CPU time 3379.89 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 03:06:41 PM PST 24
Peak memory 289240 kb
Host smart-c0ef93a8-8105-49d0-86b5-c88d35ee9342
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755829114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3755829114
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3694467443
Short name T595
Test name
Test status
Simulation time 28045791418 ps
CPU time 1663.43 seconds
Started Feb 29 02:10:21 PM PST 24
Finished Feb 29 02:38:05 PM PST 24
Peak memory 272864 kb
Host smart-2415aae0-f1dd-4214-abb7-cf4159626828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694467443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3694467443
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.635134016
Short name T642
Test name
Test status
Simulation time 1229451483 ps
CPU time 68.54 seconds
Started Feb 29 02:10:16 PM PST 24
Finished Feb 29 02:11:25 PM PST 24
Peak memory 255516 kb
Host smart-5a7244a2-c93b-436e-a4a4-30dcbb6223d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63513
4016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.635134016
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1127193261
Short name T446
Test name
Test status
Simulation time 501130099 ps
CPU time 27.75 seconds
Started Feb 29 02:10:18 PM PST 24
Finished Feb 29 02:10:46 PM PST 24
Peak memory 253788 kb
Host smart-6fcb9e5e-c4e2-4e40-9987-fc8bbd624d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11271
93261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1127193261
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.839546710
Short name T618
Test name
Test status
Simulation time 71791403140 ps
CPU time 1327.79 seconds
Started Feb 29 02:10:17 PM PST 24
Finished Feb 29 02:32:25 PM PST 24
Peak memory 286200 kb
Host smart-c2ccc40d-e1ce-46fc-aa83-70ce4f0cf24f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839546710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.839546710
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3509759530
Short name T67
Test name
Test status
Simulation time 12683139965 ps
CPU time 585.81 seconds
Started Feb 29 02:10:18 PM PST 24
Finished Feb 29 02:20:05 PM PST 24
Peak memory 264732 kb
Host smart-6ee4f162-e1c9-46d3-9a85-59d2db121b46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509759530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3509759530
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.158914715
Short name T346
Test name
Test status
Simulation time 5533626068 ps
CPU time 141 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 02:12:42 PM PST 24
Peak memory 248296 kb
Host smart-54333d99-7775-4110-8729-1ec9b46524b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158914715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.158914715
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2295574065
Short name T54
Test name
Test status
Simulation time 404811802 ps
CPU time 25.43 seconds
Started Feb 29 02:10:22 PM PST 24
Finished Feb 29 02:10:48 PM PST 24
Peak memory 254444 kb
Host smart-217b4e27-f746-463e-a6d2-691d51c086b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22955
74065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2295574065
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1213696383
Short name T517
Test name
Test status
Simulation time 189990919 ps
CPU time 13.38 seconds
Started Feb 29 02:10:22 PM PST 24
Finished Feb 29 02:10:36 PM PST 24
Peak memory 253384 kb
Host smart-254e7140-fd76-4fa5-b40d-08862d366192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
96383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1213696383
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2559778587
Short name T602
Test name
Test status
Simulation time 157469604 ps
CPU time 11.67 seconds
Started Feb 29 02:10:20 PM PST 24
Finished Feb 29 02:10:32 PM PST 24
Peak memory 246504 kb
Host smart-99929d8b-5b74-40c0-a4d8-de18aee6ff02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25597
78587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2559778587
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.766367585
Short name T685
Test name
Test status
Simulation time 2082982809 ps
CPU time 67.7 seconds
Started Feb 29 02:10:18 PM PST 24
Finished Feb 29 02:11:26 PM PST 24
Peak memory 248292 kb
Host smart-8c000bb2-8dd6-4de9-918e-c444348faa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76636
7585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.766367585
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2255081472
Short name T246
Test name
Test status
Simulation time 88107658 ps
CPU time 3.41 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:05:46 PM PST 24
Peak memory 248512 kb
Host smart-445a000b-3e1c-49ae-864c-50e8750be897
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2255081472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2255081472
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3829357562
Short name T436
Test name
Test status
Simulation time 39395386668 ps
CPU time 2398.82 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:45:42 PM PST 24
Peak memory 288496 kb
Host smart-f46bd587-6e35-43ff-a168-1270eb3ebe9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829357562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3829357562
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.122666531
Short name T630
Test name
Test status
Simulation time 449306710 ps
CPU time 21.82 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:06:05 PM PST 24
Peak memory 240056 kb
Host smart-1db7b3ad-bc31-4582-9c3f-98de0c3f08db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=122666531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.122666531
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.66236886
Short name T459
Test name
Test status
Simulation time 9266245861 ps
CPU time 132.39 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:07:57 PM PST 24
Peak memory 256004 kb
Host smart-57d26502-9820-4f23-a792-558e4e610363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66236
886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.66236886
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2490301877
Short name T648
Test name
Test status
Simulation time 2269590542 ps
CPU time 68.32 seconds
Started Feb 29 02:05:43 PM PST 24
Finished Feb 29 02:06:52 PM PST 24
Peak memory 254640 kb
Host smart-53725d4d-de16-48c4-9aab-c96f3375d3ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903
01877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2490301877
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2333050087
Short name T250
Test name
Test status
Simulation time 45329231430 ps
CPU time 876.44 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:20:22 PM PST 24
Peak memory 271988 kb
Host smart-5f257684-e42b-473e-b936-d54876cc3cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333050087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2333050087
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4201583988
Short name T466
Test name
Test status
Simulation time 91263215394 ps
CPU time 2490.53 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:47:17 PM PST 24
Peak memory 288916 kb
Host smart-28f43d87-06d4-4cee-aede-c151d2fa3974
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201583988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4201583988
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3683156833
Short name T461
Test name
Test status
Simulation time 498508842 ps
CPU time 29.71 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:06:14 PM PST 24
Peak memory 248440 kb
Host smart-aa461364-c090-487b-b528-4406cc1f29dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36831
56833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3683156833
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3212784057
Short name T703
Test name
Test status
Simulation time 88309371 ps
CPU time 10.75 seconds
Started Feb 29 02:05:44 PM PST 24
Finished Feb 29 02:05:55 PM PST 24
Peak memory 246540 kb
Host smart-1ccde901-7599-4dd4-80c7-29b72a7917df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32127
84057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3212784057
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.678093675
Short name T117
Test name
Test status
Simulation time 757452332 ps
CPU time 46.86 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 254704 kb
Host smart-d58ad6d1-2101-4075-ae29-789e1d50eaea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67809
3675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.678093675
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3361408165
Short name T589
Test name
Test status
Simulation time 475689131 ps
CPU time 20.47 seconds
Started Feb 29 02:05:42 PM PST 24
Finished Feb 29 02:06:03 PM PST 24
Peak memory 248308 kb
Host smart-85956e7f-719c-480c-927e-804247769d47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33614
08165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3361408165
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.322461805
Short name T711
Test name
Test status
Simulation time 13226909473 ps
CPU time 358.18 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:11:45 PM PST 24
Peak memory 256496 kb
Host smart-16bda446-ea13-4b44-b702-e67b366fbbaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322461805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_hand
ler_stress_all.322461805
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.43839627
Short name T244
Test name
Test status
Simulation time 44187973 ps
CPU time 3.91 seconds
Started Feb 29 02:05:45 PM PST 24
Finished Feb 29 02:05:49 PM PST 24
Peak memory 248560 kb
Host smart-412e5b5a-df6c-4219-93df-cc910a2a3b74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=43839627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.43839627
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3680030798
Short name T537
Test name
Test status
Simulation time 19093215083 ps
CPU time 1257.73 seconds
Started Feb 29 02:05:48 PM PST 24
Finished Feb 29 02:26:46 PM PST 24
Peak memory 264696 kb
Host smart-3d14dcc5-1daa-4477-994d-df306e3dacaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680030798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3680030798
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.45437045
Short name T375
Test name
Test status
Simulation time 1332609762 ps
CPU time 28.79 seconds
Started Feb 29 02:05:49 PM PST 24
Finished Feb 29 02:06:19 PM PST 24
Peak memory 240056 kb
Host smart-35e1bae6-4f1c-4c9f-bc1f-3baccbcdf59c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=45437045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.45437045
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1426190140
Short name T579
Test name
Test status
Simulation time 6752856762 ps
CPU time 208.5 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:09:15 PM PST 24
Peak memory 250416 kb
Host smart-8929979c-8a00-4a9b-89ae-11b7caac2d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
90140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1426190140
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4051264960
Short name T521
Test name
Test status
Simulation time 217985480899 ps
CPU time 2873.2 seconds
Started Feb 29 02:05:50 PM PST 24
Finished Feb 29 02:53:44 PM PST 24
Peak memory 288792 kb
Host smart-dcc3b9a1-1b2c-4ab9-880c-f21b55dc2175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051264960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4051264960
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2466971882
Short name T351
Test name
Test status
Simulation time 16527356057 ps
CPU time 349.93 seconds
Started Feb 29 02:05:48 PM PST 24
Finished Feb 29 02:11:38 PM PST 24
Peak memory 246960 kb
Host smart-578ed745-bb5a-4a10-9f07-0a9f40609fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466971882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2466971882
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2411549223
Short name T547
Test name
Test status
Simulation time 503792980 ps
CPU time 32.24 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:06:18 PM PST 24
Peak memory 254956 kb
Host smart-e988b4b6-c6ba-43c5-b6d4-dd71e16f6861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
49223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2411549223
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3233751661
Short name T593
Test name
Test status
Simulation time 9708978531 ps
CPU time 33.46 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:06:21 PM PST 24
Peak memory 247020 kb
Host smart-092aea12-14e5-4fca-b7d3-8d35bbcc4c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
51661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3233751661
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1264407322
Short name T546
Test name
Test status
Simulation time 681271564 ps
CPU time 51.2 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:06:38 PM PST 24
Peak memory 254704 kb
Host smart-5508950c-7f96-4e85-b843-e58c1267d643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12644
07322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1264407322
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4188030825
Short name T444
Test name
Test status
Simulation time 449656389 ps
CPU time 20.57 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:06:07 PM PST 24
Peak memory 248276 kb
Host smart-14f70d3f-868c-43b7-a789-46d864c5035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41880
30825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4188030825
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1487367378
Short name T77
Test name
Test status
Simulation time 613620696 ps
CPU time 63.58 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:06:57 PM PST 24
Peak memory 248628 kb
Host smart-8f01b92b-f141-4242-8b9f-be6ece20d8a5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487367378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1487367378
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.893599168
Short name T196
Test name
Test status
Simulation time 278458237826 ps
CPU time 6236.64 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 03:49:44 PM PST 24
Peak memory 338468 kb
Host smart-b49225f6-7754-4b38-b6fd-89034e9d21bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893599168 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.893599168
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2392347192
Short name T218
Test name
Test status
Simulation time 22437331 ps
CPU time 2.61 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:05:57 PM PST 24
Peak memory 248564 kb
Host smart-2e79ecbe-16ec-4e76-b467-68f8cb512575
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2392347192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2392347192
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.159015080
Short name T683
Test name
Test status
Simulation time 88188429395 ps
CPU time 2689.08 seconds
Started Feb 29 02:05:40 PM PST 24
Finished Feb 29 02:50:29 PM PST 24
Peak memory 284540 kb
Host smart-52638f1f-6ba5-49d7-9fe7-2deb42080dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159015080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.159015080
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3970627728
Short name T519
Test name
Test status
Simulation time 1102547779 ps
CPU time 15.74 seconds
Started Feb 29 02:05:57 PM PST 24
Finished Feb 29 02:06:13 PM PST 24
Peak memory 247908 kb
Host smart-97646a03-cb59-401e-a511-7e7e81cf8ba9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3970627728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3970627728
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2970419158
Short name T481
Test name
Test status
Simulation time 8261485106 ps
CPU time 214.79 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:09:22 PM PST 24
Peak memory 256480 kb
Host smart-e14904b4-ef19-4db1-be5d-2e24f7058292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704
19158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2970419158
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.628255421
Short name T397
Test name
Test status
Simulation time 63766954 ps
CPU time 5.5 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:05:52 PM PST 24
Peak memory 238356 kb
Host smart-292c02ff-8165-4cda-a73f-4bcbf12da7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62825
5421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.628255421
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2250038905
Short name T343
Test name
Test status
Simulation time 34240873407 ps
CPU time 709.23 seconds
Started Feb 29 02:05:56 PM PST 24
Finished Feb 29 02:17:46 PM PST 24
Peak memory 264732 kb
Host smart-6f7407c7-0bce-4a5d-85fc-012c6dfdf9ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250038905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2250038905
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2181137273
Short name T631
Test name
Test status
Simulation time 20960562895 ps
CPU time 941.34 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:21:36 PM PST 24
Peak memory 265696 kb
Host smart-e075d1a3-367a-4c60-9787-aaaf588c7996
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181137273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2181137273
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.57369238
Short name T663
Test name
Test status
Simulation time 9321240193 ps
CPU time 370.71 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:12:06 PM PST 24
Peak memory 246980 kb
Host smart-e1d4e52e-b078-4209-8f28-33f7dd689294
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57369238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.57369238
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.288236921
Short name T492
Test name
Test status
Simulation time 613823482 ps
CPU time 23.22 seconds
Started Feb 29 02:05:46 PM PST 24
Finished Feb 29 02:06:09 PM PST 24
Peak memory 248280 kb
Host smart-6a63ec00-bb35-404b-a55b-e50efd185010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
6921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.288236921
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2333574520
Short name T382
Test name
Test status
Simulation time 337251162 ps
CPU time 21.67 seconds
Started Feb 29 02:05:47 PM PST 24
Finished Feb 29 02:06:09 PM PST 24
Peak memory 254520 kb
Host smart-7d8dc42b-c62c-4d54-8eef-12de2d7d1678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23335
74520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2333574520
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1359503003
Short name T411
Test name
Test status
Simulation time 160070733 ps
CPU time 4.5 seconds
Started Feb 29 02:05:41 PM PST 24
Finished Feb 29 02:05:46 PM PST 24
Peak memory 238340 kb
Host smart-ba2bb654-763a-4583-9e30-23989e4c6304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13595
03003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1359503003
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1212094116
Short name T708
Test name
Test status
Simulation time 736506767 ps
CPU time 41.85 seconds
Started Feb 29 02:05:48 PM PST 24
Finished Feb 29 02:06:30 PM PST 24
Peak memory 248276 kb
Host smart-ff4fe24c-ef89-47c0-b72e-9d1906b4ca8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12120
94116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1212094116
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2434920382
Short name T292
Test name
Test status
Simulation time 188482450068 ps
CPU time 2138.43 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:41:33 PM PST 24
Peak memory 272860 kb
Host smart-c3f19c4e-865d-4f35-acff-a6cc99adf611
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434920382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2434920382
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.500518330
Short name T234
Test name
Test status
Simulation time 86743713 ps
CPU time 3.85 seconds
Started Feb 29 02:05:52 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 248572 kb
Host smart-c5f233cf-87e0-474a-88af-62272238f7d6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=500518330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.500518330
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1404431652
Short name T487
Test name
Test status
Simulation time 16923570478 ps
CPU time 1496.89 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:30:51 PM PST 24
Peak memory 288548 kb
Host smart-01ebaded-5d5d-46cf-93a7-cf6ffec64446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404431652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1404431652
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3602575580
Short name T616
Test name
Test status
Simulation time 1102809394 ps
CPU time 28.24 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:06:21 PM PST 24
Peak memory 240160 kb
Host smart-0a2c7268-34f0-4a36-abc4-baab33027c38
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3602575580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3602575580
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.605832615
Short name T396
Test name
Test status
Simulation time 2149888372 ps
CPU time 88.8 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:07:24 PM PST 24
Peak memory 255960 kb
Host smart-e04f546f-aa29-491b-8d32-31da1d502370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60583
2615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.605832615
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.712284799
Short name T627
Test name
Test status
Simulation time 2178890817 ps
CPU time 35.13 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:06:30 PM PST 24
Peak memory 254956 kb
Host smart-cba97a07-7242-49c1-a026-9f691dbf232f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71228
4799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.712284799
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2198680869
Short name T14
Test name
Test status
Simulation time 30785829829 ps
CPU time 2107.41 seconds
Started Feb 29 02:05:52 PM PST 24
Finished Feb 29 02:41:00 PM PST 24
Peak memory 284940 kb
Host smart-36b6287e-16ce-49e2-9e39-be75730ca8a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198680869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2198680869
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.952081017
Short name T65
Test name
Test status
Simulation time 7101656356 ps
CPU time 80.1 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:07:13 PM PST 24
Peak memory 254044 kb
Host smart-a535d130-d6bc-403e-9022-8c77f8f3dafc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952081017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.952081017
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.685941624
Short name T597
Test name
Test status
Simulation time 2205894123 ps
CPU time 42.35 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:06:37 PM PST 24
Peak memory 255076 kb
Host smart-f288f43b-3de6-4736-9122-08f216ed4e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68594
1624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.685941624
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3809586531
Short name T95
Test name
Test status
Simulation time 628566609 ps
CPU time 37.89 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:32 PM PST 24
Peak memory 254732 kb
Host smart-b92ff840-1cd0-445b-a58d-db7d63967855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
86531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3809586531
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3001217324
Short name T45
Test name
Test status
Simulation time 2180990898 ps
CPU time 31.67 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:06:25 PM PST 24
Peak memory 255132 kb
Host smart-a7dd9e02-7e57-4df1-b74a-8871d6c2d9b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30012
17324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3001217324
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3478546600
Short name T462
Test name
Test status
Simulation time 857064799 ps
CPU time 59.95 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:55 PM PST 24
Peak memory 256416 kb
Host smart-fe3b7517-7e48-44ce-aef7-bca4b5fc69bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34785
46600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3478546600
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4225379681
Short name T299
Test name
Test status
Simulation time 18081045744 ps
CPU time 1831.93 seconds
Started Feb 29 02:05:52 PM PST 24
Finished Feb 29 02:36:25 PM PST 24
Peak memory 297236 kb
Host smart-91915a78-2e7d-4d20-8fde-0b41c50035ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225379681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4225379681
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.885754824
Short name T240
Test name
Test status
Simulation time 32864713 ps
CPU time 3.64 seconds
Started Feb 29 02:05:57 PM PST 24
Finished Feb 29 02:06:01 PM PST 24
Peak memory 248008 kb
Host smart-4bc97b1d-39b3-41bb-aecc-c2d030134bea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=885754824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.885754824
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.233524317
Short name T562
Test name
Test status
Simulation time 55947203274 ps
CPU time 1660.16 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:33:34 PM PST 24
Peak memory 272128 kb
Host smart-5150ae8a-2a33-45bb-b5a2-893877ece337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233524317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.233524317
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1874417928
Short name T33
Test name
Test status
Simulation time 606131299 ps
CPU time 17.81 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:06:13 PM PST 24
Peak memory 240036 kb
Host smart-4d6f42a6-eb6c-4d1f-a451-cd52599b1ac8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1874417928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1874417928
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4177537242
Short name T634
Test name
Test status
Simulation time 178960583 ps
CPU time 14.13 seconds
Started Feb 29 02:05:57 PM PST 24
Finished Feb 29 02:06:12 PM PST 24
Peak memory 248288 kb
Host smart-785684e1-8f67-426a-8646-60e1d302c0d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41775
37242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4177537242
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3055783299
Short name T220
Test name
Test status
Simulation time 50334792 ps
CPU time 7.31 seconds
Started Feb 29 02:05:55 PM PST 24
Finished Feb 29 02:06:02 PM PST 24
Peak memory 250916 kb
Host smart-e6240727-3edc-4a39-9a76-c6b178cf9e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30557
83299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3055783299
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1910859133
Short name T645
Test name
Test status
Simulation time 48404601636 ps
CPU time 1547.21 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:31:42 PM PST 24
Peak memory 272356 kb
Host smart-98e3b9a8-09c9-40df-abf0-d5dbea0333bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910859133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1910859133
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2968982332
Short name T496
Test name
Test status
Simulation time 129945653760 ps
CPU time 1870.94 seconds
Started Feb 29 02:05:53 PM PST 24
Finished Feb 29 02:37:05 PM PST 24
Peak memory 271952 kb
Host smart-fec9b85a-9616-4500-84fd-870b1b0dab8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968982332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2968982332
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3265458398
Short name T704
Test name
Test status
Simulation time 8906710071 ps
CPU time 370.05 seconds
Started Feb 29 02:05:59 PM PST 24
Finished Feb 29 02:12:09 PM PST 24
Peak memory 256516 kb
Host smart-9121240c-05c3-4796-8de1-68b37c48f9c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265458398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3265458398
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1419609783
Short name T430
Test name
Test status
Simulation time 97141382 ps
CPU time 12.87 seconds
Started Feb 29 02:05:59 PM PST 24
Finished Feb 29 02:06:13 PM PST 24
Peak memory 248260 kb
Host smart-260defb6-0f3b-4134-80c0-328a0683d3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
09783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1419609783
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.928578275
Short name T89
Test name
Test status
Simulation time 1191438778 ps
CPU time 20.96 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:15 PM PST 24
Peak memory 248440 kb
Host smart-65668d2d-0d15-49fa-89d9-294022e769a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92857
8275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.928578275
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3561168709
Short name T458
Test name
Test status
Simulation time 5041933385 ps
CPU time 42.51 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 02:06:37 PM PST 24
Peak memory 248288 kb
Host smart-9ab99292-1503-4a05-83af-e15ba9b7e00c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35611
68709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3561168709
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2565577721
Short name T90
Test name
Test status
Simulation time 35420539391 ps
CPU time 1456.88 seconds
Started Feb 29 02:05:56 PM PST 24
Finished Feb 29 02:30:14 PM PST 24
Peak memory 288820 kb
Host smart-b12af217-d808-4b73-8ac1-fd236722c214
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565577721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2565577721
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.612623288
Short name T35
Test name
Test status
Simulation time 374585394195 ps
CPU time 7133.72 seconds
Started Feb 29 02:05:54 PM PST 24
Finished Feb 29 04:04:49 PM PST 24
Peak memory 354612 kb
Host smart-60f80746-887d-4da3-83aa-35a76a37b152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612623288 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.612623288
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%