Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	74421	1			T1	7		T12	10		T46	3
class_i[0x1]	38076	1			T1	2		T10	5		T11	9
class_i[0x2]	83798	1			T1	59		T3	48		T5	3383
class_i[0x3]	56525	1			T3	434		T11	1		T17	10

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60517	1			T1	14		T3	277		T5	856
alert[0x1]	62081	1			T1	9		T3	1		T5	829
alert[0x2]	66588	1			T1	24		T5	772		T10	1
alert[0x3]	63634	1			T1	21		T3	204		T5	926

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

252536

1

T1

68

T3

482

T5

3383

esc_ping_fail

284

1

T10

5

T11

11

T12

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60420	1			T1	14		T3	277		T5	856
esc_integrity_fail	alert[0x1]	62017	1			T1	9		T3	1		T5	829
esc_integrity_fail	alert[0x2]	66521	1			T1	24		T5	772		T12	2
esc_integrity_fail	alert[0x3]	63578	1			T1	21		T3	204		T5	926
esc_ping_fail	alert[0x0]	97	1			T10	1		T11	4		T12	2
esc_ping_fail	alert[0x1]	64	1			T10	3		T11	3		T12	2
esc_ping_fail	alert[0x2]	67	1			T10	1		T11	2		T12	1
esc_ping_fail	alert[0x3]	56	1			T11	2		T12	1		T17	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	74357	1			T1	7		T12	10		T46	3
esc_integrity_fail	class_i[0x1]	38002	1			T1	2		T17	1		T23	325
esc_integrity_fail	class_i[0x2]	83734	1			T1	59		T3	48		T5	3383
esc_integrity_fail	class_i[0x3]	56443	1			T3	434		T17	1		T23	282
esc_ping_fail	class_i[0x0]	64	1			T238	9		T302	6		T310	4
esc_ping_fail	class_i[0x1]	74	1			T10	5		T11	9		T12	6
esc_ping_fail	class_i[0x2]	64	1			T11	1		T17	1		T233	1
esc_ping_fail	class_i[0x3]	82	1			T11	1		T17	9		T233	6