Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	653044715	0	0	621
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	653044715	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	653044715	652885229	0	0
tb.dut.CheckAccuCntDw	0	0	621	621	0	0
tb.dut.CheckEscCntDw	0	0	621	621	0	0
tb.dut.CheckNAlerts	0	0	621	621	0	0
tb.dut.CheckNClasses	0	0	621	621	0	0
tb.dut.CheckNEscSev	0	0	621	621	0	0
tb.dut.CrashdumpKnownO_A	0	0	653044715	652885229	0	0
tb.dut.EdnKnownO_A	0	0	653044715	652885229	0	0
tb.dut.EscPKnownO_A	0	0	653044715	652885229	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	653044715	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	653044715	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	653044715	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	653044715	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	653044715	70	0	0
tb.dut.IrqAKnownO_A	0	0	653044715	652885229	0	0
tb.dut.IrqBKnownO_A	0	0	653044715	652885229	0	0
tb.dut.IrqCKnownO_A	0	0	653044715	652885229	0	0
tb.dut.IrqDKnownO_A	0	0	653044715	652885229	0	0
tb.dut.TlAReadyKnownO_A	0	0	653044715	652885229	0	0
tb.dut.TlDValidKnownO_A	0	0	653044715	652885229	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	678728176	2991330	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	678728176	13682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	678728176	13524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	678728176	12577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	678728176	12571	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	678728176	12443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	678728176	12750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	678728176	15301	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	678728176	12382	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	678728176	12434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	678728176	12383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	678728176	12665	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	678728176	13601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	678728176	13791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	678728176	12754	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	678728176	12453	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	678728176	12357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	678728176	14750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	678728176	13375	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	678728176	13589	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	678728176	13683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	678728176	12443	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	678728176	13451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	678728176	12482	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	678728176	13493	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	678728176	12414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	678728176	12676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	678728176	13551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	678728176	12539	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	678728176	13661	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	678728176	13849	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	678728176	12185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	678728176	13535	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	678728176	13449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	678728176	12515	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	678728176	12401	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	678728176	12282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	678728176	13709	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	678728176	12402	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	678728176	13484	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	678728176	12667	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	678728176	12324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	678728176	12359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	678728176	13927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	678728176	13562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	678728176	13667	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	678728176	12609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	678728176	12291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	678728176	12454	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	678728176	12497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	678728176	13550	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	678728176	12392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	678728176	12734	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	678728176	12491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	678728176	14648	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	678728176	12575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	678728176	12619	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	678728176	12631	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	678728176	12559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	678728176	13525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	678728176	12639	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	678728176	13329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	678728176	13160	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	678728176	13498	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	678728176	12326	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	678728176	12372	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	678728176	12704	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	678728176	14887	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	678728176	12547	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	678728176	12632	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	678728176	23041	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	678728176	13861	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	678728176	13648	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	678728176	13964	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	678728176	13704	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	678728176	12324	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	678728176	13703	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	678728176	15334	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	678728176	12208	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	653044715	2201	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	653044715	231560	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	653044715	305985341	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	653044715	233	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	653044715	788	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	653044715	42	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	653044715	363	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	652870182	238636020	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	653044715	866	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	653044715	854	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	653044715	836	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	653044715	824	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	653044715	1483	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	653044715	149773	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	653044715	1383	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	653044715	58	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653044715	1243	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	653044715	1033	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	653044715	652885229	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	653044715	2387	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	653044715	166752	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	653044715	371902621	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	653044715	236	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	653044715	497	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	653044715	24	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	653044715	232	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	652870182	288998255	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	653044715	568	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	653044715	559	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	653044715	548	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	653044715	536	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	653044715	814	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	653044715	102794	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	653044715	726	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	653044715	63	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653044715	1267	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	653044715	1057	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	653044715	652885229	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	653044715	3669	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	653044715	212814	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	653044715	375198084	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	653044715	198	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	653044715	448	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	653044715	22	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	653044715	181	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	652870182	315058946	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	653044715	517	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	653044715	509	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	653044715	496	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	653044715	485	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	653044715	793	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	653044715	91857	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	653044715	717	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	653044715	52	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653044715	1190	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	653044715	980	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	653044715	652885229	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	653044715	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	653044715	4220	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	653044715	190706	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	653044715	389626688	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	653044715	237	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	653044715	490	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	653044715	21	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	653044715	211	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	652870182	301564795	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	653044715	548	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	653044715	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	653044715	524	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	653044715	512	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	653044715	601	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	653044715	73965	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	653044715	530	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	653044715	47	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	653044715	1243	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	653044715	1033	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	621	621	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	653044715	652885229	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	678728176	128556456	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	678728176	678079131	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	678728176	678079131	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	678728176	174015043	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	678728176	678079131	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	678728176	678079131	0	0
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