Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	58	1			T82	1		T37	1		T29	1
class_index[0x1]	63	1			T75	1		T77	1		T49	1
class_index[0x2]	52	1			T3	2		T4	1		T22	1
class_index[0x3]	47	1			T75	1		T82	1		T40	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	100	1			T77	1		T49	1		T82	1
intr_timeout_cnt[1]	36	1			T4	1		T82	2		T27	2
intr_timeout_cnt[2]	24	1			T3	2		T22	1		T37	1
intr_timeout_cnt[3]	12	1			T75	1		T29	1		T102	1
intr_timeout_cnt[4]	11	1			T37	1		T29	2		T57	3
intr_timeout_cnt[5]	12	1			T245	1		T115	2		T59	1
intr_timeout_cnt[6]	12	1			T29	1		T59	2		T246	3
intr_timeout_cnt[7]	6	1			T58	1		T59	1		T246	1
intr_timeout_cnt[8]	5	1			T75	1		T40	1		T247	3
intr_timeout_cnt[9]	2	1			T248	1		T249	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	30	1			T82	1		T25	1		T87	2
class_index[0x0]	intr_timeout_cnt[1]	8	1			T60	1		T227	1		T250	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T37	1		T88	1		T90	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T251	1		T252	1		T253	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T29	1		T254	1		T251	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T255	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T256	1		T257	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	4	1			T58	1		T246	1		T258	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T247	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T77	1		T49	1		T27	2
class_index[0x1]	intr_timeout_cnt[1]	9	1			T82	1		T58	1		T259	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T55	1		T104	1		T260	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T249	2		T258	1		T261	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T37	1		T29	1		T260	1
class_index[0x1]	intr_timeout_cnt[5]	4	1			T245	1		T262	2		T263	1
class_index[0x1]	intr_timeout_cnt[6]	4	1			T59	1		T246	3		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T59	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T75	1		T247	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T248	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	25	1			T36	1		T37	2		T25	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T4	1		T27	2		T114	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T3	2		T22	1		T55	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T29	1		T102	1		T264	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T115	2		T59	1		T255	1
class_index[0x2]	intr_timeout_cnt[6]	4	1			T59	1		T265	1		T258	1
class_index[0x2]	intr_timeout_cnt[7]	1	1			T266	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	18	1			T121	1		T123	1		T55	1
class_index[0x3]	intr_timeout_cnt[1]	12	1			T82	1		T25	2		T122	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T267	1		T248	2		T109	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T75	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	4	1			T57	3		T268	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	2	1			T267	1		T269	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T29	1		T229	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T40	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T249	1		-	-		-	-