Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	345088	1			T1	19		T2	99		T3	11
all_values[1]	345088	1			T1	19		T2	99		T3	11
all_values[2]	345088	1			T1	19		T2	99		T3	11
all_values[3]	345088	1			T1	19		T2	99		T3	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

687391

1

T1

47

T2

210

T3

24

auto[1]

692961

1

T1

29

T2

186

T3

20

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

824982

1

T1

14

T2

201

T3

8

auto[1]

555370

1

T1

62

T2

195

T3

36

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	99169	1			T1	3		T2	24		T3	2
all_values[0]	auto[0]	auto[1]	73049	1			T1	8		T2	24		T3	5
all_values[0]	auto[1]	auto[0]	100131	1			T1	4		T2	27		T4	352
all_values[0]	auto[1]	auto[1]	72739	1			T1	4		T2	24		T3	4
all_values[1]	auto[0]	auto[0]	102044	1			T1	1		T2	25		T7	1
all_values[1]	auto[0]	auto[1]	69328	1			T1	11		T2	25		T3	5
all_values[1]	auto[1]	auto[0]	103706	1			T1	1		T2	25		T3	1
all_values[1]	auto[1]	auto[1]	70010	1			T1	6		T2	24		T3	5
all_values[2]	auto[0]	auto[0]	105305	1			T1	1		T2	27		T3	2
all_values[2]	auto[0]	auto[1]	66441	1			T1	14		T2	27		T3	3
all_values[2]	auto[1]	auto[0]	107048	1			T2	23		T3	1		T7	1
all_values[2]	auto[1]	auto[1]	66294	1			T1	4		T2	22		T3	5
all_values[3]	auto[0]	auto[0]	103249	1			T2	29		T3	1		T4	352
all_values[3]	auto[0]	auto[1]	68806	1			T1	9		T2	29		T3	6
all_values[3]	auto[1]	auto[0]	104330	1			T1	4		T2	21		T3	1
all_values[3]	auto[1]	auto[1]	68703	1			T1	6		T2	20		T3	3