Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	266	1			T168	4		T169	7		T170	7
all_values[1]	266	1			T168	4		T169	7		T170	7
all_values[2]	266	1			T168	4		T169	7		T170	7
all_values[3]	266	1			T168	4		T169	7		T170	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609

1

T168

12

T169

20

T170

14

auto[1]

455

1

T168

4

T169

8

T170

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

457

1

T168

7

T169

7

T170

7

auto[1]

607

1

T168

9

T169

21

T170

21

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

645

1

T168

10

T169

12

T170

14

auto[1]

419

1

T168

6

T169

16

T170

14

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

70

1

T168

2

T169

2

T335

3

all_values[0]

auto[0]

auto[0]

auto[1]

22

1

T169

1

T170

2

T336

2

all_values[0]

auto[0]

auto[1]

auto[0]

39

1

T335

2

T337

1

T338

2

all_values[0]

auto[0]

auto[1]

auto[1]

17

1

T339

1

T340

1

T337

1

all_values[0]

auto[1]

auto[0]

auto[1]

79

1

T168

2

T169

3

T170

2

all_values[0]

auto[1]

auto[1]

auto[1]

39

1

T169

1

T170

3

T339

1

all_values[1]

auto[0]

auto[0]

auto[0]

59

1

T169

1

T170

3

T335

2

all_values[1]

auto[0]

auto[0]

auto[1]

32

1

T168

1

T169

2

T170

1

all_values[1]

auto[0]

auto[1]

auto[0]

52

1

T168

2

T335

1

T243

2

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T170

1

T335

1

T340

1

all_values[1]

auto[1]

auto[0]

auto[1]

56

1

T168

1

T169

4

T170

1

all_values[1]

auto[1]

auto[1]

auto[1]

45

1

T170

1

T335

2

T336

1

all_values[2]

auto[0]

auto[0]

auto[0]

67

1

T168

1

T169

2

T170

1

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T169

1

T335

1

T340

1

all_values[2]

auto[0]

auto[1]

auto[0]

43

1

T335

1

T336

1

T337

1

all_values[2]

auto[0]

auto[1]

auto[1]

24

1

T168

2

T170

2

T337

1

all_values[2]

auto[1]

auto[0]

auto[1]

61

1

T168

1

T169

4

T170

1

all_values[2]

auto[1]

auto[1]

auto[1]

46

1

T170

3

T335

3

T336

2

all_values[3]

auto[0]

auto[0]

auto[0]

73

1

T168

2

T170

2

T335

2

all_values[3]

auto[0]

auto[0]

auto[1]

20

1

T243

1

T340

1

T341

1

all_values[3]

auto[0]

auto[1]

auto[0]

54

1

T169

2

T170

1

T335

1

all_values[3]

auto[0]

auto[1]

auto[1]

26

1

T169

1

T170

1

T335

2

all_values[3]

auto[1]

auto[0]

auto[1]

45

1

T168

2

T170

1

T243

2

all_values[3]

auto[1]

auto[1]

auto[1]

48

1

T169

4

T170

2

T335

2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal