Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	92714	1			T5	240		T8	502		T26	1450
accum_cnt_1000	212504	1			T3	12		T18	76		T5	1019
accum_cnt_100	22345	1			T1	8		T18	54		T5	65
accum_cnt_50	60476	1			T1	56		T3	3		T4	1
accum_cnt_10	178704	1			T1	14		T2	147		T3	23
accum_cnt_0	407325	1			T1	30		T2	49		T3	30

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	254832	1			T1	27		T2	49		T3	17
class_index[0x1]	254832	1			T1	27		T2	49		T3	17
class_index[0x2]	254832	1			T1	27		T2	49		T3	17
class_index[0x3]	254832	1			T1	27		T2	49		T3	17

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	27897	1			T26	589		T28	234		T23	223
class_index[0x0]	accum_cnt_1000	58668	1			T18	40		T6	977		T26	502
class_index[0x0]	accum_cnt_100	6882	1			T18	27		T5	13		T6	140
class_index[0x0]	accum_cnt_50	14201	1			T1	22		T4	1		T18	22
class_index[0x0]	accum_cnt_10	42473	1			T1	3		T2	49		T3	4
class_index[0x0]	accum_cnt_0	91369	1			T1	2		T3	13		T18	1
class_index[0x1]	accum_cnt_2000	21787	1			T5	92		T44	94		T74	288
class_index[0x1]	accum_cnt_1000	51413	1			T5	860		T44	834		T64	46
class_index[0x1]	accum_cnt_100	5041	1			T5	49		T83	12		T23	8
class_index[0x1]	accum_cnt_50	15619	1			T1	22		T5	63		T12	6
class_index[0x1]	accum_cnt_10	52725	1			T1	5		T2	49		T3	2
class_index[0x1]	accum_cnt_0	99152	1			T3	15		T7	4		T4	2
class_index[0x2]	accum_cnt_2000	20481	1			T26	254		T24	85		T66	527
class_index[0x2]	accum_cnt_1000	51837	1			T18	36		T26	245		T23	609
class_index[0x2]	accum_cnt_100	5501	1			T1	8		T18	27		T26	15
class_index[0x2]	accum_cnt_50	13623	1			T1	12		T3	3		T18	23
class_index[0x2]	accum_cnt_10	43545	1			T1	6		T2	49		T3	14
class_index[0x2]	accum_cnt_0	107094	1			T1	1		T7	1		T4	4
class_index[0x3]	accum_cnt_2000	22549	1			T5	148		T8	502		T26	607
class_index[0x3]	accum_cnt_1000	50586	1			T3	12		T5	159		T8	445
class_index[0x3]	accum_cnt_100	4921	1			T5	3		T8	26		T26	28
class_index[0x3]	accum_cnt_50	17033	1			T5	36		T8	24		T79	6
class_index[0x3]	accum_cnt_10	39961	1			T3	3		T7	4		T4	1041
class_index[0x3]	accum_cnt_0	109710	1			T1	27		T2	49		T3	2