Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2740	1			T24	47		T238	1		T82	266
alert[0x1]	6101	1			T17	1		T46	6		T24	36
alert[0x2]	5417	1			T10	1		T12	2		T28	399
alert[0x3]	6969	1			T5	19		T10	1		T77	5
alert[0x4]	4389	1			T10	2		T23	3		T49	3
alert[0x5]	4964	1			T4	11		T5	20		T23	3
alert[0x6]	3323	1			T5	461		T10	2		T23	9
alert[0x7]	4290	1			T5	17		T11	1		T12	1
alert[0x8]	5076	1			T4	11		T12	1		T28	54
alert[0x9]	2570	1			T4	34		T5	30		T17	1
alert[0xa]	5953	1			T4	525		T5	58		T6	1
alert[0xb]	6035	1			T5	54		T69	18		T77	10
alert[0xc]	3008	1			T4	108		T5	105		T11	1
alert[0xd]	7193	1			T5	10		T11	1		T23	3
alert[0xe]	6577	1			T17	2		T46	8		T69	58
alert[0xf]	11755	1			T4	48		T5	67		T11	1
alert[0x10]	5046	1			T5	13		T17	2		T28	11
alert[0x11]	13697	1			T4	375		T5	7		T10	1
alert[0x12]	5614	1			T10	1		T11	1		T23	2
alert[0x13]	11871	1			T5	300		T12	1		T28	32
alert[0x14]	10730	1			T4	3286		T6	1		T10	1
alert[0x15]	6152	1			T4	86		T5	33		T23	4
alert[0x16]	2782	1			T4	237		T5	15		T28	27
alert[0x17]	5613	1			T12	1		T28	33		T69	17
alert[0x18]	4746	1			T4	2		T17	1		T24	63
alert[0x19]	6909	1			T91	1		T77	2		T78	698
alert[0x1a]	3808	1			T5	30		T10	1		T46	30
alert[0x1b]	7579	1			T44	1		T24	46		T40	2
alert[0x1c]	4588	1			T4	9		T10	1		T17	1
alert[0x1d]	8488	1			T4	39		T10	1		T23	2
alert[0x1e]	16631	1			T4	1043		T5	262		T24	9178
alert[0x1f]	12533	1			T4	92		T77	19		T82	143
alert[0x20]	3665	1			T44	1		T49	3		T78	10
alert[0x21]	3639	1			T4	1101		T11	1		T17	1
alert[0x22]	11042	1			T44	1		T46	1		T49	1
alert[0x23]	2412	1			T5	30		T17	1		T28	170
alert[0x24]	2855	1			T11	1		T24	22		T69	2
alert[0x25]	7232	1			T1	2		T5	98		T10	1
alert[0x26]	3470	1			T4	9		T5	309		T12	1
alert[0x27]	6194	1			T5	178		T11	1		T17	1
alert[0x28]	8067	1			T4	4889		T11	1		T46	3
alert[0x29]	16418	1			T5	360		T28	31		T24	225
alert[0x2a]	10109	1			T4	151		T5	516		T17	1
alert[0x2b]	6467	1			T4	17		T5	41		T12	2
alert[0x2c]	9699	1			T4	3		T5	2119		T23	1
alert[0x2d]	4416	1			T4	105		T11	1		T24	265
alert[0x2e]	3216	1			T10	1		T24	75		T77	6
alert[0x2f]	3860	1			T4	12		T11	2		T28	2067
alert[0x30]	8931	1			T10	2		T11	1		T28	157
alert[0x31]	6084	1			T4	5		T5	6		T17	1
alert[0x32]	5124	1			T12	1		T27	70		T36	11
alert[0x33]	2049	1			T4	42		T5	144		T17	1
alert[0x34]	7822	1			T24	18		T69	30		T91	53
alert[0x35]	3007	1			T1	1		T4	127		T5	33
alert[0x36]	5888	1			T4	17		T24	1460		T91	2
alert[0x37]	5494	1			T4	42		T5	317		T11	1
alert[0x38]	3698	1			T5	45		T17	1		T78	16
alert[0x39]	5492	1			T12	1		T69	174		T78	120
alert[0x3a]	10884	1			T4	1371		T5	18		T10	2
alert[0x3b]	3195	1			T5	57		T24	73		T69	3
alert[0x3c]	11507	1			T24	312		T82	9		T27	35
alert[0x3d]	7018	1			T91	2		T78	16		T82	312
alert[0x3e]	8231	1			T17	1		T28	81		T27	86
alert[0x3f]	4388	1			T5	1135		T17	1		T23	33
alert[0x40]	3560	1			T69	1		T49	6		T82	32

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	78423	1			T4	13612		T5	1		T6	2
class_i[0x1]	58493	1			T1	1		T5	8		T12	10
class_i[0x2]	172779	1			T1	2		T4	90		T5	4
class_i[0x3]	108585	1			T4	95		T5	6894		T10	19

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

417614

1

T1

3

T4

13797

T5

6907

alert_ping_fail

666

1

T6

2

T10

19

T11

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2726	1			T24	47		T82	266		T27	329
alert_integrity_fail	alert[0x1]	6094	1			T46	6		T24	36		T69	17
alert_integrity_fail	alert[0x2]	5405	1			T28	399		T24	473		T77	2
alert_integrity_fail	alert[0x3]	6961	1			T5	19		T77	5		T78	338
alert_integrity_fail	alert[0x4]	4379	1			T23	3		T49	3		T78	85
alert_integrity_fail	alert[0x5]	4953	1			T4	11		T5	20		T23	3
alert_integrity_fail	alert[0x6]	3311	1			T5	461		T23	9		T24	54
alert_integrity_fail	alert[0x7]	4276	1			T5	17		T24	354		T77	2
alert_integrity_fail	alert[0x8]	5059	1			T4	11		T28	54		T24	163
alert_integrity_fail	alert[0x9]	2560	1			T4	34		T5	30		T91	4
alert_integrity_fail	alert[0xa]	5938	1			T4	525		T5	58		T23	13
alert_integrity_fail	alert[0xb]	6024	1			T5	54		T69	18		T77	10
alert_integrity_fail	alert[0xc]	3001	1			T4	108		T5	105		T24	32
alert_integrity_fail	alert[0xd]	7190	1			T5	10		T23	3		T46	1
alert_integrity_fail	alert[0xe]	6570	1			T46	8		T69	58		T78	58
alert_integrity_fail	alert[0xf]	11741	1			T4	48		T5	67		T28	6
alert_integrity_fail	alert[0x10]	5036	1			T5	13		T28	11		T24	41
alert_integrity_fail	alert[0x11]	13690	1			T4	375		T5	7		T23	5
alert_integrity_fail	alert[0x12]	5608	1			T23	2		T77	27		T82	497
alert_integrity_fail	alert[0x13]	11862	1			T5	300		T28	32		T24	7
alert_integrity_fail	alert[0x14]	10717	1			T4	3286		T77	1		T78	7
alert_integrity_fail	alert[0x15]	6141	1			T4	86		T5	33		T23	4
alert_integrity_fail	alert[0x16]	2773	1			T4	237		T5	15		T28	27
alert_integrity_fail	alert[0x17]	5609	1			T28	33		T69	17		T77	2
alert_integrity_fail	alert[0x18]	4733	1			T4	2		T24	63		T27	87
alert_integrity_fail	alert[0x19]	6901	1			T91	1		T77	2		T78	698
alert_integrity_fail	alert[0x1a]	3802	1			T5	30		T46	30		T69	1
alert_integrity_fail	alert[0x1b]	7572	1			T24	46		T40	2		T29	22
alert_integrity_fail	alert[0x1c]	4573	1			T4	9		T23	165		T24	95
alert_integrity_fail	alert[0x1d]	8477	1			T4	39		T23	2		T77	10
alert_integrity_fail	alert[0x1e]	16617	1			T4	1043		T5	262		T24	9178
alert_integrity_fail	alert[0x1f]	12521	1			T4	92		T77	19		T82	143
alert_integrity_fail	alert[0x20]	3653	1			T49	3		T78	10		T27	521
alert_integrity_fail	alert[0x21]	3627	1			T4	1101		T24	112		T69	1
alert_integrity_fail	alert[0x22]	11025	1			T46	1		T49	1		T78	87
alert_integrity_fail	alert[0x23]	2395	1			T5	30		T28	170		T23	1
alert_integrity_fail	alert[0x24]	2846	1			T24	22		T69	2		T49	1
alert_integrity_fail	alert[0x25]	7225	1			T1	2		T5	98		T24	656
alert_integrity_fail	alert[0x26]	3462	1			T4	9		T5	309		T69	54
alert_integrity_fail	alert[0x27]	6184	1			T5	178		T78	22		T82	44
alert_integrity_fail	alert[0x28]	8057	1			T4	4889		T46	3		T24	317
alert_integrity_fail	alert[0x29]	16412	1			T5	360		T28	31		T24	225
alert_integrity_fail	alert[0x2a]	10095	1			T4	151		T5	516		T28	50
alert_integrity_fail	alert[0x2b]	6450	1			T4	17		T5	41		T28	31
alert_integrity_fail	alert[0x2c]	9688	1			T4	3		T5	2119		T23	1
alert_integrity_fail	alert[0x2d]	4408	1			T4	105		T24	265		T77	8
alert_integrity_fail	alert[0x2e]	3207	1			T24	75		T77	6		T78	5
alert_integrity_fail	alert[0x2f]	3849	1			T4	12		T28	2067		T24	34
alert_integrity_fail	alert[0x30]	8914	1			T28	157		T23	3		T49	3
alert_integrity_fail	alert[0x31]	6075	1			T4	5		T5	6		T28	128
alert_integrity_fail	alert[0x32]	5115	1			T27	70		T36	11		T37	3
alert_integrity_fail	alert[0x33]	2037	1			T4	42		T5	144		T77	2
alert_integrity_fail	alert[0x34]	7812	1			T24	18		T69	30		T91	53
alert_integrity_fail	alert[0x35]	2997	1			T1	1		T4	127		T5	33
alert_integrity_fail	alert[0x36]	5881	1			T4	17		T24	1460		T91	2
alert_integrity_fail	alert[0x37]	5487	1			T4	42		T5	317		T28	17
alert_integrity_fail	alert[0x38]	3688	1			T5	45		T78	16		T82	4
alert_integrity_fail	alert[0x39]	5480	1			T69	174		T78	120		T29	48
alert_integrity_fail	alert[0x3a]	10876	1			T4	1371		T5	18		T24	90
alert_integrity_fail	alert[0x3b]	3184	1			T5	57		T24	73		T69	3
alert_integrity_fail	alert[0x3c]	11496	1			T24	312		T82	9		T27	35
alert_integrity_fail	alert[0x3d]	7008	1			T91	2		T78	16		T82	312
alert_integrity_fail	alert[0x3e]	8220	1			T28	81		T27	86		T51	5
alert_integrity_fail	alert[0x3f]	4385	1			T5	1135		T23	33		T24	126
alert_integrity_fail	alert[0x40]	3556	1			T69	1		T49	6		T82	32
alert_ping_fail	alert[0x0]	14	1			T238	1		T296	2		T297	1
alert_ping_fail	alert[0x1]	7	1			T17	1		T298	1		T299	1
alert_ping_fail	alert[0x2]	12	1			T10	1		T12	2		T222	1
alert_ping_fail	alert[0x3]	8	1			T10	1		T300	1		T301	1
alert_ping_fail	alert[0x4]	10	1			T10	2		T222	1		T302	2
alert_ping_fail	alert[0x5]	11	1			T294	1		T303	1		T300	1
alert_ping_fail	alert[0x6]	12	1			T10	2		T233	1		T304	1
alert_ping_fail	alert[0x7]	14	1			T11	1		T12	1		T285	2
alert_ping_fail	alert[0x8]	17	1			T12	1		T222	1		T277	1
alert_ping_fail	alert[0x9]	10	1			T17	1		T238	2		T222	1
alert_ping_fail	alert[0xa]	15	1			T6	1		T10	1		T233	1
alert_ping_fail	alert[0xb]	11	1			T233	1		T305	1		T306	1
alert_ping_fail	alert[0xc]	7	1			T11	1		T17	1		T307	1
alert_ping_fail	alert[0xd]	3	1			T11	1		T298	1		T308	1
alert_ping_fail	alert[0xe]	7	1			T17	2		T299	1		T309	1
alert_ping_fail	alert[0xf]	14	1			T11	1		T238	1		T233	1
alert_ping_fail	alert[0x10]	10	1			T17	2		T303	1		T304	1
alert_ping_fail	alert[0x11]	7	1			T10	1		T222	1		T303	1
alert_ping_fail	alert[0x12]	6	1			T10	1		T11	1		T302	1
alert_ping_fail	alert[0x13]	9	1			T12	1		T44	2		T222	1
alert_ping_fail	alert[0x14]	13	1			T6	1		T10	1		T233	2
alert_ping_fail	alert[0x15]	11	1			T44	2		T233	1		T310	2
alert_ping_fail	alert[0x16]	9	1			T222	1		T300	1		T311	1
alert_ping_fail	alert[0x17]	4	1			T12	1		T222	1		T309	1
alert_ping_fail	alert[0x18]	13	1			T17	1		T233	1		T302	1
alert_ping_fail	alert[0x19]	8	1			T233	1		T298	2		T296	1
alert_ping_fail	alert[0x1a]	6	1			T10	1		T310	1		T309	1
alert_ping_fail	alert[0x1b]	7	1			T44	1		T312	2		T307	1
alert_ping_fail	alert[0x1c]	15	1			T10	1		T17	1		T222	1
alert_ping_fail	alert[0x1d]	11	1			T10	1		T238	1		T299	2
alert_ping_fail	alert[0x1e]	14	1			T298	3		T296	2		T305	1
alert_ping_fail	alert[0x1f]	12	1			T298	1		T312	1		T307	1
alert_ping_fail	alert[0x20]	12	1			T44	1		T238	1		T312	1
alert_ping_fail	alert[0x21]	12	1			T11	1		T17	1		T238	1
alert_ping_fail	alert[0x22]	17	1			T44	1		T238	1		T222	1
alert_ping_fail	alert[0x23]	17	1			T17	1		T238	2		T310	1
alert_ping_fail	alert[0x24]	9	1			T11	1		T238	1		T222	2
alert_ping_fail	alert[0x25]	7	1			T10	1		T309	1		T313	1
alert_ping_fail	alert[0x26]	8	1			T12	1		T310	1		T314	1
alert_ping_fail	alert[0x27]	10	1			T11	1		T17	1		T233	1
alert_ping_fail	alert[0x28]	10	1			T11	1		T233	1		T307	1
alert_ping_fail	alert[0x29]	6	1			T238	1		T314	1		T315	1
alert_ping_fail	alert[0x2a]	14	1			T17	1		T222	1		T305	1
alert_ping_fail	alert[0x2b]	17	1			T12	2		T298	1		T296	1
alert_ping_fail	alert[0x2c]	11	1			T233	1		T312	3		T285	1
alert_ping_fail	alert[0x2d]	8	1			T11	1		T298	1		T316	1
alert_ping_fail	alert[0x2e]	9	1			T10	1		T303	1		T312	1
alert_ping_fail	alert[0x2f]	11	1			T11	2		T238	1		T233	1
alert_ping_fail	alert[0x30]	17	1			T10	2		T11	1		T238	1
alert_ping_fail	alert[0x31]	9	1			T17	1		T307	1		T300	1
alert_ping_fail	alert[0x32]	9	1			T12	1		T302	1		T297	1
alert_ping_fail	alert[0x33]	12	1			T17	1		T238	3		T222	1
alert_ping_fail	alert[0x34]	10	1			T233	2		T317	1		T301	1
alert_ping_fail	alert[0x35]	10	1			T12	1		T233	1		T298	1
alert_ping_fail	alert[0x36]	7	1			T298	1		T306	1		T318	1
alert_ping_fail	alert[0x37]	7	1			T11	1		T306	1		T318	1
alert_ping_fail	alert[0x38]	10	1			T17	1		T222	1		T296	1
alert_ping_fail	alert[0x39]	12	1			T12	1		T233	1		T305	1
alert_ping_fail	alert[0x3a]	8	1			T10	2		T306	1		T300	1
alert_ping_fail	alert[0x3b]	11	1			T298	1		T296	1		T299	1
alert_ping_fail	alert[0x3c]	11	1			T222	2		T298	1		T296	2
alert_ping_fail	alert[0x3d]	10	1			T296	1		T305	1		T306	1
alert_ping_fail	alert[0x3e]	11	1			T17	1		T298	1		T302	1
alert_ping_fail	alert[0x3f]	3	1			T17	1		T299	1		T297	1
alert_ping_fail	alert[0x40]	4	1			T305	1		T314	1		T319	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	78265	1			T4	13612		T5	1		T28	3294
alert_integrity_fail	class_i[0x1]	58314	1			T1	1		T5	8		T23	159
alert_integrity_fail	class_i[0x2]	172590	1			T1	2		T4	90		T5	4
alert_integrity_fail	class_i[0x3]	108445	1			T4	95		T5	6894		T23	3
alert_ping_fail	class_i[0x0]	158	1			T6	2		T17	4		T233	17
alert_ping_fail	class_i[0x1]	179	1			T12	10		T17	2		T44	7
alert_ping_fail	class_i[0x2]	189	1			T11	12		T12	1		T17	10
alert_ping_fail	class_i[0x3]	140	1			T10	19		T11	2		T12	1