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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.64 99.99 98.66 100.00 100.00 100.00 99.38 99.48


Total test records in report: 826
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T770 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.595081529 Mar 03 12:34:46 PM PST 24 Mar 03 12:34:55 PM PST 24 334027507 ps
T771 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3083509380 Mar 03 12:34:59 PM PST 24 Mar 03 12:35:44 PM PST 24 1352087553 ps
T772 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2666086993 Mar 03 12:35:29 PM PST 24 Mar 03 12:35:41 PM PST 24 174504376 ps
T773 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1618049677 Mar 03 12:35:07 PM PST 24 Mar 03 12:35:18 PM PST 24 8090927 ps
T774 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1318197490 Mar 03 12:34:56 PM PST 24 Mar 03 12:35:10 PM PST 24 1752179925 ps
T775 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3308424669 Mar 03 12:35:06 PM PST 24 Mar 03 12:35:10 PM PST 24 88790899 ps
T776 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1382783571 Mar 03 12:35:01 PM PST 24 Mar 03 12:35:06 PM PST 24 485042400 ps
T777 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3749376076 Mar 03 12:35:13 PM PST 24 Mar 03 12:35:15 PM PST 24 9085119 ps
T778 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4033887601 Mar 03 12:35:13 PM PST 24 Mar 03 12:35:15 PM PST 24 10438531 ps
T779 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.967978403 Mar 03 12:34:49 PM PST 24 Mar 03 12:35:08 PM PST 24 1014591978 ps
T780 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3514582596 Mar 03 12:34:57 PM PST 24 Mar 03 12:35:02 PM PST 24 15920833 ps
T781 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2426402563 Mar 03 12:35:09 PM PST 24 Mar 03 12:35:20 PM PST 24 156626410 ps
T782 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3120085591 Mar 03 12:34:51 PM PST 24 Mar 03 12:34:55 PM PST 24 118626420 ps
T783 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4051337925 Mar 03 12:34:51 PM PST 24 Mar 03 12:39:04 PM PST 24 3448714221 ps
T157 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1830024944 Mar 03 12:35:05 PM PST 24 Mar 03 12:50:08 PM PST 24 50271410876 ps
T784 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2964276464 Mar 03 12:35:01 PM PST 24 Mar 03 12:35:03 PM PST 24 9819635 ps
T152 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2094861732 Mar 03 12:34:45 PM PST 24 Mar 03 12:37:46 PM PST 24 3748640524 ps
T785 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1629824438 Mar 03 12:34:46 PM PST 24 Mar 03 12:34:57 PM PST 24 502044614 ps
T786 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.935349560 Mar 03 12:34:52 PM PST 24 Mar 03 12:34:59 PM PST 24 283277503 ps
T787 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4281849399 Mar 03 12:35:12 PM PST 24 Mar 03 12:35:18 PM PST 24 69689475 ps
T788 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3700900060 Mar 03 12:35:01 PM PST 24 Mar 03 12:35:02 PM PST 24 6199880 ps
T153 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.84769685 Mar 03 12:35:04 PM PST 24 Mar 03 12:38:17 PM PST 24 3504775220 ps
T146 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2471610437 Mar 03 12:35:05 PM PST 24 Mar 03 12:40:12 PM PST 24 25339582151 ps
T144 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.775538473 Mar 03 12:35:05 PM PST 24 Mar 03 12:40:02 PM PST 24 4383674485 ps
T789 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1108251522 Mar 03 12:35:18 PM PST 24 Mar 03 12:35:20 PM PST 24 9561819 ps
T790 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1468521717 Mar 03 12:35:22 PM PST 24 Mar 03 12:35:23 PM PST 24 14921413 ps
T791 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.901528931 Mar 03 12:34:57 PM PST 24 Mar 03 12:35:31 PM PST 24 903513824 ps
T162 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4004145617 Mar 03 12:34:57 PM PST 24 Mar 03 12:52:37 PM PST 24 14419982177 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3934609672 Mar 03 12:35:13 PM PST 24 Mar 03 12:36:54 PM PST 24 1819201856 ps
T793 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2018667949 Mar 03 12:34:58 PM PST 24 Mar 03 12:40:35 PM PST 24 11652089079 ps
T794 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2104422768 Mar 03 12:35:28 PM PST 24 Mar 03 12:35:30 PM PST 24 15788589 ps
T795 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3978873128 Mar 03 12:34:55 PM PST 24 Mar 03 12:35:07 PM PST 24 84667044 ps
T796 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1040243385 Mar 03 12:34:50 PM PST 24 Mar 03 12:34:56 PM PST 24 73785514 ps
T186 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2139259241 Mar 03 12:34:46 PM PST 24 Mar 03 12:34:53 PM PST 24 114668123 ps
T797 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.987787849 Mar 03 12:34:56 PM PST 24 Mar 03 12:35:01 PM PST 24 17328844 ps
T798 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1847584590 Mar 03 12:35:02 PM PST 24 Mar 03 12:35:07 PM PST 24 120479552 ps
T171 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3024163498 Mar 03 12:35:03 PM PST 24 Mar 03 12:35:08 PM PST 24 106545567 ps
T799 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3888641877 Mar 03 12:34:56 PM PST 24 Mar 03 12:35:08 PM PST 24 828555976 ps
T800 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4282133426 Mar 03 12:35:15 PM PST 24 Mar 03 12:35:18 PM PST 24 9619000 ps
T174 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.336642222 Mar 03 12:34:53 PM PST 24 Mar 03 12:36:14 PM PST 24 1319465563 ps
T158 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1150080605 Mar 03 12:34:56 PM PST 24 Mar 03 12:40:37 PM PST 24 16152726951 ps
T344 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2855569917 Mar 03 12:34:48 PM PST 24 Mar 03 12:45:19 PM PST 24 18381065904 ps
T150 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3151398717 Mar 03 12:35:07 PM PST 24 Mar 03 12:37:30 PM PST 24 4392236666 ps
T801 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1138061514 Mar 03 12:34:58 PM PST 24 Mar 03 12:35:02 PM PST 24 9872278 ps
T802 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2695081619 Mar 03 12:34:45 PM PST 24 Mar 03 12:34:46 PM PST 24 29734749 ps
T803 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3210935490 Mar 03 12:35:07 PM PST 24 Mar 03 12:35:08 PM PST 24 20226955 ps
T804 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2884543443 Mar 03 12:35:05 PM PST 24 Mar 03 12:35:06 PM PST 24 10822440 ps
T805 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2980214660 Mar 03 12:34:47 PM PST 24 Mar 03 12:34:49 PM PST 24 6871715 ps
T806 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1002274859 Mar 03 12:34:57 PM PST 24 Mar 03 12:35:04 PM PST 24 88273334 ps
T807 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1102247481 Mar 03 12:34:56 PM PST 24 Mar 03 12:35:01 PM PST 24 60559040 ps
T139 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1777284652 Mar 03 12:34:49 PM PST 24 Mar 03 12:38:37 PM PST 24 2058202520 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1802574741 Mar 03 12:34:56 PM PST 24 Mar 03 12:35:04 PM PST 24 29486892 ps
T164 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3641932655 Mar 03 12:35:02 PM PST 24 Mar 03 12:52:04 PM PST 24 24968323966 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.288511756 Mar 03 12:35:14 PM PST 24 Mar 03 12:35:18 PM PST 24 26423904 ps
T163 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.640453325 Mar 03 12:34:49 PM PST 24 Mar 03 12:39:27 PM PST 24 3732288670 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.928320654 Mar 03 12:34:50 PM PST 24 Mar 03 12:34:57 PM PST 24 45533302 ps
T159 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2348364454 Mar 03 12:34:47 PM PST 24 Mar 03 12:37:16 PM PST 24 2088959986 ps
T811 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1546357417 Mar 03 12:35:00 PM PST 24 Mar 03 12:35:02 PM PST 24 6501135 ps
T812 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3871763121 Mar 03 12:35:03 PM PST 24 Mar 03 12:35:09 PM PST 24 100827725 ps
T813 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2673791199 Mar 03 12:34:57 PM PST 24 Mar 03 12:35:02 PM PST 24 23760246 ps
T814 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.103572700 Mar 03 12:34:58 PM PST 24 Mar 03 12:35:34 PM PST 24 480545291 ps
T815 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1268024685 Mar 03 12:34:57 PM PST 24 Mar 03 12:35:09 PM PST 24 966773213 ps
T816 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.921518318 Mar 03 12:35:04 PM PST 24 Mar 03 12:35:05 PM PST 24 53909219 ps
T176 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2374325383 Mar 03 12:35:05 PM PST 24 Mar 03 12:35:42 PM PST 24 522949788 ps
T817 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2739614770 Mar 03 12:35:25 PM PST 24 Mar 03 12:38:26 PM PST 24 2715650158 ps
T818 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2158449091 Mar 03 12:34:54 PM PST 24 Mar 03 12:35:04 PM PST 24 181037875 ps
T161 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4044643170 Mar 03 12:35:06 PM PST 24 Mar 03 12:46:24 PM PST 24 6216325177 ps
T819 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2229151268 Mar 03 12:35:19 PM PST 24 Mar 03 12:35:23 PM PST 24 36092251 ps
T820 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2130712483 Mar 03 12:35:03 PM PST 24 Mar 03 12:35:25 PM PST 24 1368965098 ps
T821 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.720944547 Mar 03 12:35:00 PM PST 24 Mar 03 12:35:12 PM PST 24 723283671 ps
T822 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.270299739 Mar 03 12:34:54 PM PST 24 Mar 03 12:35:04 PM PST 24 552895359 ps
T160 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3251697827 Mar 03 12:34:58 PM PST 24 Mar 03 12:43:21 PM PST 24 20711455940 ps
T823 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2108335433 Mar 03 12:35:07 PM PST 24 Mar 03 12:35:09 PM PST 24 9464316 ps
T824 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1762144298 Mar 03 12:35:04 PM PST 24 Mar 03 12:35:06 PM PST 24 7335893 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.121602334 Mar 03 12:35:17 PM PST 24 Mar 03 12:35:36 PM PST 24 580718558 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2002914385 Mar 03 12:35:05 PM PST 24 Mar 03 12:35:26 PM PST 24 300170450 ps

Test location /workspace/coverage/default/35.alert_handler_stress_all.2558298464
Short name T5
Test name
Test status
Simulation time 670283097810 ps
CPU time 2476.73 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 01:23:18 PM PST 24
Peak memory 288888 kb
Host smart-d4fdd978-ff43-427d-ad54-d4cacf52e3c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558298464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2558298464
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1063294151
Short name T23
Test name
Test status
Simulation time 80224049122 ps
CPU time 2234.39 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 01:19:05 PM PST 24
Peak memory 281612 kb
Host smart-672aada0-fe0c-4b46-86bd-3ce05511247a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063294151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1063294151
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.3578229602
Short name T82
Test name
Test status
Simulation time 285735315508 ps
CPU time 8844.57 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 03:09:25 PM PST 24
Peak memory 322648 kb
Host smart-d43f4e11-d88d-4eec-9f53-c68b291d89fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578229602 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.3578229602
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4260055560
Short name T13
Test name
Test status
Simulation time 353477159 ps
CPU time 12.87 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:33 PM PST 24
Peak memory 264320 kb
Host smart-00b5d8a8-f3c5-4952-9ef4-cbeadb5aa87c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4260055560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4260055560
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1221236977
Short name T166
Test name
Test status
Simulation time 464192916 ps
CPU time 32.49 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:40 PM PST 24
Peak memory 244492 kb
Host smart-d560180c-08eb-4a23-a56f-82671f76e5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1221236977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1221236977
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3294996032
Short name T6
Test name
Test status
Simulation time 41428894026 ps
CPU time 2320.07 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 01:20:31 PM PST 24
Peak memory 286708 kb
Host smart-8b67acc2-1b23-477b-a915-0107d12ca5c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294996032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3294996032
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1968120292
Short name T58
Test name
Test status
Simulation time 12934783918 ps
CPU time 1291.77 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:02:47 PM PST 24
Peak memory 289828 kb
Host smart-c8874b9b-20ff-4618-8e44-deed8e12a58c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968120292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1968120292
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.372688165
Short name T133
Test name
Test status
Simulation time 18632382986 ps
CPU time 293.93 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:39:54 PM PST 24
Peak memory 271784 kb
Host smart-81c2312d-f934-4912-91ac-b2f598f02260
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=372688165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.372688165
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.4038966924
Short name T51
Test name
Test status
Simulation time 48309196756 ps
CPU time 1728.77 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 01:10:01 PM PST 24
Peak memory 289584 kb
Host smart-a4517bfc-040c-4c48-ad07-39e12ed38585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038966924 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.4038966924
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1830024944
Short name T157
Test name
Test status
Simulation time 50271410876 ps
CPU time 900.68 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:50:08 PM PST 24
Peak memory 264932 kb
Host smart-77118e90-6c12-45e5-9edf-17aa456f7da8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830024944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1830024944
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3196118469
Short name T28
Test name
Test status
Simulation time 161238673511 ps
CPU time 3143.96 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 01:33:41 PM PST 24
Peak memory 301716 kb
Host smart-7279e847-c060-421e-81a7-4a0b79e1a33a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196118469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3196118469
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.766556836
Short name T141
Test name
Test status
Simulation time 8024706634 ps
CPU time 644.81 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:45:45 PM PST 24
Peak memory 271980 kb
Host smart-b32e97ac-9c05-44fc-acb8-3d896c5f0c64
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766556836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.766556836
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4058378380
Short name T106
Test name
Test status
Simulation time 34951391337 ps
CPU time 807.05 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:54:51 PM PST 24
Peak memory 272964 kb
Host smart-0729ba43-428b-406b-879f-0646c72e558f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058378380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4058378380
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3934668663
Short name T44
Test name
Test status
Simulation time 151413793327 ps
CPU time 2505.12 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 01:23:30 PM PST 24
Peak memory 273388 kb
Host smart-5664994b-9dd8-4422-ba59-be21e387f760
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934668663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3934668663
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.4109926089
Short name T136
Test name
Test status
Simulation time 69029060306 ps
CPU time 1240.98 seconds
Started Mar 03 12:34:52 PM PST 24
Finished Mar 03 12:55:34 PM PST 24
Peak memory 264924 kb
Host smart-938e3d0e-74d7-4f88-84b7-700aaa1f506a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109926089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.4109926089
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3780368233
Short name T17
Test name
Test status
Simulation time 29728267635 ps
CPU time 601.89 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 12:52:27 PM PST 24
Peak memory 248828 kb
Host smart-ad985967-7cf6-4d93-a87d-5a3213926d1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780368233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3780368233
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3151670659
Short name T335
Test name
Test status
Simulation time 11935709 ps
CPU time 1.57 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 235272 kb
Host smart-1161b2e5-967f-4736-a0d2-8b5c317cded3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3151670659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3151670659
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1317522172
Short name T295
Test name
Test status
Simulation time 58994153821 ps
CPU time 3400.92 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 01:38:23 PM PST 24
Peak memory 288888 kb
Host smart-08979383-3e72-460c-a54c-5ae0beaec9c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317522172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1317522172
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.4055918254
Short name T46
Test name
Test status
Simulation time 51026894170 ps
CPU time 2888.86 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 01:29:28 PM PST 24
Peak memory 289580 kb
Host smart-a825ce99-2523-4682-8ac9-230e6b1b91bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055918254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.4055918254
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.4021244232
Short name T135
Test name
Test status
Simulation time 50921333536 ps
CPU time 1120.69 seconds
Started Mar 03 12:34:52 PM PST 24
Finished Mar 03 12:53:33 PM PST 24
Peak memory 265008 kb
Host smart-66cabea9-aa9b-4687-a1eb-f0caa6482ebe
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021244232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.4021244232
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.954461966
Short name T29
Test name
Test status
Simulation time 116586606389 ps
CPU time 2443.56 seconds
Started Mar 03 12:41:40 PM PST 24
Finished Mar 03 01:22:24 PM PST 24
Peak memory 305860 kb
Host smart-d8201525-ef92-4dcb-a4e0-738aeca9ae32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954461966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_han
dler_stress_all.954461966
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.59009074
Short name T147
Test name
Test status
Simulation time 5538126936 ps
CPU time 343.53 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:40:43 PM PST 24
Peak memory 265008 kb
Host smart-f39bec91-a075-407c-8da0-4656c80ef2d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=59009074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors
.59009074
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3075854173
Short name T316
Test name
Test status
Simulation time 45512530756 ps
CPU time 2372.47 seconds
Started Mar 03 12:42:59 PM PST 24
Finished Mar 03 01:22:32 PM PST 24
Peak memory 285104 kb
Host smart-0f9f849d-31fa-4e28-9515-4ba4fc542aa6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075854173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3075854173
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.118767280
Short name T10
Test name
Test status
Simulation time 10617928575 ps
CPU time 440.89 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:48:36 PM PST 24
Peak memory 246740 kb
Host smart-ff7c3587-e450-4129-8a66-7dbc424bd447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118767280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.118767280
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1966297461
Short name T127
Test name
Test status
Simulation time 6179009975 ps
CPU time 455.1 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:42:40 PM PST 24
Peak memory 265092 kb
Host smart-ec82685d-dc04-4484-9b8c-aa8cc61e21eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966297461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1966297461
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3583013655
Short name T551
Test name
Test status
Simulation time 118278871939 ps
CPU time 3503.47 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 01:40:03 PM PST 24
Peak memory 289472 kb
Host smart-a44600d7-2940-4063-9628-e949b7a5e8ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583013655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3583013655
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.601531681
Short name T308
Test name
Test status
Simulation time 25938588379 ps
CPU time 549.41 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:50:29 PM PST 24
Peak memory 246600 kb
Host smart-b0a5aa88-4e54-4322-829a-da1bfaa6f139
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601531681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.601531681
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.1167062353
Short name T37
Test name
Test status
Simulation time 680033571126 ps
CPU time 5487.19 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 02:13:28 PM PST 24
Peak memory 321960 kb
Host smart-f861178a-1aa3-41b8-9c21-dfd7fde47d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167062353 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.1167062353
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4004145617
Short name T162
Test name
Test status
Simulation time 14419982177 ps
CPU time 1056.39 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:52:37 PM PST 24
Peak memory 265040 kb
Host smart-b4378418-50d6-4ce2-82b8-5fca507b2397
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004145617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4004145617
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.2335926643
Short name T233
Test name
Test status
Simulation time 13437136375 ps
CPU time 535.65 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:50:22 PM PST 24
Peak memory 247920 kb
Host smart-a58105ed-3cb2-4bdd-b202-6251a986ba47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335926643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.2335926643
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.324113847
Short name T140
Test name
Test status
Simulation time 64326280797 ps
CPU time 1300.22 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:56:41 PM PST 24
Peak memory 265096 kb
Host smart-bf84b187-0205-49ba-8371-746497b6e043
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324113847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.324113847
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.660079970
Short name T340
Test name
Test status
Simulation time 20755188 ps
CPU time 1.41 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 236084 kb
Host smart-60a18e1b-4cf8-47bb-a46f-ab5903a97cf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=660079970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.660079970
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3258453677
Short name T324
Test name
Test status
Simulation time 54296005383 ps
CPU time 3158.13 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 01:34:31 PM PST 24
Peak memory 281620 kb
Host smart-6c85ec11-71a7-4ce7-967e-e14a7fb5a69e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258453677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3258453677
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.4006084783
Short name T59
Test name
Test status
Simulation time 153673787132 ps
CPU time 1981.9 seconds
Started Mar 03 12:42:24 PM PST 24
Finished Mar 03 01:15:26 PM PST 24
Peak memory 289596 kb
Host smart-9e76877c-59f7-49d2-b8e8-7be0142fb879
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006084783 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.4006084783
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2936666493
Short name T4
Test name
Test status
Simulation time 55435666899 ps
CPU time 1186.91 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 01:02:03 PM PST 24
Peak memory 289784 kb
Host smart-15a79e46-6dd6-4c01-9284-47f7f0491dfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936666493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2936666493
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2425588015
Short name T343
Test name
Test status
Simulation time 113965257 ps
CPU time 4.72 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:35:18 PM PST 24
Peak memory 239968 kb
Host smart-108cd042-b0e4-46a7-82f4-049f09fe9d3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2425588015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2425588015
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1650355403
Short name T261
Test name
Test status
Simulation time 160659360444 ps
CPU time 2714.59 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 01:27:07 PM PST 24
Peak memory 305212 kb
Host smart-1b9c4018-c023-4bba-b3a2-9f602224fe2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650355403 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1650355403
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1051374706
Short name T48
Test name
Test status
Simulation time 20647456281 ps
CPU time 1487.85 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 01:06:40 PM PST 24
Peak memory 273416 kb
Host smart-a3b7f4ba-e78d-4bc5-87ce-ae9311576fcb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051374706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1051374706
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4044643170
Short name T161
Test name
Test status
Simulation time 6216325177 ps
CPU time 676.62 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 265284 kb
Host smart-b410e104-c693-4eb9-90ce-2fc8afafb8a2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044643170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4044643170
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.4187039446
Short name T109
Test name
Test status
Simulation time 13011680364 ps
CPU time 716.99 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:53:56 PM PST 24
Peak memory 265240 kb
Host smart-83b91886-4784-4ac4-a2f3-dfbd02ade631
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187039446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.4187039446
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3841054421
Short name T314
Test name
Test status
Simulation time 10412520873 ps
CPU time 471.92 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:49:51 PM PST 24
Peak memory 248732 kb
Host smart-db70061b-3ecd-4011-b112-da3b5e388b0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841054421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3841054421
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3348260574
Short name T296
Test name
Test status
Simulation time 28488900078 ps
CPU time 313.2 seconds
Started Mar 03 12:42:33 PM PST 24
Finished Mar 03 12:47:48 PM PST 24
Peak memory 246264 kb
Host smart-324ebd37-c3df-488b-ab0b-4ce79fd91c6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348260574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3348260574
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.372290075
Short name T173
Test name
Test status
Simulation time 35138414 ps
CPU time 2.91 seconds
Started Mar 03 12:35:15 PM PST 24
Finished Mar 03 12:35:19 PM PST 24
Peak memory 236556 kb
Host smart-51fa2a71-5d83-4348-92c1-702d9cb07bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=372290075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.372290075
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.330245246
Short name T131
Test name
Test status
Simulation time 875542905 ps
CPU time 94.41 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:36:19 PM PST 24
Peak memory 256672 kb
Host smart-761dede1-fa64-4f1f-b0ea-93c16c8733f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=330245246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.330245246
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.84769685
Short name T153
Test name
Test status
Simulation time 3504775220 ps
CPU time 188.11 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 264956 kb
Host smart-4413a8e6-5af1-4823-a34b-4c9e3ec036d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=84769685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_error
s.84769685
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.357248776
Short name T247
Test name
Test status
Simulation time 45964494023 ps
CPU time 3074.35 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 01:33:03 PM PST 24
Peak memory 284424 kb
Host smart-e31e900a-fb27-4c7e-895b-3ba1dc57a358
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357248776 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.357248776
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4248828937
Short name T285
Test name
Test status
Simulation time 74796314274 ps
CPU time 2180.39 seconds
Started Mar 03 12:41:59 PM PST 24
Finished Mar 03 01:18:21 PM PST 24
Peak memory 288844 kb
Host smart-af34cd6e-f323-4f5a-99d6-cf06fffd70ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248828937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4248828937
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.967021943
Short name T145
Test name
Test status
Simulation time 28404749038 ps
CPU time 464.07 seconds
Started Mar 03 12:35:10 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 265084 kb
Host smart-dd9c02ff-ee26-4cf9-92aa-da759a24cab0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967021943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.967021943
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3529969505
Short name T215
Test name
Test status
Simulation time 128600179 ps
CPU time 4.08 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:13 PM PST 24
Peak memory 248944 kb
Host smart-43dc0e1d-ab7b-46c3-8b12-26563d6826e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3529969505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3529969505
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1595606079
Short name T216
Test name
Test status
Simulation time 39960590 ps
CPU time 2.17 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:17 PM PST 24
Peak memory 248888 kb
Host smart-fcd75e61-4410-4ff7-b112-76df0c8b1bf5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1595606079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1595606079
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1849756961
Short name T204
Test name
Test status
Simulation time 21703723 ps
CPU time 2.11 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:18 PM PST 24
Peak memory 248916 kb
Host smart-a3fff62c-b36a-4480-9f46-17cb4676cc73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1849756961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1849756961
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2626269584
Short name T219
Test name
Test status
Simulation time 34180447 ps
CPU time 3.57 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 249028 kb
Host smart-e5718b01-b48a-499a-90ba-8f7c75d44025
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2626269584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2626269584
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1577067813
Short name T249
Test name
Test status
Simulation time 1110782094880 ps
CPU time 3943.94 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:47:00 PM PST 24
Peak memory 298748 kb
Host smart-d5edcb44-302c-4dd9-83d5-272acb2d5c0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577067813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1577067813
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4265544196
Short name T245
Test name
Test status
Simulation time 1346847113 ps
CPU time 25.96 seconds
Started Mar 03 12:42:51 PM PST 24
Finished Mar 03 12:43:18 PM PST 24
Peak memory 252892 kb
Host smart-ed4edd0d-e0dd-4897-8565-8306f59e99a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
44196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4265544196
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1308231792
Short name T252
Test name
Test status
Simulation time 119960768109 ps
CPU time 1144.03 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 01:00:20 PM PST 24
Peak memory 289796 kb
Host smart-5b62213f-6967-4398-bc3b-a643ec2d5e0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308231792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1308231792
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2533511621
Short name T288
Test name
Test status
Simulation time 201088420121 ps
CPU time 3031.94 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 01:32:32 PM PST 24
Peak memory 289104 kb
Host smart-0306cf0e-cc18-4835-a97c-dc02090baab8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533511621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2533511621
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2706656807
Short name T119
Test name
Test status
Simulation time 85634920687 ps
CPU time 9298.12 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 03:17:11 PM PST 24
Peak memory 403920 kb
Host smart-b9836e62-b675-4afc-9478-5c7190ca2261
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706656807 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2706656807
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3469333146
Short name T257
Test name
Test status
Simulation time 125524935823 ps
CPU time 6493.57 seconds
Started Mar 03 12:42:08 PM PST 24
Finished Mar 03 02:30:22 PM PST 24
Peak memory 350940 kb
Host smart-dd60938a-75b9-4ddb-a122-c265e260e9e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469333146 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3469333146
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.4163610846
Short name T272
Test name
Test status
Simulation time 15698042099 ps
CPU time 1258.14 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 01:02:31 PM PST 24
Peak memory 284896 kb
Host smart-54308a52-8581-494f-aeba-6f3030e9665c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163610846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4163610846
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3856766849
Short name T27
Test name
Test status
Simulation time 70553340563 ps
CPU time 6768.96 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 333520 kb
Host smart-e5d775f1-8a55-4330-8ec1-a64cf1d33ae9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856766849 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3856766849
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3486680861
Short name T179
Test name
Test status
Simulation time 271111951 ps
CPU time 2.17 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 236548 kb
Host smart-347fd0d9-b3b7-47ce-979b-94be4941c642
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3486680861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3486680861
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1777284652
Short name T139
Test name
Test status
Simulation time 2058202520 ps
CPU time 227.84 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 272052 kb
Host smart-61690e23-2c80-4470-94fe-b8f2549306c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1777284652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1777284652
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3749376076
Short name T777
Test name
Test status
Simulation time 9085119 ps
CPU time 1.6 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:35:15 PM PST 24
Peak memory 234404 kb
Host smart-e371da16-b109-42b5-94ef-7aceab66b7d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3749376076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3749376076
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.315762365
Short name T222
Test name
Test status
Simulation time 23493194143 ps
CPU time 484.55 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:49:24 PM PST 24
Peak memory 247632 kb
Host smart-1849dfab-5985-40b8-82b9-07a1b40f1546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315762365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.315762365
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3267534190
Short name T319
Test name
Test status
Simulation time 26808284709 ps
CPU time 558.58 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:50:35 PM PST 24
Peak memory 247728 kb
Host smart-83d0fe37-9f6f-43ba-8fb7-38e98df8c4bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267534190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3267534190
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.445452582
Short name T269
Test name
Test status
Simulation time 141382193 ps
CPU time 5.11 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 247080 kb
Host smart-fe955279-c02d-4d55-8321-114688a01db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44545
2582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.445452582
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1651782329
Short name T57
Test name
Test status
Simulation time 29417941025 ps
CPU time 1544.5 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 01:07:04 PM PST 24
Peak memory 289900 kb
Host smart-41b0dc7a-6118-4ba3-bbac-3963e995645f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651782329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1651782329
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3889932385
Short name T271
Test name
Test status
Simulation time 2027630693 ps
CPU time 44.99 seconds
Started Mar 03 12:43:00 PM PST 24
Finished Mar 03 12:43:45 PM PST 24
Peak memory 248572 kb
Host smart-52bec521-f60e-4777-9661-8a11a3a77247
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38899
32385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3889932385
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.4079937095
Short name T227
Test name
Test status
Simulation time 752656940143 ps
CPU time 3070.49 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 01:33:53 PM PST 24
Peak memory 288736 kb
Host smart-4b3b1207-d8a7-449b-bee4-dac271b8f6cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079937095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.4079937095
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.222173775
Short name T75
Test name
Test status
Simulation time 910831275 ps
CPU time 51.27 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:47 PM PST 24
Peak memory 256352 kb
Host smart-cec5ed80-f6bf-4bb7-b940-cdaf465ed483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22217
3775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.222173775
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1549264030
Short name T40
Test name
Test status
Simulation time 729552813 ps
CPU time 28.23 seconds
Started Mar 03 12:42:00 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 255572 kb
Host smart-0ba58589-ed29-419a-bd81-53f78ddcee5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
64030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1549264030
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1321469824
Short name T266
Test name
Test status
Simulation time 931974037 ps
CPU time 15.17 seconds
Started Mar 03 12:42:19 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 252392 kb
Host smart-d5cbb1c0-1a20-4b93-b7c8-1b3df84e5cd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13214
69824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1321469824
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2590818490
Short name T293
Test name
Test status
Simulation time 34234367060 ps
CPU time 1046.68 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 12:59:42 PM PST 24
Peak memory 273044 kb
Host smart-36605504-f884-4ca6-99ad-7df12c015317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590818490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2590818490
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2802332258
Short name T248
Test name
Test status
Simulation time 785833451 ps
CPU time 43.89 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:43:13 PM PST 24
Peak memory 255636 kb
Host smart-edf95ff8-c4ba-4231-acd6-592a7b068f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28023
32258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2802332258
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4004169560
Short name T281
Test name
Test status
Simulation time 34624422476 ps
CPU time 2042.23 seconds
Started Mar 03 12:42:30 PM PST 24
Finished Mar 03 01:16:32 PM PST 24
Peak memory 272868 kb
Host smart-f1bba0ad-4f59-45fe-81ec-f6976fff5bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004169560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4004169560
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2341740882
Short name T255
Test name
Test status
Simulation time 434131952 ps
CPU time 29.42 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:43 PM PST 24
Peak memory 254932 kb
Host smart-eb615239-1751-4aa8-bac6-088fde00066e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23417
40882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2341740882
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.276142901
Short name T15
Test name
Test status
Simulation time 694073390 ps
CPU time 19.28 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 272884 kb
Host smart-d50ec7ee-d0fc-4ce5-a2ee-27e3f2bbe967
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=276142901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.276142901
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3210747942
Short name T175
Test name
Test status
Simulation time 111804475 ps
CPU time 3.91 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:35:05 PM PST 24
Peak memory 236156 kb
Host smart-584e21af-715f-4ff6-99f5-9a7ed9b7bb17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3210747942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3210747942
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3024163498
Short name T171
Test name
Test status
Simulation time 106545567 ps
CPU time 5.27 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 236160 kb
Host smart-ddc262f9-0b5e-45cc-b06d-c09e27c3a67e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3024163498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3024163498
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3151398717
Short name T150
Test name
Test status
Simulation time 4392236666 ps
CPU time 143.23 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:37:30 PM PST 24
Peak memory 256296 kb
Host smart-3027a047-f8f6-46d7-8a5e-c82188cd8b66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3151398717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3151398717
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2005282783
Short name T149
Test name
Test status
Simulation time 30739644305 ps
CPU time 311.54 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:40:19 PM PST 24
Peak memory 265040 kb
Host smart-f7755a9d-8b69-43aa-a3bc-12a3f0161725
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2005282783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2005282783
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1042493145
Short name T167
Test name
Test status
Simulation time 1248599901 ps
CPU time 41.07 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:42 PM PST 24
Peak memory 236396 kb
Host smart-62c3bcab-da5f-4056-9e25-127490869caa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1042493145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1042493145
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2728295156
Short name T134
Test name
Test status
Simulation time 33384602766 ps
CPU time 616.34 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:45:18 PM PST 24
Peak memory 267668 kb
Host smart-023e0224-9aee-45ab-b6c4-258d0a7f46f4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728295156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2728295156
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.4270776380
Short name T138
Test name
Test status
Simulation time 1823181056 ps
CPU time 234.67 seconds
Started Mar 03 12:35:09 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 264916 kb
Host smart-3207a125-c4ad-478b-a0ad-96d199824323
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4270776380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.4270776380
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.775538473
Short name T144
Test name
Test status
Simulation time 4383674485 ps
CPU time 294.7 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:40:02 PM PST 24
Peak memory 265132 kb
Host smart-423bffa0-7e2f-4a53-81ef-c14b62a553d8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775538473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.775538473
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.488955181
Short name T180
Test name
Test status
Simulation time 562158338 ps
CPU time 44.06 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:35:58 PM PST 24
Peak memory 240092 kb
Host smart-0757e65f-729a-480f-a488-2f7211762643
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=488955181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.488955181
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2139259241
Short name T186
Test name
Test status
Simulation time 114668123 ps
CPU time 5.9 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:53 PM PST 24
Peak memory 236484 kb
Host smart-4e5cfef3-5982-4916-8a23-172353ea816a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2139259241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2139259241
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4217987852
Short name T177
Test name
Test status
Simulation time 60266881 ps
CPU time 2.68 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:47 PM PST 24
Peak memory 236116 kb
Host smart-1860a0ee-2d9e-4000-a11a-52961e454aaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4217987852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4217987852
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.336642222
Short name T174
Test name
Test status
Simulation time 1319465563 ps
CPU time 80.92 seconds
Started Mar 03 12:34:53 PM PST 24
Finished Mar 03 12:36:14 PM PST 24
Peak memory 236320 kb
Host smart-c5c249f5-d1c1-4063-b25d-a9f62fdecfc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=336642222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.336642222
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2336921649
Short name T185
Test name
Test status
Simulation time 389616176 ps
CPU time 21.69 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 236232 kb
Host smart-8ba15238-2996-4629-8824-1670da4642e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2336921649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2336921649
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2156385502
Short name T178
Test name
Test status
Simulation time 55791331 ps
CPU time 4.03 seconds
Started Mar 03 12:34:55 PM PST 24
Finished Mar 03 12:34:59 PM PST 24
Peak memory 236160 kb
Host smart-df3afa14-2c1e-4b60-b2ed-a1b620da7071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2156385502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2156385502
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1322033690
Short name T172
Test name
Test status
Simulation time 71285386 ps
CPU time 3.09 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 236256 kb
Host smart-45eafc0b-5d77-455e-9122-0313cc8e44e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1322033690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1322033690
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2989366867
Short name T25
Test name
Test status
Simulation time 35224252907 ps
CPU time 1510.51 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 01:07:12 PM PST 24
Peak memory 288908 kb
Host smart-fbcebcf3-f0a8-4d9b-b491-7f30016fef43
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989366867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2989366867
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3329868955
Short name T744
Test name
Test status
Simulation time 1732579174 ps
CPU time 131.74 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:37:01 PM PST 24
Peak memory 240008 kb
Host smart-fff599fa-b94b-41c4-b98d-19395e28b935
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3329868955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3329868955
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.896190533
Short name T761
Test name
Test status
Simulation time 4951192098 ps
CPU time 206.76 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:38:12 PM PST 24
Peak memory 240128 kb
Host smart-ac1ec38f-407f-4042-b1fb-24250bf9b1d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=896190533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.896190533
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3157823420
Short name T194
Test name
Test status
Simulation time 26801411 ps
CPU time 3.72 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:51 PM PST 24
Peak memory 239940 kb
Host smart-a4e1ceb0-b473-4470-8048-7d679896df71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3157823420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3157823420
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.1040243385
Short name T796
Test name
Test status
Simulation time 73785514 ps
CPU time 6.13 seconds
Started Mar 03 12:34:50 PM PST 24
Finished Mar 03 12:34:56 PM PST 24
Peak memory 238876 kb
Host smart-6abc9de7-cd09-4fed-96a9-7d54f593aef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040243385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.1040243385
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1629824438
Short name T785
Test name
Test status
Simulation time 502044614 ps
CPU time 10.42 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:57 PM PST 24
Peak memory 236068 kb
Host smart-79abfe27-86c7-4dea-a093-f7f3c764f507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1629824438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1629824438
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.1301211251
Short name T766
Test name
Test status
Simulation time 106282128 ps
CPU time 1.56 seconds
Started Mar 03 12:34:44 PM PST 24
Finished Mar 03 12:34:46 PM PST 24
Peak memory 236184 kb
Host smart-12022d7c-14fe-4762-9caf-a746d2aedf46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1301211251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.1301211251
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3537662884
Short name T768
Test name
Test status
Simulation time 2568468821 ps
CPU time 39.08 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:35:24 PM PST 24
Peak memory 248320 kb
Host smart-1609ad58-47a6-4a16-9af2-d0f02c7201da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3537662884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3537662884
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2348364454
Short name T159
Test name
Test status
Simulation time 2088959986 ps
CPU time 149.14 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:37:16 PM PST 24
Peak memory 256692 kb
Host smart-5109b0dc-b66d-46bd-aaf4-972f3c53df0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2348364454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2348364454
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.103572700
Short name T814
Test name
Test status
Simulation time 480545291 ps
CPU time 33.12 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:35:34 PM PST 24
Peak memory 248128 kb
Host smart-bab8b77c-21d4-4aa8-a5cf-5677db61833b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103572700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.103572700
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2333179705
Short name T742
Test name
Test status
Simulation time 1108421720 ps
CPU time 63.42 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:36:04 PM PST 24
Peak memory 236240 kb
Host smart-10bec54e-b154-49e6-babb-24a0bc28f3a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2333179705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2333179705
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1079614106
Short name T345
Test name
Test status
Simulation time 5954270165 ps
CPU time 197.71 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:38:05 PM PST 24
Peak memory 236208 kb
Host smart-2f881c7b-9389-45fd-9c82-f76a1df244a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1079614106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1079614106
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.651991280
Short name T759
Test name
Test status
Simulation time 434932727 ps
CPU time 7.73 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 239996 kb
Host smart-5fd2d085-fa68-4c41-8f67-4714d9e9b0d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=651991280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.651991280
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3922184540
Short name T745
Test name
Test status
Simulation time 51241578 ps
CPU time 4.67 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:34:56 PM PST 24
Peak memory 240152 kb
Host smart-8cf3cc0c-db02-471f-a678-23b45df0dd47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922184540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3922184540
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2050536301
Short name T183
Test name
Test status
Simulation time 241160724 ps
CPU time 5.52 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:54 PM PST 24
Peak memory 236000 kb
Host smart-9ed9ad20-ae4e-481f-a6f5-7f2f6d6cc2be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2050536301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2050536301
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2695081619
Short name T802
Test name
Test status
Simulation time 29734749 ps
CPU time 1.36 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:34:46 PM PST 24
Peak memory 235320 kb
Host smart-4e5432ce-c119-465c-a998-a37d76d14273
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2695081619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2695081619
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3978873128
Short name T795
Test name
Test status
Simulation time 84667044 ps
CPU time 11.17 seconds
Started Mar 03 12:34:55 PM PST 24
Finished Mar 03 12:35:07 PM PST 24
Peak memory 244356 kb
Host smart-687b6ae7-d2e2-4c44-be23-8558389c551d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3978873128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3978873128
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.915669921
Short name T148
Test name
Test status
Simulation time 11715593639 ps
CPU time 413.51 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:41:40 PM PST 24
Peak memory 267328 kb
Host smart-e64e355e-3304-465d-a3d1-785461a132b2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915669921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.915669921
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.216580403
Short name T242
Test name
Test status
Simulation time 217933928 ps
CPU time 4.7 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:52 PM PST 24
Peak memory 239412 kb
Host smart-b2fa3c34-bbed-4d6c-a0e5-bea32f3f15e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=216580403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.216580403
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.901528931
Short name T791
Test name
Test status
Simulation time 903513824 ps
CPU time 30.74 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:31 PM PST 24
Peak memory 240140 kb
Host smart-760d9875-87e6-44dd-aec8-dae3ca8255fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=901528931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.901528931
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3888641877
Short name T799
Test name
Test status
Simulation time 828555976 ps
CPU time 7.64 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 250400 kb
Host smart-7a4809de-47ee-4312-b3b5-1e2d7c823a79
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888641877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3888641877
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.371844915
Short name T714
Test name
Test status
Simulation time 81948392 ps
CPU time 4.82 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 235172 kb
Host smart-860ce96f-8ffb-44df-be3a-b647d3bc7011
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=371844915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.371844915
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1102247481
Short name T807
Test name
Test status
Simulation time 60559040 ps
CPU time 1.46 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:01 PM PST 24
Peak memory 235320 kb
Host smart-a0e687fc-8276-4e5f-9397-078b58fd2870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102247481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1102247481
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1473416326
Short name T721
Test name
Test status
Simulation time 672326074 ps
CPU time 39.34 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:41 PM PST 24
Peak memory 248256 kb
Host smart-b7fb91e9-0d9f-4af9-80d1-47126285b6ab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1473416326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1473416326
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1220044968
Short name T132
Test name
Test status
Simulation time 780498285 ps
CPU time 91.73 seconds
Started Mar 03 12:35:20 PM PST 24
Finished Mar 03 12:36:58 PM PST 24
Peak memory 256712 kb
Host smart-d12d1cbf-f29e-47db-abe6-417ecee100c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1220044968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1220044968
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2060463898
Short name T736
Test name
Test status
Simulation time 721241681 ps
CPU time 21.92 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:35:29 PM PST 24
Peak memory 248684 kb
Host smart-562fdd87-8014-4e2f-947a-107e7de32b9c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2060463898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2060463898
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2374325383
Short name T176
Test name
Test status
Simulation time 522949788 ps
CPU time 34.94 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:42 PM PST 24
Peak memory 240400 kb
Host smart-0f5e6537-46df-4d0b-baa5-c671b2395650
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2374325383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2374325383
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2330303370
Short name T730
Test name
Test status
Simulation time 219975395 ps
CPU time 7.47 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:12 PM PST 24
Peak memory 250668 kb
Host smart-36ce1b99-853d-4de3-bd5e-bce39154d3d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330303370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2330303370
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2229151268
Short name T819
Test name
Test status
Simulation time 36092251 ps
CPU time 3.55 seconds
Started Mar 03 12:35:19 PM PST 24
Finished Mar 03 12:35:23 PM PST 24
Peak memory 236172 kb
Host smart-a5847241-b757-4724-b370-237a057cae8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2229151268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2229151268
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3514582596
Short name T780
Test name
Test status
Simulation time 15920833 ps
CPU time 1.46 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 236112 kb
Host smart-be294cb0-e5c6-417f-9d16-dbfe8f6ca6bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3514582596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3514582596
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2130712483
Short name T820
Test name
Test status
Simulation time 1368965098 ps
CPU time 21.74 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:25 PM PST 24
Peak memory 244692 kb
Host smart-aa176515-03a8-44ed-b95c-8b77f9e33b64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2130712483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2130712483
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1620287564
Short name T240
Test name
Test status
Simulation time 774012369 ps
CPU time 9.9 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 251804 kb
Host smart-fbc6c919-5792-499e-b5d6-aaf5ddf6bbfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1620287564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1620287564
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3346112004
Short name T725
Test name
Test status
Simulation time 37234099 ps
CPU time 5.14 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 255436 kb
Host smart-8afd0929-b44b-4afd-9ff8-7fe70657ae11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346112004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3346112004
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.933160712
Short name T756
Test name
Test status
Simulation time 112512950 ps
CPU time 7.21 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 235220 kb
Host smart-0bff241c-aa1a-4645-9a87-e90d6bce9f53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=933160712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.933160712
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.348282456
Short name T181
Test name
Test status
Simulation time 989673823 ps
CPU time 18.66 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:22 PM PST 24
Peak memory 240076 kb
Host smart-96ae79f8-9072-4c61-9ffb-e1528acef684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=348282456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.348282456
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2739614770
Short name T817
Test name
Test status
Simulation time 2715650158 ps
CPU time 180.71 seconds
Started Mar 03 12:35:25 PM PST 24
Finished Mar 03 12:38:26 PM PST 24
Peak memory 257152 kb
Host smart-1cdd0a89-1a6d-444f-a86c-0a9310ae2ee6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2739614770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2739614770
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1729778401
Short name T708
Test name
Test status
Simulation time 996219354 ps
CPU time 18.97 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:23 PM PST 24
Peak memory 248340 kb
Host smart-9988cf66-7698-4aa9-85e1-da13a9435bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1729778401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1729778401
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3871763121
Short name T812
Test name
Test status
Simulation time 100827725 ps
CPU time 4.9 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 250580 kb
Host smart-0e0a7e54-44bb-46ae-9c1a-b06eb1d769c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871763121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3871763121
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.543143209
Short name T769
Test name
Test status
Simulation time 134033998 ps
CPU time 8.74 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:35:23 PM PST 24
Peak memory 240040 kb
Host smart-9986e35a-314a-4d79-85df-d2754b65cfa0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=543143209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.543143209
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1219312510
Short name T733
Test name
Test status
Simulation time 2046830903 ps
CPU time 19.8 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:25 PM PST 24
Peak memory 243556 kb
Host smart-aa4545d9-fab5-4c07-9243-d3520719a125
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1219312510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1219312510
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3409405512
Short name T239
Test name
Test status
Simulation time 1225497761 ps
CPU time 20.91 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:25 PM PST 24
Peak memory 254236 kb
Host smart-dd177e4c-34e7-4528-b0b0-c99a8462f5ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3409405512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3409405512
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3705678430
Short name T719
Test name
Test status
Simulation time 176716495 ps
CPU time 8.19 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 239180 kb
Host smart-e16283ac-d633-4ff5-99b7-f0435ea43fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705678430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3705678430
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.713865638
Short name T241
Test name
Test status
Simulation time 273227569 ps
CPU time 4.85 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 239876 kb
Host smart-f39d45ab-cce4-4564-ae89-89395d966db0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=713865638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.713865638
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2220531160
Short name T765
Test name
Test status
Simulation time 16096613 ps
CPU time 1.29 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:03 PM PST 24
Peak memory 236180 kb
Host smart-62fed952-2ce8-4886-ad30-20fb6a7fbe23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2220531160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2220531160
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2813512820
Short name T712
Test name
Test status
Simulation time 1552147555 ps
CPU time 9.01 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:12 PM PST 24
Peak memory 243424 kb
Host smart-1b7299a0-a5f8-4001-a924-464c85b7d5bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2813512820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2813512820
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2471610437
Short name T146
Test name
Test status
Simulation time 25339582151 ps
CPU time 304.63 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:40:12 PM PST 24
Peak memory 265120 kb
Host smart-50336822-b982-4f4e-9ee6-f211be9a2fe6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2471610437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2471610437
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1150080605
Short name T158
Test name
Test status
Simulation time 16152726951 ps
CPU time 336.46 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:40:37 PM PST 24
Peak memory 265140 kb
Host smart-5b9735ca-d25d-405a-bf89-26270d7cce3a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150080605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1150080605
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.689984339
Short name T746
Test name
Test status
Simulation time 64498751 ps
CPU time 4.71 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:35:07 PM PST 24
Peak memory 247560 kb
Host smart-830c5769-ce9a-47d6-87fc-aabb5446778c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=689984339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.689984339
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1502127729
Short name T764
Test name
Test status
Simulation time 793589657 ps
CPU time 13.67 seconds
Started Mar 03 12:35:44 PM PST 24
Finished Mar 03 12:35:58 PM PST 24
Peak memory 250812 kb
Host smart-f6b8f044-cb5a-4d1d-ade3-b0ded75a8a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502127729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1502127729
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1268024685
Short name T815
Test name
Test status
Simulation time 966773213 ps
CPU time 8.3 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 236088 kb
Host smart-11305a76-c0fa-4cba-9a9e-7c3efa36ee10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1268024685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1268024685
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3700900060
Short name T788
Test name
Test status
Simulation time 6199880 ps
CPU time 1.34 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 235292 kb
Host smart-04908f23-11df-45a3-b497-15440c2c4fe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3700900060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3700900060
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.609764091
Short name T182
Test name
Test status
Simulation time 326194023 ps
CPU time 19.44 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:35:22 PM PST 24
Peak memory 243432 kb
Host smart-b45d58e8-b4a1-44da-8069-30f51d8f4156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=609764091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.609764091
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2180803687
Short name T151
Test name
Test status
Simulation time 2651186396 ps
CPU time 174.39 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:37:39 PM PST 24
Peak memory 256380 kb
Host smart-3d113482-373b-4090-947e-807976897dc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2180803687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2180803687
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3641932655
Short name T164
Test name
Test status
Simulation time 24968323966 ps
CPU time 1022.23 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:52:04 PM PST 24
Peak memory 265036 kb
Host smart-1e1f47fd-2432-447f-91e8-4a8d2cec6d86
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641932655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3641932655
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.720944547
Short name T821
Test name
Test status
Simulation time 723283671 ps
CPU time 11.76 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:12 PM PST 24
Peak memory 248304 kb
Host smart-4a397cb7-2ae8-47aa-bad0-510c6b8c914c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=720944547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.720944547
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.4140381361
Short name T734
Test name
Test status
Simulation time 124761862 ps
CPU time 5.47 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 250564 kb
Host smart-4cb7265f-b6db-4ca2-9a67-f935141f55de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140381361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.4140381361
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3458465403
Short name T752
Test name
Test status
Simulation time 33644706 ps
CPU time 5.74 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 236088 kb
Host smart-6444b29c-5ee4-4097-a774-4e757be89a51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3458465403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3458465403
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2029350181
Short name T748
Test name
Test status
Simulation time 15392900 ps
CPU time 1.75 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 236180 kb
Host smart-8e881843-6fbf-4882-b341-c08a4e87be8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2029350181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2029350181
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1738045798
Short name T727
Test name
Test status
Simulation time 2165295709 ps
CPU time 37.15 seconds
Started Mar 03 12:35:11 PM PST 24
Finished Mar 03 12:35:49 PM PST 24
Peak memory 244412 kb
Host smart-c86c8c74-d6fc-45d4-878c-53c7ec9632b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1738045798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1738045798
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3180501729
Short name T128
Test name
Test status
Simulation time 8090158458 ps
CPU time 487.18 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:43:12 PM PST 24
Peak memory 267832 kb
Host smart-b951f86a-d116-4889-aa52-ff17eb5ec92e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180501729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3180501729
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2938328836
Short name T713
Test name
Test status
Simulation time 75854739 ps
CPU time 5.75 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 248328 kb
Host smart-adfa5724-4110-4803-9e0d-bebb1c025ee4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2938328836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2938328836
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.621512470
Short name T723
Test name
Test status
Simulation time 124253546 ps
CPU time 9.95 seconds
Started Mar 03 12:34:52 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 253360 kb
Host smart-014acaee-5e3f-4660-bcbb-f7862f8a4d02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621512470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.621512470
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.4281849399
Short name T787
Test name
Test status
Simulation time 69689475 ps
CPU time 5.78 seconds
Started Mar 03 12:35:12 PM PST 24
Finished Mar 03 12:35:18 PM PST 24
Peak memory 236088 kb
Host smart-e57aaede-af31-4cbd-9ef5-f678c83c5d5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4281849399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.4281849399
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2290955285
Short name T168
Test name
Test status
Simulation time 40074599 ps
CPU time 1.28 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 236024 kb
Host smart-efd8772c-4a86-4830-8b97-43706e7640bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2290955285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2290955285
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4093643010
Short name T749
Test name
Test status
Simulation time 9719505606 ps
CPU time 39.42 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:43 PM PST 24
Peak memory 244320 kb
Host smart-02e62223-71c2-46af-af2c-57d8f39b9bf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4093643010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4093643010
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1771794506
Short name T720
Test name
Test status
Simulation time 540033411 ps
CPU time 8.83 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:16 PM PST 24
Peak memory 248232 kb
Host smart-1968fee0-7855-4a0e-8b7f-dfae3e6134f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1771794506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1771794506
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2811038342
Short name T747
Test name
Test status
Simulation time 107471882 ps
CPU time 7.47 seconds
Started Mar 03 12:35:26 PM PST 24
Finished Mar 03 12:35:34 PM PST 24
Peak memory 240236 kb
Host smart-588e262c-01f6-4ffb-9db8-2e102d8db9ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811038342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2811038342
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.606609231
Short name T750
Test name
Test status
Simulation time 37240401 ps
CPU time 5.36 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:54 PM PST 24
Peak memory 236116 kb
Host smart-1c48479d-98cd-4193-bcc4-23091dbaa1b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=606609231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.606609231
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1564659246
Short name T715
Test name
Test status
Simulation time 7999792 ps
CPU time 1.34 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 235408 kb
Host smart-d53c6381-204f-4a59-9ccf-15c9076649dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1564659246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1564659246
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3507526833
Short name T196
Test name
Test status
Simulation time 89749116 ps
CPU time 12.77 seconds
Started Mar 03 12:35:11 PM PST 24
Finished Mar 03 12:35:24 PM PST 24
Peak memory 244280 kb
Host smart-22a3c047-3676-492c-a58c-5accabb2592b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507526833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3507526833
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.921527910
Short name T707
Test name
Test status
Simulation time 1122314831 ps
CPU time 9.61 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:17 PM PST 24
Peak memory 248168 kb
Host smart-f5c3eb8d-4a07-41f9-b065-8f92aa096a1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=921527910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.921527910
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3308424669
Short name T775
Test name
Test status
Simulation time 88790899 ps
CPU time 2.56 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 236044 kb
Host smart-d9e4e08b-e110-49a6-901c-9f07bbcf1f7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3308424669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3308424669
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2426402563
Short name T781
Test name
Test status
Simulation time 156626410 ps
CPU time 10.93 seconds
Started Mar 03 12:35:09 PM PST 24
Finished Mar 03 12:35:20 PM PST 24
Peak memory 242468 kb
Host smart-971fa113-592c-4ef5-942c-2ba9ac00e550
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426402563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2426402563
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3000363397
Short name T347
Test name
Test status
Simulation time 375946403 ps
CPU time 8.22 seconds
Started Mar 03 12:35:18 PM PST 24
Finished Mar 03 12:35:31 PM PST 24
Peak memory 235212 kb
Host smart-91ec6470-a170-4ae6-9d1f-abc5ecb13eb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3000363397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3000363397
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4173988870
Short name T758
Test name
Test status
Simulation time 6815816 ps
CPU time 1.48 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:05 PM PST 24
Peak memory 236164 kb
Host smart-9c186f4d-30f9-414d-8811-2e20ee6dac0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4173988870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4173988870
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2002914385
Short name T826
Test name
Test status
Simulation time 300170450 ps
CPU time 18.73 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:26 PM PST 24
Peak memory 243364 kb
Host smart-cb5fcb5c-1996-46aa-ae4c-05358395473f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2002914385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2002914385
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1886443528
Short name T156
Test name
Test status
Simulation time 849450069 ps
CPU time 98.82 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:36:43 PM PST 24
Peak memory 265136 kb
Host smart-62ffcbdf-0e0d-40ca-9030-2f7747222e65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1886443528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1886443528
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.1126815697
Short name T129
Test name
Test status
Simulation time 24461879416 ps
CPU time 306.27 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:40:10 PM PST 24
Peak memory 264904 kb
Host smart-a27e3063-f043-4894-a763-76d963216887
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126815697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.1126815697
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1622856142
Short name T753
Test name
Test status
Simulation time 354616234 ps
CPU time 12.4 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 248360 kb
Host smart-8c4686bd-cd35-4197-bc8d-cce104c40e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1622856142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1622856142
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4051337925
Short name T783
Test name
Test status
Simulation time 3448714221 ps
CPU time 253.43 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:39:04 PM PST 24
Peak memory 240072 kb
Host smart-1a8524c3-a217-48d1-bdbf-f108c25564e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4051337925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4051337925
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2250716628
Short name T743
Test name
Test status
Simulation time 5930884358 ps
CPU time 271.23 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:39:18 PM PST 24
Peak memory 236208 kb
Host smart-cde846f0-452b-4f35-8a20-77d38690ee2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2250716628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2250716628
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3655862723
Short name T732
Test name
Test status
Simulation time 51024153 ps
CPU time 4.91 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:56 PM PST 24
Peak memory 240360 kb
Host smart-f2dfbf45-1ed8-493d-be7e-46bae44c7b96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3655862723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3655862723
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3120085591
Short name T782
Test name
Test status
Simulation time 118626420 ps
CPU time 4.61 seconds
Started Mar 03 12:34:51 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 240864 kb
Host smart-8650aaa0-d6dd-46ff-a80c-0ca15fe8fbfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120085591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3120085591
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1847584590
Short name T798
Test name
Test status
Simulation time 120479552 ps
CPU time 4.36 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:35:07 PM PST 24
Peak memory 235160 kb
Host smart-dfac3b36-7b90-41cd-872a-dc6063fe0dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1847584590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1847584590
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.1138061514
Short name T801
Test name
Test status
Simulation time 9872278 ps
CPU time 1.27 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 236136 kb
Host smart-b1cb11a8-86c1-4484-8311-8731c9211907
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1138061514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1138061514
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2522329892
Short name T751
Test name
Test status
Simulation time 5863398648 ps
CPU time 37.8 seconds
Started Mar 03 12:34:50 PM PST 24
Finished Mar 03 12:35:28 PM PST 24
Peak memory 248412 kb
Host smart-8c705f45-1bce-486f-af50-ca46abdf721b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2522329892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2522329892
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3251697827
Short name T160
Test name
Test status
Simulation time 20711455940 ps
CPU time 500.78 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:43:21 PM PST 24
Peak memory 267760 kb
Host smart-85d77971-74a5-47f4-a69c-1d8d0620552d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251697827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3251697827
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1432131659
Short name T737
Test name
Test status
Simulation time 120372698 ps
CPU time 7.86 seconds
Started Mar 03 12:35:14 PM PST 24
Finished Mar 03 12:35:22 PM PST 24
Peak memory 248024 kb
Host smart-89815842-025b-4bf0-946f-c464ed53e72a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1432131659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1432131659
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1990073966
Short name T339
Test name
Test status
Simulation time 12029161 ps
CPU time 1.23 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 235180 kb
Host smart-a1f6925d-0367-4dd3-817c-c2045eb12e5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1990073966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1990073966
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4282133426
Short name T800
Test name
Test status
Simulation time 9619000 ps
CPU time 1.26 seconds
Started Mar 03 12:35:15 PM PST 24
Finished Mar 03 12:35:18 PM PST 24
Peak memory 234396 kb
Host smart-caeb418d-1439-475b-a6a3-a6fbfcd73a42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4282133426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4282133426
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3834626804
Short name T729
Test name
Test status
Simulation time 16965770 ps
CPU time 1.28 seconds
Started Mar 03 12:35:18 PM PST 24
Finished Mar 03 12:35:19 PM PST 24
Peak memory 234324 kb
Host smart-8d266665-0dbb-4149-8616-0a4113c77b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3834626804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3834626804
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2884543443
Short name T804
Test name
Test status
Simulation time 10822440 ps
CPU time 1.54 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 235296 kb
Host smart-3d3b3d47-9ce6-46c6-a6c2-f91af7115b26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2884543443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2884543443
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1874833731
Short name T757
Test name
Test status
Simulation time 15363695 ps
CPU time 1.34 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 234320 kb
Host smart-0bf952f5-8e68-46a2-b169-e6962c86e42e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1874833731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1874833731
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1762144298
Short name T824
Test name
Test status
Simulation time 7335893 ps
CPU time 1.37 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 236068 kb
Host smart-5b0d6420-d3ca-4302-9844-5459d784fa51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762144298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1762144298
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4283483019
Short name T709
Test name
Test status
Simulation time 8207736 ps
CPU time 1.45 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 234224 kb
Host smart-20a02210-81d3-4d4b-a278-eefabb14cbf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4283483019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4283483019
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1997426522
Short name T336
Test name
Test status
Simulation time 15613528 ps
CPU time 1.27 seconds
Started Mar 03 12:35:05 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 236068 kb
Host smart-1ff57453-3fe1-4a7e-bee5-ebccf8e4b539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1997426522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1997426522
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2104422768
Short name T794
Test name
Test status
Simulation time 15788589 ps
CPU time 1.38 seconds
Started Mar 03 12:35:28 PM PST 24
Finished Mar 03 12:35:30 PM PST 24
Peak memory 236168 kb
Host smart-16b5703d-8f43-41d5-9343-9f6fedfe84ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2104422768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2104422768
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1290608611
Short name T728
Test name
Test status
Simulation time 6811317 ps
CPU time 1.42 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 235328 kb
Host smart-2537d839-b7d4-45b4-8d7f-2bd4b7a641a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1290608611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1290608611
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.588430003
Short name T741
Test name
Test status
Simulation time 58215239699 ps
CPU time 289.12 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:39:50 PM PST 24
Peak memory 240152 kb
Host smart-a5ed9d78-87dc-4300-9904-68ec426358df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=588430003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.588430003
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2018667949
Short name T793
Test name
Test status
Simulation time 11652089079 ps
CPU time 334.33 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:40:35 PM PST 24
Peak memory 235252 kb
Host smart-11d9a279-dc51-4221-9c08-15341d55bb97
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2018667949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2018667949
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3415387743
Short name T740
Test name
Test status
Simulation time 129994344 ps
CPU time 10.55 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:35:00 PM PST 24
Peak memory 239960 kb
Host smart-f4df53ef-a93f-4c0b-80d4-1b91784d4d15
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3415387743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3415387743
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.711102741
Short name T722
Test name
Test status
Simulation time 102539308 ps
CPU time 4.36 seconds
Started Mar 03 12:35:03 PM PST 24
Finished Mar 03 12:35:07 PM PST 24
Peak memory 238428 kb
Host smart-20a136a2-afd5-481d-901a-998cbf318c14
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711102741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.711102741
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.288511756
Short name T809
Test name
Test status
Simulation time 26423904 ps
CPU time 3.55 seconds
Started Mar 03 12:35:14 PM PST 24
Finished Mar 03 12:35:18 PM PST 24
Peak memory 239948 kb
Host smart-828a2c7a-ce18-4b8b-b580-1b5c2bc3e572
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=288511756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.288511756
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2980214660
Short name T805
Test name
Test status
Simulation time 6871715 ps
CPU time 1.4 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 235348 kb
Host smart-83ac3f80-3d15-4774-a2a3-2fbd73ceb2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2980214660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2980214660
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1568867922
Short name T184
Test name
Test status
Simulation time 696774691 ps
CPU time 19.08 seconds
Started Mar 03 12:34:50 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 248288 kb
Host smart-f8f055b8-9e7d-488d-a9a0-2982ce3f7623
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1568867922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1568867922
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2465792342
Short name T137
Test name
Test status
Simulation time 1660922923 ps
CPU time 101.5 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:36:45 PM PST 24
Peak memory 264912 kb
Host smart-0b7d8871-f82a-4de0-ab42-2d73b402122a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2465792342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2465792342
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1318197490
Short name T774
Test name
Test status
Simulation time 1752179925 ps
CPU time 9.2 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 248324 kb
Host smart-0c49aa0e-f55b-40dc-9c92-c5428a4a6ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1318197490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1318197490
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4080937833
Short name T187
Test name
Test status
Simulation time 58994736 ps
CPU time 3.96 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 235284 kb
Host smart-ff46d2ff-f603-4b6d-a801-d0c1c9c60374
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4080937833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4080937833
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2108335433
Short name T823
Test name
Test status
Simulation time 9464316 ps
CPU time 1.27 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 236148 kb
Host smart-fc3049fc-2813-41da-8389-7db35a39ee3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2108335433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2108335433
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.381759259
Short name T337
Test name
Test status
Simulation time 10115336 ps
CPU time 1.49 seconds
Started Mar 03 12:35:11 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 236168 kb
Host smart-f4342dbf-93c3-451b-b775-e41f606ade54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=381759259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.381759259
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2881737550
Short name T754
Test name
Test status
Simulation time 8284360 ps
CPU time 1.56 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 236160 kb
Host smart-2f849b3a-37ec-4cc3-a807-392d4277a5ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2881737550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2881737550
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3972088067
Short name T738
Test name
Test status
Simulation time 7526842 ps
CPU time 1.53 seconds
Started Mar 03 12:35:14 PM PST 24
Finished Mar 03 12:35:23 PM PST 24
Peak memory 234404 kb
Host smart-cf087319-2a0c-4838-a331-45b3774ddd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3972088067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3972088067
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3439536377
Short name T718
Test name
Test status
Simulation time 7854616 ps
CPU time 1.51 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 234312 kb
Host smart-f49a1eed-3ff6-4541-a553-d44c26582232
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3439536377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3439536377
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4195430100
Short name T735
Test name
Test status
Simulation time 11874507 ps
CPU time 1.63 seconds
Started Mar 03 12:35:12 PM PST 24
Finished Mar 03 12:35:14 PM PST 24
Peak memory 235300 kb
Host smart-f76f448e-62ac-4822-bf50-1eb6c3b45b48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4195430100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4195430100
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2964276464
Short name T784
Test name
Test status
Simulation time 9819635 ps
CPU time 1.51 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:03 PM PST 24
Peak memory 235308 kb
Host smart-370cc38f-c9a9-4238-a471-c425e2c2f5bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2964276464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2964276464
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3210935490
Short name T803
Test name
Test status
Simulation time 20226955 ps
CPU time 1.3 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 235260 kb
Host smart-6b505550-8b00-4a76-a5c1-6d03c875acda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3210935490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3210935490
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.921518318
Short name T816
Test name
Test status
Simulation time 53909219 ps
CPU time 1.38 seconds
Started Mar 03 12:35:04 PM PST 24
Finished Mar 03 12:35:05 PM PST 24
Peak memory 235408 kb
Host smart-ad411f7e-c08a-4c09-a66d-a8b7e61e4cd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=921518318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.921518318
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3213518215
Short name T170
Test name
Test status
Simulation time 18810607 ps
CPU time 1.44 seconds
Started Mar 03 12:35:19 PM PST 24
Finished Mar 03 12:35:21 PM PST 24
Peak memory 235288 kb
Host smart-090a7284-b239-4864-9082-c754f308cf22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3213518215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3213518215
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.3932019971
Short name T731
Test name
Test status
Simulation time 3415168505 ps
CPU time 116.65 seconds
Started Mar 03 12:35:09 PM PST 24
Finished Mar 03 12:37:06 PM PST 24
Peak memory 240148 kb
Host smart-d58a8cc4-5b7b-4549-bef4-5840d43002a5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3932019971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.3932019971
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3934609672
Short name T792
Test name
Test status
Simulation time 1819201856 ps
CPU time 100.1 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:36:54 PM PST 24
Peak memory 240036 kb
Host smart-28f8fee6-92e5-49a1-be09-ec60481d9136
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3934609672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3934609672
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.928320654
Short name T810
Test name
Test status
Simulation time 45533302 ps
CPU time 6.6 seconds
Started Mar 03 12:34:50 PM PST 24
Finished Mar 03 12:34:57 PM PST 24
Peak memory 240096 kb
Host smart-e0c0364a-ff40-420f-ab4b-4e1c772a8bd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=928320654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.928320654
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2790533865
Short name T724
Test name
Test status
Simulation time 88789290 ps
CPU time 5.55 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 256404 kb
Host smart-7dfe5182-8e02-41c3-9949-212ba7954df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790533865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2790533865
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3083509380
Short name T771
Test name
Test status
Simulation time 1352087553 ps
CPU time 43.61 seconds
Started Mar 03 12:34:59 PM PST 24
Finished Mar 03 12:35:44 PM PST 24
Peak memory 244416 kb
Host smart-8f513353-b2c6-4ac9-af54-b90254962354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3083509380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3083509380
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.640453325
Short name T163
Test name
Test status
Simulation time 3732288670 ps
CPU time 278.45 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:39:27 PM PST 24
Peak memory 272252 kb
Host smart-38831e46-571f-4508-8d3b-534c084b9bc6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=640453325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.640453325
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1802574741
Short name T808
Test name
Test status
Simulation time 29486892 ps
CPU time 4.02 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 248328 kb
Host smart-29ad7c44-1525-4096-abcf-16a457d0cdb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1802574741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1802574741
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1108251522
Short name T789
Test name
Test status
Simulation time 9561819 ps
CPU time 1.42 seconds
Started Mar 03 12:35:18 PM PST 24
Finished Mar 03 12:35:20 PM PST 24
Peak memory 236264 kb
Host smart-785ca2b6-91e6-4f5e-a78c-542961786133
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1108251522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1108251522
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3617279962
Short name T755
Test name
Test status
Simulation time 12507089 ps
CPU time 1.48 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 235332 kb
Host smart-44a90f08-8e56-444c-9ef3-4bf063661f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3617279962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3617279962
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2673791199
Short name T813
Test name
Test status
Simulation time 23760246 ps
CPU time 1.17 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 236180 kb
Host smart-b5e4ff93-bc10-4913-b569-d8520bccea55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2673791199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2673791199
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.282354854
Short name T767
Test name
Test status
Simulation time 13040654 ps
CPU time 1.28 seconds
Started Mar 03 12:34:54 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 236204 kb
Host smart-b32f48b2-7d40-405f-9dcf-966dd7e3ec21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=282354854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.282354854
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.972733806
Short name T338
Test name
Test status
Simulation time 8276337 ps
CPU time 1.32 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:34:51 PM PST 24
Peak memory 236244 kb
Host smart-458cd41c-3aa4-4cb2-8c40-509bcd00aad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=972733806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.972733806
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2690837369
Short name T169
Test name
Test status
Simulation time 11504622 ps
CPU time 1.23 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 235260 kb
Host smart-645433a3-7ed3-4d7d-80e6-f96c945696c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2690837369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2690837369
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2479165315
Short name T760
Test name
Test status
Simulation time 8614587 ps
CPU time 1.32 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 235348 kb
Host smart-236537a6-6040-4080-8e4a-6d66d963df67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2479165315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2479165315
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1204151055
Short name T717
Test name
Test status
Simulation time 10527809 ps
CPU time 1.34 seconds
Started Mar 03 12:35:33 PM PST 24
Finished Mar 03 12:35:34 PM PST 24
Peak memory 236168 kb
Host smart-df15bd40-55a1-4003-8414-0af7ea73c45b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1204151055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1204151055
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1468521717
Short name T790
Test name
Test status
Simulation time 14921413 ps
CPU time 1.26 seconds
Started Mar 03 12:35:22 PM PST 24
Finished Mar 03 12:35:23 PM PST 24
Peak memory 234216 kb
Host smart-66b2f3a3-5eb0-4ecb-b26c-14ebb77ba361
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1468521717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1468521717
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1618049677
Short name T773
Test name
Test status
Simulation time 8090927 ps
CPU time 1.39 seconds
Started Mar 03 12:35:07 PM PST 24
Finished Mar 03 12:35:18 PM PST 24
Peak memory 234384 kb
Host smart-0c6009dc-882f-42f5-ac4e-ba9e043293fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1618049677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1618049677
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.935349560
Short name T786
Test name
Test status
Simulation time 283277503 ps
CPU time 6.77 seconds
Started Mar 03 12:34:52 PM PST 24
Finished Mar 03 12:34:59 PM PST 24
Peak memory 240148 kb
Host smart-d6ffbdd3-9eb1-4344-a167-7ca44f6d18d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935349560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.935349560
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.595081529
Short name T770
Test name
Test status
Simulation time 334027507 ps
CPU time 7.99 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 235296 kb
Host smart-ca414d22-cd18-472e-bae7-e6d345a5e95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=595081529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.595081529
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1546357417
Short name T811
Test name
Test status
Simulation time 6501135 ps
CPU time 1.37 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 236188 kb
Host smart-c4761e3e-5d34-4974-bea3-4b3cee554ebc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546357417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1546357417
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3485362967
Short name T762
Test name
Test status
Simulation time 607752363 ps
CPU time 34.49 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:35:24 PM PST 24
Peak memory 248240 kb
Host smart-fa2f1f5a-3bae-4c68-99cf-cb7dbf22756a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3485362967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3485362967
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.2855569917
Short name T344
Test name
Test status
Simulation time 18381065904 ps
CPU time 631.14 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:45:19 PM PST 24
Peak memory 264996 kb
Host smart-8ab8a659-4fc3-41c9-b752-0e1902b9aea3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855569917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.2855569917
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1382783571
Short name T776
Test name
Test status
Simulation time 485042400 ps
CPU time 5.14 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 252792 kb
Host smart-ab430048-2a6c-4324-9872-28a6e06130e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1382783571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1382783571
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2158449091
Short name T818
Test name
Test status
Simulation time 181037875 ps
CPU time 9.38 seconds
Started Mar 03 12:34:54 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 250396 kb
Host smart-3251d725-8e9c-42ae-9df8-9284c0b2f1a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158449091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2158449091
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2587343334
Short name T346
Test name
Test status
Simulation time 331174140 ps
CPU time 7.91 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 236084 kb
Host smart-b47e8d36-4433-4a2c-ac9b-5e44ee12ca5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2587343334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2587343334
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2835294983
Short name T243
Test name
Test status
Simulation time 11110407 ps
CPU time 1.58 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 236096 kb
Host smart-9e16eb56-6634-4c41-bcf4-b1cf43ae2eb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2835294983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2835294983
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3098660568
Short name T711
Test name
Test status
Simulation time 2870514803 ps
CPU time 42.09 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:43 PM PST 24
Peak memory 244400 kb
Host smart-1e02998b-134d-449c-8707-225a83f3ce22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3098660568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3098660568
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2094861732
Short name T152
Test name
Test status
Simulation time 3748640524 ps
CPU time 178.99 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:37:46 PM PST 24
Peak memory 256740 kb
Host smart-fb373a6a-35ea-482b-ba06-81359e6ab3df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2094861732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2094861732
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2666086993
Short name T772
Test name
Test status
Simulation time 174504376 ps
CPU time 11.8 seconds
Started Mar 03 12:35:29 PM PST 24
Finished Mar 03 12:35:41 PM PST 24
Peak memory 246804 kb
Host smart-000b2621-54b7-4d0e-a4f8-7dc1a5235203
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2666086993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2666086993
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.121602334
Short name T825
Test name
Test status
Simulation time 580718558 ps
CPU time 19.09 seconds
Started Mar 03 12:35:17 PM PST 24
Finished Mar 03 12:35:36 PM PST 24
Peak memory 244780 kb
Host smart-51374b35-5e74-4597-b84c-e55db673b298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=121602334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.121602334
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.270299739
Short name T822
Test name
Test status
Simulation time 552895359 ps
CPU time 9.02 seconds
Started Mar 03 12:34:54 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 239228 kb
Host smart-f636ebec-4711-4c19-9f3f-7a3db756469a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270299739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.270299739
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4047463353
Short name T763
Test name
Test status
Simulation time 112033469 ps
CPU time 5.36 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:06 PM PST 24
Peak memory 235204 kb
Host smart-a6292b04-c1a8-448b-b9a3-c837f6305146
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4047463353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4047463353
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.357402850
Short name T341
Test name
Test status
Simulation time 14714014 ps
CPU time 1.25 seconds
Started Mar 03 12:34:52 PM PST 24
Finished Mar 03 12:34:53 PM PST 24
Peak memory 235316 kb
Host smart-a0046459-3175-4e40-bfdc-dedcd426c93b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=357402850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.357402850
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1914541335
Short name T195
Test name
Test status
Simulation time 508947838 ps
CPU time 34.21 seconds
Started Mar 03 12:34:50 PM PST 24
Finished Mar 03 12:35:24 PM PST 24
Peak memory 244352 kb
Host smart-9352e505-444d-456c-90bc-f290ad37ddb2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1914541335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1914541335
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3269149402
Short name T154
Test name
Test status
Simulation time 1440473446 ps
CPU time 91.61 seconds
Started Mar 03 12:35:16 PM PST 24
Finished Mar 03 12:36:48 PM PST 24
Peak memory 265276 kb
Host smart-5bed3197-7b59-4885-9fb3-3e936afd09c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3269149402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3269149402
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.4071815482
Short name T155
Test name
Test status
Simulation time 131486667108 ps
CPU time 1122.01 seconds
Started Mar 03 12:34:58 PM PST 24
Finished Mar 03 12:53:43 PM PST 24
Peak memory 265352 kb
Host smart-47e9d6b8-b779-494c-8360-6cc226e27ff9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071815482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.4071815482
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2337031857
Short name T739
Test name
Test status
Simulation time 1461066040 ps
CPU time 8.45 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:10 PM PST 24
Peak memory 248376 kb
Host smart-03715350-eb32-43b5-aa5a-7174f0fe929d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2337031857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2337031857
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.141457750
Short name T165
Test name
Test status
Simulation time 100939427 ps
CPU time 2.69 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:03 PM PST 24
Peak memory 236212 kb
Host smart-0f5e94e5-601b-41e4-9c34-64f0868d29c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=141457750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.141457750
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.4033948781
Short name T342
Test name
Test status
Simulation time 154558433 ps
CPU time 6.18 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:35:13 PM PST 24
Peak memory 240144 kb
Host smart-86dfb94d-10d1-4d4f-9f48-f38191668abf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033948781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.4033948781
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.990719415
Short name T710
Test name
Test status
Simulation time 21064635 ps
CPU time 3.07 seconds
Started Mar 03 12:34:54 PM PST 24
Finished Mar 03 12:34:58 PM PST 24
Peak memory 235260 kb
Host smart-5fa9274b-495f-415c-9cea-7a7c19806054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=990719415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.990719415
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.987787849
Short name T797
Test name
Test status
Simulation time 17328844 ps
CPU time 1.28 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:01 PM PST 24
Peak memory 234296 kb
Host smart-647e25b1-4711-4b2e-b87d-7f6f03c68e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=987787849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.987787849
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.544846706
Short name T716
Test name
Test status
Simulation time 257720681 ps
CPU time 18.52 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:19 PM PST 24
Peak memory 244352 kb
Host smart-1f5bc0e8-fc78-426d-bd7e-005bc6f771de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=544846706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.544846706
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3641930172
Short name T143
Test name
Test status
Simulation time 9810349333 ps
CPU time 160.91 seconds
Started Mar 03 12:35:06 PM PST 24
Finished Mar 03 12:37:48 PM PST 24
Peak memory 265040 kb
Host smart-7f8f2699-a589-43b2-8b11-9842d93fdda4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3641930172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3641930172
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3539232271
Short name T726
Test name
Test status
Simulation time 293604821 ps
CPU time 6.02 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:07 PM PST 24
Peak memory 240004 kb
Host smart-fa402afa-59a0-480a-8458-ead178a95afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3539232271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3539232271
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3075627220
Short name T198
Test name
Test status
Simulation time 80591637 ps
CPU time 4.97 seconds
Started Mar 03 12:34:55 PM PST 24
Finished Mar 03 12:35:01 PM PST 24
Peak memory 235284 kb
Host smart-13508658-871e-46b6-8f4c-d0b2d774f253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3075627220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3075627220
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3161452861
Short name T199
Test name
Test status
Simulation time 433544273 ps
CPU time 4.72 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:05 PM PST 24
Peak memory 239872 kb
Host smart-9287477a-46de-4a08-b48c-0cffceec4b00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161452861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3161452861
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2695441669
Short name T197
Test name
Test status
Simulation time 341028489 ps
CPU time 7.7 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:09 PM PST 24
Peak memory 236036 kb
Host smart-5e629b34-470b-480d-a1ed-4b8a3821b0fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2695441669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2695441669
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.4033887601
Short name T778
Test name
Test status
Simulation time 10438531 ps
CPU time 1.57 seconds
Started Mar 03 12:35:13 PM PST 24
Finished Mar 03 12:35:15 PM PST 24
Peak memory 235336 kb
Host smart-c2989ccc-f194-4e42-8a4a-9da6e9f7c9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033887601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.4033887601
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.967978403
Short name T779
Test name
Test status
Simulation time 1014591978 ps
CPU time 18.42 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:35:08 PM PST 24
Peak memory 243476 kb
Host smart-ee847c14-2f45-4d25-bec9-6d19f7c44a2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=967978403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.967978403
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4109937323
Short name T130
Test name
Test status
Simulation time 5943102129 ps
CPU time 292.57 seconds
Started Mar 03 12:35:02 PM PST 24
Finished Mar 03 12:39:55 PM PST 24
Peak memory 270820 kb
Host smart-5b3fc5ed-df98-4922-909e-ccfe183da8c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4109937323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4109937323
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3160250337
Short name T142
Test name
Test status
Simulation time 12779389442 ps
CPU time 449.75 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 265352 kb
Host smart-4af9ce04-19a9-4f41-9d92-4c5bacaffa55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160250337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3160250337
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1002274859
Short name T806
Test name
Test status
Simulation time 88273334 ps
CPU time 3.98 seconds
Started Mar 03 12:34:57 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 240080 kb
Host smart-18d197b1-2f39-4a94-818c-6e31dcac856f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1002274859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1002274859
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1521234382
Short name T39
Test name
Test status
Simulation time 146138824462 ps
CPU time 2966.69 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 01:30:32 PM PST 24
Peak memory 289776 kb
Host smart-ff005acd-2997-40a1-bd44-823d2e5fab55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521234382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1521234382
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.148358458
Short name T370
Test name
Test status
Simulation time 1130676672 ps
CPU time 26.22 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 12:41:39 PM PST 24
Peak memory 252508 kb
Host smart-90fda1cf-0770-42a9-bebb-729a9b0d96b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=148358458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.148358458
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3847225700
Short name T635
Test name
Test status
Simulation time 22080644603 ps
CPU time 224.15 seconds
Started Mar 03 12:41:29 PM PST 24
Finished Mar 03 12:45:14 PM PST 24
Peak memory 256992 kb
Host smart-287be18f-18a7-4533-8b70-6ba51bd2a5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38472
25700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3847225700
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2398914935
Short name T538
Test name
Test status
Simulation time 1147808788 ps
CPU time 24.95 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:39 PM PST 24
Peak memory 254912 kb
Host smart-26331018-85ec-4fc1-9deb-b473c5978d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23989
14935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2398914935
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.503680356
Short name T325
Test name
Test status
Simulation time 41222257597 ps
CPU time 2406.94 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 01:21:11 PM PST 24
Peak memory 283376 kb
Host smart-b73ad637-ec73-444c-bc34-681c0e280a21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503680356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.503680356
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.508311595
Short name T228
Test name
Test status
Simulation time 55622984561 ps
CPU time 3125.3 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:33:20 PM PST 24
Peak memory 288544 kb
Host smart-07bd474d-bfc0-427d-b2e1-a5a140288ca8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508311595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.508311595
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.528296499
Short name T238
Test name
Test status
Simulation time 38904119958 ps
CPU time 429.39 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:48:15 PM PST 24
Peak memory 247576 kb
Host smart-bef0763a-226e-471b-880f-9cfdf004141e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528296499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.528296499
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.322148341
Short name T632
Test name
Test status
Simulation time 78330348 ps
CPU time 7.22 seconds
Started Mar 03 12:41:03 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 252720 kb
Host smart-e76726c9-3f52-4a39-9a4e-3fdb08056734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32214
8341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.322148341
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4242795208
Short name T70
Test name
Test status
Simulation time 308683153 ps
CPU time 15.29 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 247160 kb
Host smart-407eabeb-2191-412a-a370-ddadc82c54c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
95208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4242795208
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3170199704
Short name T533
Test name
Test status
Simulation time 62424936 ps
CPU time 7.47 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 247140 kb
Host smart-d4c3030e-fea3-4960-bfba-f7df6a25cdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
99704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3170199704
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1670394581
Short name T393
Test name
Test status
Simulation time 891236687 ps
CPU time 4.52 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 248856 kb
Host smart-8ab20ef6-4568-4dbc-9307-adde03fcd5ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16703
94581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1670394581
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1748485000
Short name T377
Test name
Test status
Simulation time 228444873038 ps
CPU time 3537.68 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 01:40:15 PM PST 24
Peak memory 289340 kb
Host smart-024102da-7c66-4192-867b-e9d239a56f04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748485000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1748485000
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1473183730
Short name T663
Test name
Test status
Simulation time 277819931 ps
CPU time 14.72 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:41:54 PM PST 24
Peak memory 248764 kb
Host smart-51ebd18e-b35e-46c1-938a-6f3ac97a01ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1473183730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1473183730
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2001458567
Short name T435
Test name
Test status
Simulation time 7086327654 ps
CPU time 145.73 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:43:49 PM PST 24
Peak memory 256984 kb
Host smart-0b08d766-3ed3-4c17-9322-c3e0a81eda6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20014
58567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2001458567
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2966745877
Short name T475
Test name
Test status
Simulation time 2976837309 ps
CPU time 47.01 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:42:07 PM PST 24
Peak memory 255280 kb
Host smart-f510383b-2e85-4afb-832a-cccb13688297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29667
45877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2966745877
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4192627533
Short name T332
Test name
Test status
Simulation time 90387883114 ps
CPU time 1340.07 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 01:03:50 PM PST 24
Peak memory 289484 kb
Host smart-ecf58f5f-63f0-4c31-b750-39eaeca870ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192627533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4192627533
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.265946153
Short name T604
Test name
Test status
Simulation time 29557750938 ps
CPU time 1940.26 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:13:36 PM PST 24
Peak memory 282352 kb
Host smart-4800ad07-1991-4c6d-8fa6-4ae52efb6cc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265946153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.265946153
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1515623811
Short name T193
Test name
Test status
Simulation time 425548861 ps
CPU time 5.34 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:10 PM PST 24
Peak memory 240520 kb
Host smart-dbb13758-a35c-4dbf-b55d-d36b5f95570a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15156
23811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1515623811
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1172017834
Short name T698
Test name
Test status
Simulation time 2328844386 ps
CPU time 67.5 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:42:25 PM PST 24
Peak memory 255256 kb
Host smart-668eacfb-cabb-48e4-8225-0afc1e6c3ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11720
17834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1172017834
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4090301243
Short name T33
Test name
Test status
Simulation time 584521952 ps
CPU time 24.5 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:39 PM PST 24
Peak memory 276944 kb
Host smart-b01b0108-051f-47b0-97ce-5ee79ca935a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4090301243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4090301243
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.837848593
Short name T368
Test name
Test status
Simulation time 42957941 ps
CPU time 2.74 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:24 PM PST 24
Peak memory 240560 kb
Host smart-65690f77-a0dd-41f0-be4b-86854482c3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83784
8593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.837848593
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1158542423
Short name T364
Test name
Test status
Simulation time 803646011 ps
CPU time 48.4 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 248876 kb
Host smart-5e04965b-3677-4c28-b7e3-0e55cefa5a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11585
42423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1158542423
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.330542968
Short name T36
Test name
Test status
Simulation time 442375863525 ps
CPU time 2068.13 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 01:15:46 PM PST 24
Peak memory 288200 kb
Host smart-b4a2c0e5-61fc-47af-9fb0-7de83406b8b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330542968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.330542968
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.394923374
Short name T524
Test name
Test status
Simulation time 24162609309 ps
CPU time 1449.78 seconds
Started Mar 03 12:45:04 PM PST 24
Finished Mar 03 01:09:15 PM PST 24
Peak memory 287968 kb
Host smart-730e99d8-f4a7-43a3-bdbf-1db0b901857d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394923374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.394923374
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3844060145
Short name T689
Test name
Test status
Simulation time 696594600 ps
CPU time 10.07 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 240564 kb
Host smart-a24b05d2-b644-4769-a369-8d362a95b266
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3844060145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3844060145
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3180626944
Short name T465
Test name
Test status
Simulation time 3198818607 ps
CPU time 44.67 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:42:02 PM PST 24
Peak memory 256268 kb
Host smart-512bd8f5-910f-407b-b2dc-3e2514e00609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
26944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3180626944
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1810486534
Short name T419
Test name
Test status
Simulation time 1647786729 ps
CPU time 35.05 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:42:13 PM PST 24
Peak memory 255012 kb
Host smart-7d0b70c2-0d93-4a78-a3cc-d1ed1ed3da35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
86534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1810486534
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3331440077
Short name T323
Test name
Test status
Simulation time 166998009416 ps
CPU time 1931.56 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 01:13:37 PM PST 24
Peak memory 282956 kb
Host smart-e8158c80-d78d-4259-8b38-befea90dbe82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331440077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3331440077
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1401287368
Short name T415
Test name
Test status
Simulation time 10695158891 ps
CPU time 969.5 seconds
Started Mar 03 12:41:35 PM PST 24
Finished Mar 03 12:57:45 PM PST 24
Peak memory 271608 kb
Host smart-af160d1d-db4f-46e5-8762-7f8f1910f1d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401287368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1401287368
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3256322656
Short name T453
Test name
Test status
Simulation time 441135801 ps
CPU time 27.81 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:48 PM PST 24
Peak memory 248752 kb
Host smart-ae18ca55-e7a0-43e3-ae6b-744dfd86e7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
22656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3256322656
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3663335658
Short name T530
Test name
Test status
Simulation time 50801334 ps
CPU time 5.79 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 247164 kb
Host smart-93f85eaf-1383-4c87-8dd5-95287fa4f156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36633
35658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3663335658
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2700873653
Short name T3
Test name
Test status
Simulation time 911070388 ps
CPU time 34.56 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:42:21 PM PST 24
Peak memory 247148 kb
Host smart-c9cd6b9d-8c05-486c-98fd-c2cccf325a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27008
73653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2700873653
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1100924940
Short name T360
Test name
Test status
Simulation time 86683467 ps
CPU time 10.26 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:31 PM PST 24
Peak memory 253512 kb
Host smart-95cfe028-5bee-41fb-bd3f-0120a6832b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
24940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1100924940
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1143325738
Short name T675
Test name
Test status
Simulation time 44928991009 ps
CPU time 1262.45 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:02:28 PM PST 24
Peak memory 283736 kb
Host smart-c8bb294f-8551-44bb-9e68-c9ca72bc7b6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143325738 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1143325738
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1298714995
Short name T510
Test name
Test status
Simulation time 170337182972 ps
CPU time 1883.02 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 01:12:57 PM PST 24
Peak memory 282172 kb
Host smart-616a7b8c-82e8-4e91-ba82-128d238f16fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298714995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1298714995
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1652702533
Short name T9
Test name
Test status
Simulation time 5469981689 ps
CPU time 58.4 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 12:42:24 PM PST 24
Peak memory 240620 kb
Host smart-da29e6a6-1c5a-432c-8958-d4b05070e10b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1652702533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1652702533
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3861777923
Short name T379
Test name
Test status
Simulation time 1434201347 ps
CPU time 66.05 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:42:25 PM PST 24
Peak memory 255520 kb
Host smart-67584164-ec76-4969-bfa7-c3064f6289ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38617
77923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3861777923
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2056557906
Short name T612
Test name
Test status
Simulation time 129205490 ps
CPU time 11.42 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:35 PM PST 24
Peak memory 248352 kb
Host smart-2c87b637-097b-4024-8280-03d5b7069ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20565
57906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2056557906
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.599641373
Short name T609
Test name
Test status
Simulation time 11436526554 ps
CPU time 1155.74 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 01:00:33 PM PST 24
Peak memory 273084 kb
Host smart-9e1fe4f7-5d6a-46cb-a02a-95c8257ffde0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599641373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.599641373
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.266967182
Short name T517
Test name
Test status
Simulation time 27832285111 ps
CPU time 1663.91 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 01:09:18 PM PST 24
Peak memory 272456 kb
Host smart-22b2c7a8-bba7-4d56-89d3-f22f5c5e5f32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266967182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.266967182
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1597610869
Short name T311
Test name
Test status
Simulation time 4904076294 ps
CPU time 193.09 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 12:48:26 PM PST 24
Peak memory 247320 kb
Host smart-43b27568-d8a5-479a-b004-689f7ef46b80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597610869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1597610869
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.533397305
Short name T428
Test name
Test status
Simulation time 3305216891 ps
CPU time 42.19 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 248824 kb
Host smart-e53aa3cd-f034-40f7-aa2f-91dbb98cc968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53339
7305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.533397305
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.339030454
Short name T664
Test name
Test status
Simulation time 9278137444 ps
CPU time 74.35 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:42:53 PM PST 24
Peak memory 255344 kb
Host smart-91f6b93e-db94-4ae7-9179-32dc8cad398c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33903
0454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.339030454
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2892215182
Short name T1
Test name
Test status
Simulation time 1031312346 ps
CPU time 57.82 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:42:17 PM PST 24
Peak memory 248776 kb
Host smart-b845a081-b0ed-4fb5-a2d7-cd305b12bf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28922
15182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2892215182
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1849058166
Short name T466
Test name
Test status
Simulation time 2232375183 ps
CPU time 67.12 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 255780 kb
Host smart-658586bd-39a4-444e-b36d-b425ed52623b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18490
58166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1849058166
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2286808951
Short name T49
Test name
Test status
Simulation time 12240856049 ps
CPU time 1336.26 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 01:03:34 PM PST 24
Peak memory 288048 kb
Host smart-086aab4c-d361-46ef-a16f-0fbb0217b2f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286808951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2286808951
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1413016125
Short name T234
Test name
Test status
Simulation time 122978449368 ps
CPU time 1917.96 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 01:13:24 PM PST 24
Peak memory 286868 kb
Host smart-e2b767d6-4592-4931-a79b-adb6a9bdffae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413016125 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1413016125
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2832094254
Short name T205
Test name
Test status
Simulation time 37841272 ps
CPU time 2.3 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:41:39 PM PST 24
Peak memory 248888 kb
Host smart-9cdc00e0-8030-4820-9ed8-a03c2320fe6a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2832094254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2832094254
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1158320494
Short name T627
Test name
Test status
Simulation time 127266797022 ps
CPU time 1935.03 seconds
Started Mar 03 12:41:35 PM PST 24
Finished Mar 03 01:13:51 PM PST 24
Peak memory 284196 kb
Host smart-f72d8981-0bbe-4407-93fe-5ec1fc08d99c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158320494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1158320494
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.4059037024
Short name T367
Test name
Test status
Simulation time 341459524 ps
CPU time 9.91 seconds
Started Mar 03 12:41:31 PM PST 24
Finished Mar 03 12:41:41 PM PST 24
Peak memory 240544 kb
Host smart-f27d7a78-31e6-4087-90f7-640881e07c12
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4059037024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.4059037024
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3397276532
Short name T220
Test name
Test status
Simulation time 1868735236 ps
CPU time 49.98 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:42:06 PM PST 24
Peak memory 254032 kb
Host smart-06f29560-d8bb-49a8-aa5f-053700515a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33972
76532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3397276532
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1589234918
Short name T565
Test name
Test status
Simulation time 210625900 ps
CPU time 15.52 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:41:42 PM PST 24
Peak memory 255196 kb
Host smart-17a7d273-761c-420a-843c-588b6305a6c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15892
34918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1589234918
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1719552290
Short name T287
Test name
Test status
Simulation time 51542182968 ps
CPU time 3035.01 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 01:32:08 PM PST 24
Peak memory 289428 kb
Host smart-171f87d5-a160-4b04-94d4-21c731550b05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719552290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1719552290
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2688413049
Short name T619
Test name
Test status
Simulation time 89069710962 ps
CPU time 494.17 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 12:49:42 PM PST 24
Peak memory 255920 kb
Host smart-f3c82746-9a22-46df-930b-001bc8f3a29c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688413049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2688413049
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2685031019
Short name T472
Test name
Test status
Simulation time 123994005 ps
CPU time 9.09 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 12:45:22 PM PST 24
Peak memory 252476 kb
Host smart-2098c7dc-aa71-447f-ad17-f5520c61e2ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26850
31019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2685031019
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3004344453
Short name T578
Test name
Test status
Simulation time 1173193185 ps
CPU time 13.73 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:41:35 PM PST 24
Peak memory 254888 kb
Host smart-ac59c88c-3e02-4506-b946-fcbb2e5aa605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30043
44453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3004344453
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3159626418
Short name T672
Test name
Test status
Simulation time 1450659196 ps
CPU time 30.23 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:49 PM PST 24
Peak memory 248864 kb
Host smart-ceea5f4a-8e90-4415-bf4e-0e3a07524305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31596
26418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3159626418
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3869448831
Short name T41
Test name
Test status
Simulation time 864992571 ps
CPU time 47.64 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:42:26 PM PST 24
Peak memory 249080 kb
Host smart-a71972b7-d5f2-436c-a32f-46f18412fbd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38694
48831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3869448831
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.790592012
Short name T20
Test name
Test status
Simulation time 30367947363 ps
CPU time 432.68 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:48:51 PM PST 24
Peak memory 257020 kb
Host smart-422aec1e-44ed-4255-aff3-d4db5063db65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790592012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.790592012
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3227194468
Short name T210
Test name
Test status
Simulation time 182111816 ps
CPU time 4.04 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 248944 kb
Host smart-b28170ee-1e5e-483d-a8f0-da65d459a42f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3227194468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3227194468
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1864986924
Short name T662
Test name
Test status
Simulation time 54135212245 ps
CPU time 3295.62 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 01:36:29 PM PST 24
Peak memory 289780 kb
Host smart-45f85884-5591-4490-9b51-e6dca2bed6a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864986924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1864986924
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3226005412
Short name T654
Test name
Test status
Simulation time 276724019 ps
CPU time 8.78 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 12:41:50 PM PST 24
Peak memory 240668 kb
Host smart-b9da3594-b51a-4f7e-a9e8-e6d4ab435321
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3226005412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3226005412
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.422233362
Short name T363
Test name
Test status
Simulation time 7330926080 ps
CPU time 75.68 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 256236 kb
Host smart-4304fffb-557a-44f4-94b5-5452aa4b9f49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42223
3362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.422233362
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2268877245
Short name T63
Test name
Test status
Simulation time 102698332 ps
CPU time 7.34 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:26 PM PST 24
Peak memory 249512 kb
Host smart-afa0b93d-65df-463e-8081-ea4ce3b1ead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22688
77245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2268877245
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2266633135
Short name T38
Test name
Test status
Simulation time 65455081496 ps
CPU time 1356.14 seconds
Started Mar 03 12:41:42 PM PST 24
Finished Mar 03 01:04:19 PM PST 24
Peak memory 289516 kb
Host smart-dd28025b-51ee-44dc-b1be-6d69e13dd253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266633135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2266633135
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1055651609
Short name T605
Test name
Test status
Simulation time 86955191198 ps
CPU time 1247.59 seconds
Started Mar 03 12:41:42 PM PST 24
Finished Mar 03 01:02:30 PM PST 24
Peak memory 272488 kb
Host smart-be8d2081-dc9d-4b59-8441-1461d6edfcfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055651609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1055651609
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1413136335
Short name T464
Test name
Test status
Simulation time 1214002099 ps
CPU time 22.18 seconds
Started Mar 03 12:41:31 PM PST 24
Finished Mar 03 12:41:54 PM PST 24
Peak memory 248756 kb
Host smart-e4f2323c-a27c-4ad5-98ea-88056be6a1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
36335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1413136335
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4162299768
Short name T491
Test name
Test status
Simulation time 4895088864 ps
CPU time 65.12 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:42:25 PM PST 24
Peak memory 255296 kb
Host smart-ebee3479-df5f-43cb-9d88-0a715435415e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41622
99768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4162299768
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2803159123
Short name T256
Test name
Test status
Simulation time 2609057299 ps
CPU time 56.94 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 256004 kb
Host smart-06d9fe1d-44aa-4a68-840e-aa70e02f3c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28031
59123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2803159123
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.445935573
Short name T448
Test name
Test status
Simulation time 245753844 ps
CPU time 4.88 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 240576 kb
Host smart-2204d31e-1c73-4920-a09d-fc0ca794f142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44593
5573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.445935573
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2350716449
Short name T55
Test name
Test status
Simulation time 78664282995 ps
CPU time 7449.62 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 02:45:48 PM PST 24
Peak memory 354904 kb
Host smart-4ad10825-1239-44dd-bddf-b9e5d461cf4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350716449 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2350716449
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3637448248
Short name T202
Test name
Test status
Simulation time 57015479 ps
CPU time 3.29 seconds
Started Mar 03 12:42:59 PM PST 24
Finished Mar 03 12:43:02 PM PST 24
Peak memory 248556 kb
Host smart-d96e603a-a9a4-482c-97d2-dd92a6617a1e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637448248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3637448248
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.4148090328
Short name T462
Test name
Test status
Simulation time 153195016 ps
CPU time 8.64 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 12:41:50 PM PST 24
Peak memory 240548 kb
Host smart-40865591-a37c-455b-992f-16ca283fd33a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4148090328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.4148090328
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.394707089
Short name T232
Test name
Test status
Simulation time 1136948600 ps
CPU time 37.81 seconds
Started Mar 03 12:41:28 PM PST 24
Finished Mar 03 12:42:06 PM PST 24
Peak memory 255232 kb
Host smart-5f5208f2-49de-4ddf-a7eb-ea82530c9e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39470
7089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.394707089
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3882285977
Short name T86
Test name
Test status
Simulation time 1694495428 ps
CPU time 30.38 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:50 PM PST 24
Peak memory 255388 kb
Host smart-490aa3df-5039-4418-8dc3-b58fa0bac521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822
85977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3882285977
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3241461710
Short name T312
Test name
Test status
Simulation time 197073665124 ps
CPU time 3014.47 seconds
Started Mar 03 12:41:28 PM PST 24
Finished Mar 03 01:31:44 PM PST 24
Peak memory 285684 kb
Host smart-814fc05b-4c54-4f3e-b3a3-3283795fd793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241461710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3241461710
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1876178982
Short name T547
Test name
Test status
Simulation time 29975186554 ps
CPU time 1311.62 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 01:07:05 PM PST 24
Peak memory 264420 kb
Host smart-f4957734-d70c-473f-8f82-d9975e1be35e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876178982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1876178982
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2498379460
Short name T313
Test name
Test status
Simulation time 18663271977 ps
CPU time 201.57 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:45:10 PM PST 24
Peak memory 247488 kb
Host smart-8f7886f6-1694-4858-b333-3d9cf79bdf36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498379460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2498379460
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.482141784
Short name T470
Test name
Test status
Simulation time 2948862242 ps
CPU time 40.39 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 255736 kb
Host smart-2bd03dbd-4212-46f8-8faa-95a6bd0320a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48214
1784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.482141784
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2412525486
Short name T405
Test name
Test status
Simulation time 149608971 ps
CPU time 10.94 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:41:32 PM PST 24
Peak memory 248260 kb
Host smart-34bfec57-1210-4f4d-95ab-6ae92abb6398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24125
25486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2412525486
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.930875269
Short name T35
Test name
Test status
Simulation time 38372334 ps
CPU time 5.85 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 12:45:19 PM PST 24
Peak memory 256532 kb
Host smart-040c1943-ae60-43cd-bb1b-f614368980b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93087
5269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.930875269
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1092935032
Short name T208
Test name
Test status
Simulation time 135098639 ps
CPU time 3.09 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 248900 kb
Host smart-0b0e083e-f616-4e24-92b7-2b9cc02b2df1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1092935032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1092935032
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3755569525
Short name T24
Test name
Test status
Simulation time 81254461211 ps
CPU time 1327.66 seconds
Started Mar 03 12:42:59 PM PST 24
Finished Mar 03 01:05:07 PM PST 24
Peak memory 289292 kb
Host smart-07698b0c-a699-46a7-bffa-da6b3df4093d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755569525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3755569525
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1926011332
Short name T191
Test name
Test status
Simulation time 468101053 ps
CPU time 21.84 seconds
Started Mar 03 12:41:35 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 240564 kb
Host smart-f2f2fc0e-4a23-4952-8a8e-e1dfa55f19e1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1926011332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1926011332
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3971310838
Short name T608
Test name
Test status
Simulation time 8193526716 ps
CPU time 268.61 seconds
Started Mar 03 12:43:00 PM PST 24
Finished Mar 03 12:47:28 PM PST 24
Peak memory 256608 kb
Host smart-a20ad04a-9c17-4369-a2d6-ffc1e2b14d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39713
10838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3971310838
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2193352463
Short name T68
Test name
Test status
Simulation time 277541154 ps
CPU time 18.36 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:42:04 PM PST 24
Peak memory 253176 kb
Host smart-4023a9d8-e71c-4308-a020-fb34edda397e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21933
52463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2193352463
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3974027656
Short name T486
Test name
Test status
Simulation time 57037665555 ps
CPU time 3250.66 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 01:35:33 PM PST 24
Peak memory 289088 kb
Host smart-2f8df1aa-a792-4b09-acfc-ce4b98ac26fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974027656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3974027656
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3271515199
Short name T568
Test name
Test status
Simulation time 60637472259 ps
CPU time 430.53 seconds
Started Mar 03 12:45:04 PM PST 24
Finished Mar 03 12:52:15 PM PST 24
Peak memory 246240 kb
Host smart-7d8ddeb7-66cb-4e0a-aae6-d9cfdc815136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271515199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3271515199
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3006191684
Short name T455
Test name
Test status
Simulation time 4808600991 ps
CPU time 42.48 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 12:45:55 PM PST 24
Peak memory 254888 kb
Host smart-1241a0ea-99d5-4d56-a355-38499bc582c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30061
91684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3006191684
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.4209557895
Short name T45
Test name
Test status
Simulation time 201627335 ps
CPU time 20.12 seconds
Started Mar 03 12:45:14 PM PST 24
Finished Mar 03 12:45:34 PM PST 24
Peak memory 246692 kb
Host smart-79c82992-0ed8-4776-a9ac-4219280c31cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
57895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.4209557895
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.380968904
Short name T587
Test name
Test status
Simulation time 283340961 ps
CPU time 19.53 seconds
Started Mar 03 12:45:14 PM PST 24
Finished Mar 03 12:45:33 PM PST 24
Peak memory 248356 kb
Host smart-829b96b8-3e17-4906-a46d-2f6f99ee31d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38096
8904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.380968904
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.776441497
Short name T121
Test name
Test status
Simulation time 266306762729 ps
CPU time 3653.17 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 01:42:31 PM PST 24
Peak memory 300140 kb
Host smart-9cfc7471-81ff-4ab6-b4e1-a8a9073f79f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776441497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.776441497
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.708035480
Short name T236
Test name
Test status
Simulation time 44179315581 ps
CPU time 1396.1 seconds
Started Mar 03 12:41:26 PM PST 24
Finished Mar 03 01:04:43 PM PST 24
Peak memory 284524 kb
Host smart-34712322-1740-43fd-b95a-04553a22b8b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708035480 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.708035480
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.486118251
Short name T211
Test name
Test status
Simulation time 61154431 ps
CPU time 2.38 seconds
Started Mar 03 12:41:34 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 248924 kb
Host smart-6662eeda-06ef-4947-b8a0-5404e2b708a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=486118251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.486118251
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.2385191827
Short name T561
Test name
Test status
Simulation time 30588727240 ps
CPU time 1689.41 seconds
Started Mar 03 12:42:51 PM PST 24
Finished Mar 03 01:11:01 PM PST 24
Peak memory 270960 kb
Host smart-86378804-2972-44be-9bf2-0f7c3acb8f70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385191827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.2385191827
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1646345780
Short name T99
Test name
Test status
Simulation time 838382008 ps
CPU time 36.16 seconds
Started Mar 03 12:43:00 PM PST 24
Finished Mar 03 12:43:36 PM PST 24
Peak memory 240204 kb
Host smart-daf06d1d-cee4-41d1-9b63-df11f1893f2a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1646345780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1646345780
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2200535708
Short name T273
Test name
Test status
Simulation time 2484312688 ps
CPU time 134.65 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:44:03 PM PST 24
Peak memory 248824 kb
Host smart-58e8654c-14a8-4b5f-85e2-6a13defa5c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22005
35708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2200535708
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3497226270
Short name T380
Test name
Test status
Simulation time 356055017 ps
CPU time 21.42 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 12:42:01 PM PST 24
Peak memory 255136 kb
Host smart-ed2fc26e-62bc-49dd-a5c5-f4df69d32cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34972
26270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3497226270
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.409835813
Short name T449
Test name
Test status
Simulation time 37740629012 ps
CPU time 2405.28 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:21:21 PM PST 24
Peak memory 273376 kb
Host smart-34b9459c-cade-4c59-9dcb-f7dff42cd9db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409835813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.409835813
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2115563151
Short name T300
Test name
Test status
Simulation time 48248365922 ps
CPU time 484.9 seconds
Started Mar 03 12:42:59 PM PST 24
Finished Mar 03 12:51:05 PM PST 24
Peak memory 247356 kb
Host smart-e293001c-7f53-4da4-90d9-e9bc0680dcaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115563151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2115563151
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2292553310
Short name T31
Test name
Test status
Simulation time 2298497891 ps
CPU time 38.39 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 248844 kb
Host smart-40501686-7cff-4700-ba8a-4e8fa1413500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22925
53310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2292553310
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3040015663
Short name T697
Test name
Test status
Simulation time 155103783 ps
CPU time 15.28 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:32 PM PST 24
Peak memory 247148 kb
Host smart-3fd299b0-b045-495d-9d21-4462d7c53469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30400
15663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3040015663
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1814233147
Short name T34
Test name
Test status
Simulation time 269797274 ps
CPU time 18.26 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 248780 kb
Host smart-d4ebf270-6303-4869-95eb-3fc5dd6c94f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18142
33147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1814233147
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1108042850
Short name T90
Test name
Test status
Simulation time 10197273322 ps
CPU time 287.73 seconds
Started Mar 03 12:42:51 PM PST 24
Finished Mar 03 12:47:39 PM PST 24
Peak memory 249672 kb
Host smart-173a477a-907f-4449-934e-d37c790094be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108042850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1108042850
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.369640431
Short name T217
Test name
Test status
Simulation time 497992132 ps
CPU time 2.69 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:41:25 PM PST 24
Peak memory 248944 kb
Host smart-1ad0cc32-a00f-4b7d-ae1a-ba9af616698f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=369640431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.369640431
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.546758250
Short name T544
Test name
Test status
Simulation time 13558028580 ps
CPU time 836.37 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 12:55:30 PM PST 24
Peak memory 270360 kb
Host smart-cb89870b-af1a-44de-a2a9-35e150b69b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546758250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.546758250
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4293796277
Short name T190
Test name
Test status
Simulation time 1479085090 ps
CPU time 20.85 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:41:51 PM PST 24
Peak memory 240644 kb
Host smart-1692b7ff-31fe-44fa-99fa-5d74e870c48c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4293796277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4293796277
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.717640081
Short name T2
Test name
Test status
Simulation time 11744501154 ps
CPU time 158.39 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:43:59 PM PST 24
Peak memory 256400 kb
Host smart-f561e8f1-ef93-4163-9939-24344ccdb3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71764
0081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.717640081
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3116420368
Short name T353
Test name
Test status
Simulation time 584775962 ps
CPU time 10.39 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:29 PM PST 24
Peak memory 251368 kb
Host smart-05389554-c47d-47cc-927c-dc3ff8146eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
20368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3116420368
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2259358435
Short name T518
Test name
Test status
Simulation time 8623509283 ps
CPU time 948.42 seconds
Started Mar 03 12:41:26 PM PST 24
Finished Mar 03 12:57:15 PM PST 24
Peak memory 273148 kb
Host smart-4b368974-8bf5-474d-aaa6-cdc9c6961389
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259358435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2259358435
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3479080791
Short name T582
Test name
Test status
Simulation time 22350981731 ps
CPU time 1430.49 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 01:05:24 PM PST 24
Peak memory 273396 kb
Host smart-104ba0ff-1e9f-4797-b710-77cf13274cde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479080791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3479080791
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2911488539
Short name T315
Test name
Test status
Simulation time 3263804735 ps
CPU time 94.8 seconds
Started Mar 03 12:41:28 PM PST 24
Finished Mar 03 12:43:04 PM PST 24
Peak memory 247504 kb
Host smart-a6d196f6-a382-4c87-b3c1-1e7785ce9290
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911488539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2911488539
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2718117208
Short name T496
Test name
Test status
Simulation time 2594060035 ps
CPU time 40.69 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 248944 kb
Host smart-caeacd10-3a4e-4570-95d7-fc2e2f3bfb70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27181
17208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2718117208
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3860026464
Short name T553
Test name
Test status
Simulation time 135916336 ps
CPU time 7.6 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 248556 kb
Host smart-4942c93b-b865-4c4c-b57c-b85d655b66a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38600
26464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3860026464
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3687961448
Short name T246
Test name
Test status
Simulation time 2252692643 ps
CPU time 40.89 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:42:00 PM PST 24
Peak memory 254068 kb
Host smart-a845d2ce-02f4-48f4-a7b7-1e22726f759b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36879
61448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3687961448
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2650761915
Short name T376
Test name
Test status
Simulation time 4995504556 ps
CPU time 30.81 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:42:07 PM PST 24
Peak memory 249020 kb
Host smart-816fb9ab-aab3-4c68-ab72-290d4e7e8394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
61915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2650761915
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.468321052
Short name T512
Test name
Test status
Simulation time 1595757132 ps
CPU time 39.4 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:42:10 PM PST 24
Peak memory 249012 kb
Host smart-065e2484-409c-4f4b-a309-163d750859db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468321052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_han
dler_stress_all.468321052
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4128177476
Short name T200
Test name
Test status
Simulation time 15890332 ps
CPU time 2.64 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:41:54 PM PST 24
Peak memory 249236 kb
Host smart-57bd9e88-633a-4ef1-82b8-0036cdc54cc1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4128177476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4128177476
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2048532469
Short name T676
Test name
Test status
Simulation time 200697186900 ps
CPU time 886.74 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:56:26 PM PST 24
Peak memory 266288 kb
Host smart-32ece16e-82db-41fc-b4da-41359e614c3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048532469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2048532469
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3722248122
Short name T463
Test name
Test status
Simulation time 1144287681 ps
CPU time 15.12 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:41:38 PM PST 24
Peak memory 248760 kb
Host smart-319cd470-4104-48c4-b6ba-969da7a4145e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3722248122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3722248122
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2409979577
Short name T439
Test name
Test status
Simulation time 4476891348 ps
CPU time 69.71 seconds
Started Mar 03 12:42:41 PM PST 24
Finished Mar 03 12:43:51 PM PST 24
Peak memory 256084 kb
Host smart-1de47f65-862f-4914-b311-527acea79afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
79577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2409979577
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2665736299
Short name T87
Test name
Test status
Simulation time 826086374 ps
CPU time 54.42 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:42:46 PM PST 24
Peak memory 255028 kb
Host smart-d1f1b6d7-333d-4aab-a6dc-f197116371f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26657
36299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2665736299
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2623390920
Short name T277
Test name
Test status
Simulation time 9942251307 ps
CPU time 1078.05 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:59:18 PM PST 24
Peak memory 282252 kb
Host smart-bbefe52d-d8a3-474e-bc39-fd8e6d3a3175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623390920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2623390920
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2473540206
Short name T352
Test name
Test status
Simulation time 74785001036 ps
CPU time 1241.06 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 01:01:58 PM PST 24
Peak memory 272000 kb
Host smart-1c91be76-5cdc-41c9-8eb3-19bf1647ef41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473540206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2473540206
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.819743073
Short name T307
Test name
Test status
Simulation time 7055735830 ps
CPU time 279.24 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:46:33 PM PST 24
Peak memory 247600 kb
Host smart-8a4c0bea-e1db-4eb2-9411-d3c87c6522b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819743073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.819743073
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.425828476
Short name T42
Test name
Test status
Simulation time 403305520 ps
CPU time 22.47 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 248756 kb
Host smart-f4ee9a63-cadb-45c1-bf1a-5f5e80b89c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42582
8476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.425828476
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4038489324
Short name T575
Test name
Test status
Simulation time 2297257112 ps
CPU time 71.95 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 248360 kb
Host smart-65e1aa97-46da-4a0e-82ed-49bef7755820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40384
89324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4038489324
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.229933709
Short name T677
Test name
Test status
Simulation time 639145847 ps
CPU time 43.67 seconds
Started Mar 03 12:41:28 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 248760 kb
Host smart-a1e0f66a-eb7a-4b59-8a7b-ec49fb3faddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22993
3709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.229933709
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3289716723
Short name T355
Test name
Test status
Simulation time 266879207 ps
CPU time 26.03 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:42:02 PM PST 24
Peak memory 255544 kb
Host smart-4ab02009-babf-4ab1-857a-b859d9340a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32897
16723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3289716723
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.125859189
Short name T535
Test name
Test status
Simulation time 50116957245 ps
CPU time 2022.22 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 01:16:25 PM PST 24
Peak memory 304752 kb
Host smart-3eaa5b80-e29f-46b6-9e82-178912025575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125859189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.125859189
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3475208967
Short name T212
Test name
Test status
Simulation time 50031449 ps
CPU time 4.4 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 12:42:47 PM PST 24
Peak memory 248456 kb
Host smart-c0e8188b-2e09-4f70-b904-151beff85779
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3475208967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3475208967
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2794408547
Short name T371
Test name
Test status
Simulation time 191642457746 ps
CPU time 3036.01 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 01:32:00 PM PST 24
Peak memory 289060 kb
Host smart-a904de7e-4b3e-41a8-8338-32ee4abf1995
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794408547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2794408547
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3867823103
Short name T705
Test name
Test status
Simulation time 476566688 ps
CPU time 18.96 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 240564 kb
Host smart-bbdc2b9f-c008-4d4b-8f80-a0af6c7f272a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3867823103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3867823103
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3836877257
Short name T71
Test name
Test status
Simulation time 3576829140 ps
CPU time 140.18 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:43:34 PM PST 24
Peak memory 256428 kb
Host smart-14a1c9a6-1b37-4b78-8b25-f47f321bd6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38368
77257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3836877257
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.387738275
Short name T527
Test name
Test status
Simulation time 553660805 ps
CPU time 35.35 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 255312 kb
Host smart-38d7dfc4-852d-4e15-844d-92945e45037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38773
8275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.387738275
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.264354118
Short name T280
Test name
Test status
Simulation time 13368041138 ps
CPU time 1367.43 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 01:04:39 PM PST 24
Peak memory 289384 kb
Host smart-6cc41e16-c077-4f8e-8af7-060b348b77e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264354118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.264354118
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2290828306
Short name T440
Test name
Test status
Simulation time 102289524434 ps
CPU time 1775.44 seconds
Started Mar 03 12:41:42 PM PST 24
Finished Mar 03 01:11:18 PM PST 24
Peak memory 282392 kb
Host smart-f42205b6-b99e-4c11-a7d7-6ec23414f3a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290828306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2290828306
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3425024147
Short name T357
Test name
Test status
Simulation time 949230764 ps
CPU time 56.05 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:42:11 PM PST 24
Peak memory 248776 kb
Host smart-b4d736fa-86ca-42ce-94ce-8ddb43a62091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
24147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3425024147
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.697488339
Short name T521
Test name
Test status
Simulation time 1234636258 ps
CPU time 18.38 seconds
Started Mar 03 12:42:41 PM PST 24
Finished Mar 03 12:43:00 PM PST 24
Peak memory 254072 kb
Host smart-3fb28127-9cf8-4a8d-87a9-d3a2ce96d5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69748
8339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.697488339
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2157379540
Short name T422
Test name
Test status
Simulation time 1245107601 ps
CPU time 42.76 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:42:19 PM PST 24
Peak memory 248056 kb
Host smart-a05b1a8f-936d-4188-8e57-5afc078783dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21573
79540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2157379540
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1017712273
Short name T372
Test name
Test status
Simulation time 3910662826 ps
CPU time 60.86 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 255596 kb
Host smart-f9a857c9-9229-4b4b-b5c5-b19ec073b73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10177
12273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1017712273
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2717113455
Short name T289
Test name
Test status
Simulation time 41720650026 ps
CPU time 2004.48 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 01:15:01 PM PST 24
Peak memory 304872 kb
Host smart-72f20643-d43d-46a5-81e9-d5f648f7ae19
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717113455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2717113455
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3954040222
Short name T69
Test name
Test status
Simulation time 76352219629 ps
CPU time 1661.48 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 01:09:07 PM PST 24
Peak memory 300460 kb
Host smart-22df6c3f-e9e9-4493-b0ab-9a0748ac2ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954040222 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3954040222
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1205416639
Short name T207
Test name
Test status
Simulation time 169279908 ps
CPU time 3.65 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:32 PM PST 24
Peak memory 248892 kb
Host smart-646bfc5f-c2f3-43b0-af49-774ce32d33a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1205416639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1205416639
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3697345174
Short name T529
Test name
Test status
Simulation time 9499710827 ps
CPU time 763.33 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:54:14 PM PST 24
Peak memory 273304 kb
Host smart-12ca7a06-a7e5-4a5b-b7e3-6d9b5b287a78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697345174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3697345174
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3562943479
Short name T350
Test name
Test status
Simulation time 3253058771 ps
CPU time 37.9 seconds
Started Mar 03 12:41:13 PM PST 24
Finished Mar 03 12:41:51 PM PST 24
Peak memory 240656 kb
Host smart-f0572a36-c16f-4381-ad11-956c0f6d0223
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3562943479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3562943479
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.201712827
Short name T226
Test name
Test status
Simulation time 22189755250 ps
CPU time 324.69 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:46:43 PM PST 24
Peak memory 256268 kb
Host smart-e018fefc-4c6f-4769-b549-078c050a3ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20171
2827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.201712827
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.604661658
Short name T638
Test name
Test status
Simulation time 918184845 ps
CPU time 47.06 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 255224 kb
Host smart-95e47df2-e00f-461c-bedd-084556cdde0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60466
1658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.604661658
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.764174455
Short name T655
Test name
Test status
Simulation time 73877564481 ps
CPU time 1709.93 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 01:09:44 PM PST 24
Peak memory 281720 kb
Host smart-3dc2b96c-dc1e-4e09-9485-66c80d17c2e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764174455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.764174455
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1761201838
Short name T406
Test name
Test status
Simulation time 37468599510 ps
CPU time 2432.84 seconds
Started Mar 03 12:41:08 PM PST 24
Finished Mar 03 01:21:42 PM PST 24
Peak memory 287224 kb
Host smart-e017d583-e2a5-4b9c-a78c-bf4da98c545f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761201838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1761201838
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2268694619
Short name T317
Test name
Test status
Simulation time 3048541747 ps
CPU time 127.79 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:43:25 PM PST 24
Peak memory 247632 kb
Host smart-c022b60f-d53c-4ae1-9b3e-cba392c9a07b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268694619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2268694619
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.803651017
Short name T400
Test name
Test status
Simulation time 1767837979 ps
CPU time 51.29 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:42:09 PM PST 24
Peak memory 248780 kb
Host smart-7e278241-0175-45c8-a0ac-84f43d294e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80365
1017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.803651017
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1835258838
Short name T657
Test name
Test status
Simulation time 3031624780 ps
CPU time 42.69 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:47 PM PST 24
Peak memory 256104 kb
Host smart-6b263a30-7cea-4370-b98a-6da0904efa71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18352
58838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1835258838
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.208318787
Short name T14
Test name
Test status
Simulation time 294579977 ps
CPU time 15.12 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 12:41:43 PM PST 24
Peak memory 274236 kb
Host smart-e2573377-d995-4fff-86a4-3a54b95f2e2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=208318787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.208318787
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2905876512
Short name T91
Test name
Test status
Simulation time 110568111 ps
CPU time 12.58 seconds
Started Mar 03 12:41:04 PM PST 24
Finished Mar 03 12:41:17 PM PST 24
Peak memory 255220 kb
Host smart-0c3aa267-23f2-47e4-afc7-c88036eb4ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29058
76512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2905876512
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1899831215
Short name T351
Test name
Test status
Simulation time 2536564524 ps
CPU time 40.03 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:58 PM PST 24
Peak memory 248824 kb
Host smart-6b4a7fb4-78ad-47cb-89b1-63383111c6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18998
31215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1899831215
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.217104282
Short name T522
Test name
Test status
Simulation time 19608045141 ps
CPU time 1154.09 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 01:00:56 PM PST 24
Peak memory 273276 kb
Host smart-f16bc33f-c294-40f0-928c-3e5700774048
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217104282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.217104282
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1752440339
Short name T493
Test name
Test status
Simulation time 4616225580 ps
CPU time 121.17 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:43:24 PM PST 24
Peak memory 256544 kb
Host smart-86181481-6809-4764-acd9-6942665536e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17524
40339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1752440339
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3170158743
Short name T443
Test name
Test status
Simulation time 127233352 ps
CPU time 10.65 seconds
Started Mar 03 12:42:41 PM PST 24
Finished Mar 03 12:42:52 PM PST 24
Peak memory 251592 kb
Host smart-11ab8f14-a7d1-48ff-ab4b-ca02dd3ab7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31701
58743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3170158743
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2832854004
Short name T432
Test name
Test status
Simulation time 40663360436 ps
CPU time 2413.22 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 01:22:56 PM PST 24
Peak memory 288640 kb
Host smart-812e7229-736a-4cc8-a444-f68c3d9db629
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832854004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2832854004
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1399945454
Short name T301
Test name
Test status
Simulation time 4023701544 ps
CPU time 171.74 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:44:38 PM PST 24
Peak memory 247504 kb
Host smart-ece7283c-f158-46d6-bbf3-df2b81c38480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399945454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1399945454
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.4069063005
Short name T96
Test name
Test status
Simulation time 342871007 ps
CPU time 28.83 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 254712 kb
Host smart-267913bd-4ae1-43c7-98df-232045c05460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40690
63005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.4069063005
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4292914038
Short name T501
Test name
Test status
Simulation time 2402875177 ps
CPU time 33.84 seconds
Started Mar 03 12:42:33 PM PST 24
Finished Mar 03 12:43:08 PM PST 24
Peak memory 253596 kb
Host smart-d361b5fd-11bc-4968-b7aa-4660e0e499c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42929
14038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4292914038
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3454399627
Short name T667
Test name
Test status
Simulation time 661456155 ps
CPU time 45.74 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 248976 kb
Host smart-e17dc45b-63e6-4e7b-abb9-6d88b99d044b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
99627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3454399627
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2118782984
Short name T117
Test name
Test status
Simulation time 86495633194 ps
CPU time 1255.81 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 01:02:28 PM PST 24
Peak memory 289196 kb
Host smart-d13bcf50-d961-4399-b55b-02f18163419e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118782984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2118782984
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1952197358
Short name T574
Test name
Test status
Simulation time 3288757818 ps
CPU time 91.78 seconds
Started Mar 03 12:41:44 PM PST 24
Finished Mar 03 12:43:16 PM PST 24
Peak memory 255744 kb
Host smart-0b34cc4b-a06b-4289-8064-c0ef01eefe48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19521
97358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1952197358
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3339927250
Short name T670
Test name
Test status
Simulation time 814238759 ps
CPU time 34.47 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:54 PM PST 24
Peak memory 255036 kb
Host smart-74947ca7-b3f3-4fb1-a9f0-f59c2a217790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33399
27250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3339927250
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2717941829
Short name T623
Test name
Test status
Simulation time 34990634909 ps
CPU time 848.45 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:55:59 PM PST 24
Peak memory 265212 kb
Host smart-a57b1543-cd52-4e16-8bfe-5b352c45f9af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717941829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2717941829
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1128936703
Short name T683
Test name
Test status
Simulation time 18408194837 ps
CPU time 407.28 seconds
Started Mar 03 12:41:24 PM PST 24
Finished Mar 03 12:48:12 PM PST 24
Peak memory 247488 kb
Host smart-b4ee8431-7052-4431-bb8b-eaad0c886790
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128936703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1128936703
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3811576694
Short name T492
Test name
Test status
Simulation time 752544857 ps
CPU time 14.74 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 248760 kb
Host smart-58670b69-d2c0-4faa-99c5-26a41febd87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
76694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3811576694
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3639624469
Short name T403
Test name
Test status
Simulation time 4788759878 ps
CPU time 68.37 seconds
Started Mar 03 12:42:42 PM PST 24
Finished Mar 03 12:43:51 PM PST 24
Peak memory 255628 kb
Host smart-b53dd6e1-d0bb-4cdd-a48e-25b20413513a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36396
24469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3639624469
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2816892335
Short name T260
Test name
Test status
Simulation time 458004008 ps
CPU time 29.21 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:20 PM PST 24
Peak memory 247596 kb
Host smart-79d4b7d7-20df-49d7-a15d-fb9cad00711b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28168
92335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2816892335
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3346363624
Short name T591
Test name
Test status
Simulation time 2532972779 ps
CPU time 40.13 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 249040 kb
Host smart-6c997bf1-545d-497f-9ccd-e2c5f6c45725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
63624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3346363624
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.280283770
Short name T607
Test name
Test status
Simulation time 19125242553 ps
CPU time 932.72 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:56:57 PM PST 24
Peak memory 273380 kb
Host smart-cec1c419-9421-4d18-a0d0-3812e8399390
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280283770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.280283770
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2289332554
Short name T26
Test name
Test status
Simulation time 129513703852 ps
CPU time 2261.74 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 01:19:33 PM PST 24
Peak memory 289064 kb
Host smart-9ffed13b-9d89-4706-94bc-d64d7987506d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289332554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2289332554
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2658244945
Short name T523
Test name
Test status
Simulation time 4370853179 ps
CPU time 259.77 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:46:14 PM PST 24
Peak memory 250900 kb
Host smart-c8636361-aff4-47d3-b900-23e88add19b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26582
44945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2658244945
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.1791514271
Short name T695
Test name
Test status
Simulation time 28077207 ps
CPU time 4.3 seconds
Started Mar 03 12:41:40 PM PST 24
Finished Mar 03 12:41:45 PM PST 24
Peak memory 250876 kb
Host smart-36cb808f-5c9b-41d0-bea3-f75adeee4161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17915
14271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.1791514271
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.296000108
Short name T330
Test name
Test status
Simulation time 28383638508 ps
CPU time 1598.83 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 01:08:19 PM PST 24
Peak memory 271632 kb
Host smart-321439e4-a93e-4da9-9958-bc8525999c09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296000108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.296000108
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.467601038
Short name T388
Test name
Test status
Simulation time 10415297274 ps
CPU time 582.99 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:51:29 PM PST 24
Peak memory 272220 kb
Host smart-79e6e060-a1fd-4afe-a3e9-d05e56375e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467601038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.467601038
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.196607684
Short name T297
Test name
Test status
Simulation time 26653685773 ps
CPU time 285.74 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:46:35 PM PST 24
Peak memory 247648 kb
Host smart-a723bc99-9125-4acc-b63f-dfeffea041a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196607684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.196607684
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2666216298
Short name T644
Test name
Test status
Simulation time 701194857 ps
CPU time 17.89 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 248772 kb
Host smart-a9184df1-b870-4740-8267-f89312553f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26662
16298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2666216298
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2274650148
Short name T373
Test name
Test status
Simulation time 82907016 ps
CPU time 9.34 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:41:58 PM PST 24
Peak memory 255244 kb
Host smart-6fc6bf58-17a3-4a3a-acb5-bf23c6f6566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22746
50148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2274650148
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3245528361
Short name T374
Test name
Test status
Simulation time 170281809 ps
CPU time 9.88 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:41:34 PM PST 24
Peak memory 254420 kb
Host smart-5f1a5903-a6c8-43d7-8022-c3ea353d1d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
28361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3245528361
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4111131616
Short name T615
Test name
Test status
Simulation time 329579768 ps
CPU time 31.41 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:21 PM PST 24
Peak memory 248776 kb
Host smart-a0ff6984-1a97-4a10-9e31-e9030226a0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41111
31616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4111131616
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3891624690
Short name T112
Test name
Test status
Simulation time 6061286076 ps
CPU time 137.73 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:43:56 PM PST 24
Peak memory 250228 kb
Host smart-95f58e53-9fe8-423f-ad79-474861f128f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891624690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3891624690
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.2912228617
Short name T407
Test name
Test status
Simulation time 197466411505 ps
CPU time 4917.7 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 02:03:39 PM PST 24
Peak memory 301172 kb
Host smart-f02a2f9d-578e-41ec-b876-2214afe7c256
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912228617 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.2912228617
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1981166505
Short name T423
Test name
Test status
Simulation time 32404585333 ps
CPU time 839.06 seconds
Started Mar 03 12:41:41 PM PST 24
Finished Mar 03 12:55:40 PM PST 24
Peak memory 289448 kb
Host smart-3123aaf7-85b9-4765-b42d-97d3387af857
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981166505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1981166505
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2996155188
Short name T490
Test name
Test status
Simulation time 1512520478 ps
CPU time 41.31 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 256032 kb
Host smart-28c5987e-d7a6-4aa1-b923-dfeab4145c18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29961
55188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2996155188
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2846486889
Short name T396
Test name
Test status
Simulation time 41028643 ps
CPU time 5.11 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:41:52 PM PST 24
Peak memory 250600 kb
Host smart-5f93f8ab-5a45-4d18-a3b9-37a4ec11dea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28464
86889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2846486889
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3344368366
Short name T454
Test name
Test status
Simulation time 16922367421 ps
CPU time 1560.88 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 01:07:29 PM PST 24
Peak memory 289364 kb
Host smart-009d7783-e42c-48d6-94a5-a150ba29d528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344368366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3344368366
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3576437560
Short name T270
Test name
Test status
Simulation time 144536076631 ps
CPU time 2384.38 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 01:21:24 PM PST 24
Peak memory 286604 kb
Host smart-499983d3-90e0-4eb8-a707-bccec805381d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576437560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3576437560
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3279442522
Short name T305
Test name
Test status
Simulation time 5391181711 ps
CPU time 214.9 seconds
Started Mar 03 12:41:38 PM PST 24
Finished Mar 03 12:45:13 PM PST 24
Peak memory 247636 kb
Host smart-e0ea11ba-b75f-40a9-ac64-b86f2dc74fe5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279442522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3279442522
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.383343451
Short name T391
Test name
Test status
Simulation time 3324687936 ps
CPU time 50.69 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:42:42 PM PST 24
Peak memory 248980 kb
Host smart-9306ef50-7ada-4d14-ba72-beccda290e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38334
3451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.383343451
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1503973977
Short name T126
Test name
Test status
Simulation time 617356583 ps
CPU time 36.69 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 255552 kb
Host smart-9223d0c5-c6b2-4e2f-bf2a-f7a803abb0d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15039
73977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1503973977
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2593590876
Short name T254
Test name
Test status
Simulation time 336948035 ps
CPU time 22.58 seconds
Started Mar 03 12:41:40 PM PST 24
Finished Mar 03 12:42:03 PM PST 24
Peak memory 255192 kb
Host smart-c50ea5f6-e30c-410b-b0e3-dcac06302d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25935
90876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2593590876
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3452673323
Short name T365
Test name
Test status
Simulation time 663018072 ps
CPU time 46.33 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 12:42:46 PM PST 24
Peak memory 248816 kb
Host smart-29fa066c-92be-40df-a41f-ab3d13bb6a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34526
73323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3452673323
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.4028046868
Short name T118
Test name
Test status
Simulation time 33561691980 ps
CPU time 1459.24 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 01:06:13 PM PST 24
Peak memory 289152 kb
Host smart-2b6c5e1c-c2a3-4d78-90b1-48bb835262e5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028046868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.4028046868
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3978261565
Short name T576
Test name
Test status
Simulation time 157148441709 ps
CPU time 2746.7 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 01:27:35 PM PST 24
Peak memory 283776 kb
Host smart-75cb40d4-060e-462b-a029-38110c319183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978261565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3978261565
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3227134575
Short name T669
Test name
Test status
Simulation time 725726469 ps
CPU time 55.61 seconds
Started Mar 03 12:41:42 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 256260 kb
Host smart-be573151-8e9e-45f3-8997-f772ff62da44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32271
34575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3227134575
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3765722398
Short name T450
Test name
Test status
Simulation time 343283955 ps
CPU time 6.15 seconds
Started Mar 03 12:41:34 PM PST 24
Finished Mar 03 12:41:41 PM PST 24
Peak memory 250364 kb
Host smart-cfc89805-2582-4779-a87d-ee7db2eece39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
22398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3765722398
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2744711373
Short name T327
Test name
Test status
Simulation time 36469328561 ps
CPU time 2266.77 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 01:19:37 PM PST 24
Peak memory 286592 kb
Host smart-b11253fe-7ab9-4875-bbd7-d79ae20d2c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744711373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2744711373
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2995703506
Short name T74
Test name
Test status
Simulation time 80299408366 ps
CPU time 1559.3 seconds
Started Mar 03 12:41:47 PM PST 24
Finished Mar 03 01:07:47 PM PST 24
Peak memory 268220 kb
Host smart-80c3ef56-df4f-4727-af88-9d38c795eadf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995703506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2995703506
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4023769793
Short name T554
Test name
Test status
Simulation time 151527341211 ps
CPU time 428.28 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 12:48:31 PM PST 24
Peak memory 247576 kb
Host smart-4b37f2a6-8f53-48f5-a292-ea1ecd29b05e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023769793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4023769793
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2966988458
Short name T56
Test name
Test status
Simulation time 711728354 ps
CPU time 16.96 seconds
Started Mar 03 12:41:42 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 248756 kb
Host smart-28b5b7e6-97ef-4747-a4ff-f93528815a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29669
88458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2966988458
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1954742432
Short name T542
Test name
Test status
Simulation time 1693813338 ps
CPU time 28.98 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 255536 kb
Host smart-ecfcea29-44a9-4a81-9de5-a0121c541f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
42432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1954742432
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2152747283
Short name T276
Test name
Test status
Simulation time 3760476006 ps
CPU time 54.89 seconds
Started Mar 03 12:41:26 PM PST 24
Finished Mar 03 12:42:21 PM PST 24
Peak memory 247528 kb
Host smart-9da6f715-4958-4ea0-b5de-d79e0fe8f72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21527
47283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2152747283
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1941174887
Short name T636
Test name
Test status
Simulation time 273925198 ps
CPU time 18.89 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 248776 kb
Host smart-aa05ea9d-745f-41a3-83e5-aa6c59e25f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19411
74887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1941174887
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1741512363
Short name T471
Test name
Test status
Simulation time 27559829689 ps
CPU time 1429.39 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 01:05:44 PM PST 24
Peak memory 289412 kb
Host smart-ac139e4a-0b4e-408e-9178-8d209afb1fbd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741512363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1741512363
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.4066630458
Short name T290
Test name
Test status
Simulation time 63577676206 ps
CPU time 2995.64 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 01:31:41 PM PST 24
Peak memory 318924 kb
Host smart-dd0d3de7-9a29-4e8c-aa77-00b7268bc6d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066630458 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.4066630458
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.802268032
Short name T601
Test name
Test status
Simulation time 18600301752 ps
CPU time 759.62 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:54:31 PM PST 24
Peak memory 273296 kb
Host smart-da78ff39-327c-4590-9913-d910611637c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802268032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.802268032
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3256575306
Short name T18
Test name
Test status
Simulation time 19386351172 ps
CPU time 272.48 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:46:24 PM PST 24
Peak memory 256608 kb
Host smart-72998695-638f-4f86-8246-72b7bdd2b4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32565
75306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3256575306
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3971979630
Short name T452
Test name
Test status
Simulation time 1270052980 ps
CPU time 22.55 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 248436 kb
Host smart-85e9cb93-1ead-459c-9562-89c39a871699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39719
79630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3971979630
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.1262236903
Short name T326
Test name
Test status
Simulation time 418824348152 ps
CPU time 1949.07 seconds
Started Mar 03 12:41:47 PM PST 24
Finished Mar 03 01:14:16 PM PST 24
Peak memory 272580 kb
Host smart-bfd3b083-a901-4105-bfc2-bea252d729ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262236903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.1262236903
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.619724841
Short name T107
Test name
Test status
Simulation time 23326862553 ps
CPU time 1235.29 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 01:02:22 PM PST 24
Peak memory 288584 kb
Host smart-5b5992a4-1f85-4399-8d2e-2fa34e658532
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619724841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.619724841
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1576696022
Short name T430
Test name
Test status
Simulation time 2264563995 ps
CPU time 85.74 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:43:17 PM PST 24
Peak memory 246624 kb
Host smart-7cdedbfc-f97c-4e98-8c3a-01e5fbad7cd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576696022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1576696022
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3248998040
Short name T356
Test name
Test status
Simulation time 440842204 ps
CPU time 9.5 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:41:40 PM PST 24
Peak memory 248740 kb
Host smart-7ae10cb1-85bc-477c-82b1-a49d1ae5ce71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32489
98040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3248998040
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.794692899
Short name T460
Test name
Test status
Simulation time 41407250 ps
CPU time 6.09 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:41:57 PM PST 24
Peak memory 252340 kb
Host smart-74080fdb-4df4-44cb-bc41-aa5219f0e199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79469
2899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.794692899
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4098534195
Short name T7
Test name
Test status
Simulation time 138210280 ps
CPU time 9.74 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 253444 kb
Host smart-de44da1d-fb3d-431a-8184-fcb74b156b1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
34195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4098534195
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3574470964
Short name T617
Test name
Test status
Simulation time 644241666 ps
CPU time 20.17 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:42:11 PM PST 24
Peak memory 255512 kb
Host smart-76db1f29-b5fb-41b8-8e51-4924fcaf7a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35744
70964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3574470964
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4160281397
Short name T274
Test name
Test status
Simulation time 202197250963 ps
CPU time 4294.56 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 01:53:23 PM PST 24
Peak memory 322624 kb
Host smart-1d6534e8-16eb-4836-a9e6-1d2f368af560
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160281397 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4160281397
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3919207319
Short name T88
Test name
Test status
Simulation time 115702668470 ps
CPU time 3270.52 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 01:36:01 PM PST 24
Peak memory 289052 kb
Host smart-87cb857e-0602-4305-9b16-613af123bfc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919207319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3919207319
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1754168387
Short name T275
Test name
Test status
Simulation time 11184464397 ps
CPU time 205.83 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:45:20 PM PST 24
Peak memory 256260 kb
Host smart-bd6ab362-2ca4-4bc7-a28e-36b9c51f9234
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17541
68387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1754168387
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3880294448
Short name T476
Test name
Test status
Simulation time 288574094 ps
CPU time 21.69 seconds
Started Mar 03 12:41:43 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 254468 kb
Host smart-e9763d54-cf4e-4cd5-9b37-6d1dacb9fcf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38802
94448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3880294448
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3493577857
Short name T192
Test name
Test status
Simulation time 49192526560 ps
CPU time 927.51 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:57:20 PM PST 24
Peak memory 273412 kb
Host smart-518a3841-e65d-41d0-a08d-3081ebc03300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493577857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3493577857
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2854690093
Short name T700
Test name
Test status
Simulation time 7677778438 ps
CPU time 318.72 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:47:11 PM PST 24
Peak memory 247636 kb
Host smart-7c079f68-b5f5-41b5-9428-48944ff382fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854690093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2854690093
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.469958958
Short name T50
Test name
Test status
Simulation time 3914471027 ps
CPU time 67.44 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:42:59 PM PST 24
Peak memory 248896 kb
Host smart-3d356239-d98c-4a14-a4ba-8b8962637905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46995
8958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.469958958
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3304534634
Short name T569
Test name
Test status
Simulation time 426725747 ps
CPU time 27.46 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:25 PM PST 24
Peak memory 253420 kb
Host smart-d1d716cd-9010-47ff-907a-867d3313e6bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33045
34634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3304534634
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1159822364
Short name T265
Test name
Test status
Simulation time 2082431417 ps
CPU time 34.26 seconds
Started Mar 03 12:41:47 PM PST 24
Finished Mar 03 12:42:22 PM PST 24
Peak memory 255788 kb
Host smart-29760a4a-4091-4e08-85a7-74ba7cbcfb5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11598
22364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1159822364
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1796754086
Short name T72
Test name
Test status
Simulation time 914997130 ps
CPU time 52.86 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 255584 kb
Host smart-d313ba81-ef03-464f-913b-db74691a1f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17967
54086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1796754086
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2114013426
Short name T434
Test name
Test status
Simulation time 20709472597 ps
CPU time 1117.77 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 01:00:29 PM PST 24
Peak memory 273492 kb
Host smart-4faf5b40-8da9-41bd-a835-acb4a3042535
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114013426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2114013426
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.366942326
Short name T102
Test name
Test status
Simulation time 16336788808 ps
CPU time 1504.85 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 01:06:57 PM PST 24
Peak memory 289208 kb
Host smart-f5090a28-9ba9-4ebf-bf80-11851485b924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366942326 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.366942326
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2115573041
Short name T552
Test name
Test status
Simulation time 18140391270 ps
CPU time 1239.63 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 01:02:25 PM PST 24
Peak memory 265216 kb
Host smart-bbab778b-d876-480f-a5db-5e3c3a5cbd24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115573041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2115573041
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.2935413484
Short name T386
Test name
Test status
Simulation time 1357223242 ps
CPU time 57.86 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 256352 kb
Host smart-843ca0c7-99bb-40c5-a784-160ea87cfd6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29354
13484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.2935413484
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2320523571
Short name T264
Test name
Test status
Simulation time 3328905959 ps
CPU time 37.53 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 255236 kb
Host smart-da470475-8237-4347-a8e0-03c753202cd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
23571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2320523571
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3467095426
Short name T358
Test name
Test status
Simulation time 158326324740 ps
CPU time 1134.5 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 01:00:51 PM PST 24
Peak memory 273256 kb
Host smart-b2c5ec5f-b0af-46e4-8a4c-a4252bcc7457
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467095426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3467095426
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1675992566
Short name T519
Test name
Test status
Simulation time 38197602722 ps
CPU time 474.08 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:49:43 PM PST 24
Peak memory 247484 kb
Host smart-6f1eb293-1bcb-4d0e-bf91-3e33841c5989
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675992566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1675992566
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1046026591
Short name T685
Test name
Test status
Simulation time 2567600302 ps
CPU time 42.79 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 248828 kb
Host smart-2c7c1aa3-d934-472e-b90e-56000afafd34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10460
26591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1046026591
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3399499219
Short name T97
Test name
Test status
Simulation time 79279714 ps
CPU time 5.29 seconds
Started Mar 03 12:41:46 PM PST 24
Finished Mar 03 12:41:52 PM PST 24
Peak memory 250608 kb
Host smart-96677ee5-7333-4f97-ab0a-1433cd9ec1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33994
99219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3399499219
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3360025210
Short name T262
Test name
Test status
Simulation time 480514162 ps
CPU time 22.04 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 255224 kb
Host smart-b2c470c9-9ecd-4189-b46d-45199adba44e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33600
25210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3360025210
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3475223223
Short name T516
Test name
Test status
Simulation time 1255039854 ps
CPU time 14.31 seconds
Started Mar 03 12:41:39 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 248828 kb
Host smart-b30d8659-9014-4973-ab3e-5668eb4a7450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
23223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3475223223
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1974416049
Short name T482
Test name
Test status
Simulation time 141526323778 ps
CPU time 1753.19 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 01:11:08 PM PST 24
Peak memory 297732 kb
Host smart-e855305e-7482-460a-9dfd-7efa89008574
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974416049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1974416049
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3030421278
Short name T597
Test name
Test status
Simulation time 17335477628 ps
CPU time 1488.37 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 01:06:48 PM PST 24
Peak memory 289072 kb
Host smart-7bd81680-79cf-4d5a-be37-f23b0eae1ee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030421278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3030421278
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2621593923
Short name T421
Test name
Test status
Simulation time 3371177621 ps
CPU time 202.3 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 12:45:00 PM PST 24
Peak memory 256304 kb
Host smart-85fe1d46-22a7-48af-8731-41ae8993e8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26215
93923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2621593923
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2502132165
Short name T123
Test name
Test status
Simulation time 1702865364 ps
CPU time 34.91 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:25 PM PST 24
Peak memory 248292 kb
Host smart-9cfe5c51-492e-4007-b683-463ebad019b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25021
32165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2502132165
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1584309841
Short name T328
Test name
Test status
Simulation time 62448889441 ps
CPU time 779.99 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:54:49 PM PST 24
Peak memory 272392 kb
Host smart-13ece2cb-a257-4004-a45d-0a782dc7e826
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584309841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1584309841
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2718555247
Short name T116
Test name
Test status
Simulation time 16027560896 ps
CPU time 1226.19 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 01:02:19 PM PST 24
Peak memory 286548 kb
Host smart-8a1f6f93-62e6-45c5-b47d-5c415ee77793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718555247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2718555247
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2925111587
Short name T310
Test name
Test status
Simulation time 19971203904 ps
CPU time 417.19 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:48:57 PM PST 24
Peak memory 247728 kb
Host smart-3dea736e-18ed-4ed3-b450-a2f622c1c4a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925111587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2925111587
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2164622454
Short name T231
Test name
Test status
Simulation time 110634472 ps
CPU time 6.74 seconds
Started Mar 03 12:41:47 PM PST 24
Finished Mar 03 12:41:55 PM PST 24
Peak memory 256836 kb
Host smart-e924cfb3-ae03-4185-851b-5ca040c75f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21646
22454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2164622454
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3720496857
Short name T451
Test name
Test status
Simulation time 2636467653 ps
CPU time 42.86 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:41 PM PST 24
Peak memory 255372 kb
Host smart-54bf0f97-2cb3-4f35-8fd5-c987cfadf6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
96857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3720496857
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2145488116
Short name T532
Test name
Test status
Simulation time 681714941 ps
CPU time 18.02 seconds
Started Mar 03 12:41:47 PM PST 24
Finished Mar 03 12:42:05 PM PST 24
Peak memory 249232 kb
Host smart-c86e17d8-f8ec-4f34-b0fa-053eca217c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21454
88116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2145488116
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1817158230
Short name T19
Test name
Test status
Simulation time 860753071 ps
CPU time 20.5 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:09 PM PST 24
Peak memory 255192 kb
Host smart-5a1fc7a8-fead-40c6-81bb-82d43c57db1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18171
58230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1817158230
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.779037301
Short name T679
Test name
Test status
Simulation time 2849121524 ps
CPU time 47.87 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 255760 kb
Host smart-c09043dd-7358-4d4c-87df-6f90a4fc2ca1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779037301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.779037301
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1749435613
Short name T251
Test name
Test status
Simulation time 695496420716 ps
CPU time 5028.48 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 02:05:41 PM PST 24
Peak memory 330840 kb
Host smart-e80ae28d-21c8-4ff4-bcee-52dc403746e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749435613 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1749435613
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1534436559
Short name T528
Test name
Test status
Simulation time 19907713847 ps
CPU time 1104.13 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 01:00:16 PM PST 24
Peak memory 281620 kb
Host smart-bbdd7257-3add-4365-9372-0cd1315f7437
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534436559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1534436559
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2300680465
Short name T188
Test name
Test status
Simulation time 10904052255 ps
CPU time 204.88 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:45:16 PM PST 24
Peak memory 256340 kb
Host smart-268d14f7-cec5-490f-a106-d88b66d33eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23006
80465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2300680465
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1319864730
Short name T89
Test name
Test status
Simulation time 3328741545 ps
CPU time 35.83 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:24 PM PST 24
Peak memory 255216 kb
Host smart-47f52541-cecc-40c7-b083-d62eda143e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13198
64730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1319864730
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3571005816
Short name T647
Test name
Test status
Simulation time 62902227695 ps
CPU time 1870.51 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 01:13:00 PM PST 24
Peak memory 289268 kb
Host smart-e84058cd-8391-421f-9ae1-f1959cf4313a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571005816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3571005816
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1140469823
Short name T189
Test name
Test status
Simulation time 144129397098 ps
CPU time 2216.1 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 01:18:47 PM PST 24
Peak memory 289380 kb
Host smart-214c638d-21fc-4d90-a90c-7f8120d544ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140469823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1140469823
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2288863143
Short name T11
Test name
Test status
Simulation time 18942526072 ps
CPU time 414.89 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:48:44 PM PST 24
Peak memory 246620 kb
Host smart-820b3ba2-eae4-4a76-84bc-91e633d408d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288863143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2288863143
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2745353562
Short name T539
Test name
Test status
Simulation time 499292161 ps
CPU time 23.14 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 255520 kb
Host smart-8d043664-2b70-4998-8733-e0c2c2617718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27453
53562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2745353562
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.117845010
Short name T111
Test name
Test status
Simulation time 355767423 ps
CPU time 26.83 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:42:18 PM PST 24
Peak memory 254992 kb
Host smart-ecee56d3-99a6-4b27-9a46-fb534424a6dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11784
5010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.117845010
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.99342280
Short name T399
Test name
Test status
Simulation time 223022800 ps
CPU time 26.89 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 255392 kb
Host smart-4031d45e-e1a4-4c15-8c28-0071b0228a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99342
280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.99342280
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2818253982
Short name T526
Test name
Test status
Simulation time 1548010579 ps
CPU time 35.8 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 248676 kb
Host smart-6861655d-a8ac-4afa-b274-f931d0f08a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28182
53982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2818253982
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2356383294
Short name T201
Test name
Test status
Simulation time 176088152 ps
CPU time 4.06 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 248940 kb
Host smart-2fd31879-67b8-4024-a2c7-8a325d4b8a37
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2356383294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2356383294
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2434961747
Short name T557
Test name
Test status
Simulation time 28513067689 ps
CPU time 981.43 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:57:43 PM PST 24
Peak memory 267232 kb
Host smart-193bfe2c-7864-4219-a240-0c96ef9ea506
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434961747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2434961747
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1859122981
Short name T559
Test name
Test status
Simulation time 1156575769 ps
CPU time 27.43 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:44 PM PST 24
Peak memory 240636 kb
Host smart-03ac3fbb-c975-4933-a4d3-c0873899f535
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1859122981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1859122981
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.201960177
Short name T483
Test name
Test status
Simulation time 12218654662 ps
CPU time 183.52 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:44:21 PM PST 24
Peak memory 256600 kb
Host smart-08120629-00ec-4bc8-b646-e757c3e3b820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20196
0177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.201960177
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.998471644
Short name T488
Test name
Test status
Simulation time 130960863 ps
CPU time 10.63 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 251380 kb
Host smart-6dfaea2c-b2c2-4915-b094-ecefa2b0ec5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99847
1644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.998471644
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.167847578
Short name T658
Test name
Test status
Simulation time 38950317666 ps
CPU time 1978.76 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 01:14:11 PM PST 24
Peak memory 283252 kb
Host smart-84dea099-0dec-4e14-ae64-36848e3f4933
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167847578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.167847578
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2922602870
Short name T442
Test name
Test status
Simulation time 158121435863 ps
CPU time 2389.44 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:21:05 PM PST 24
Peak memory 282136 kb
Host smart-1598d00f-4c9f-4d3e-9641-c35a433bd2c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922602870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2922602870
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3213747585
Short name T306
Test name
Test status
Simulation time 7809707184 ps
CPU time 340.77 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:47:03 PM PST 24
Peak memory 247652 kb
Host smart-23d8c37d-f01b-46b6-b97a-9df1452c08a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213747585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3213747585
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.269403294
Short name T73
Test name
Test status
Simulation time 160125263 ps
CPU time 3.53 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 240588 kb
Host smart-001f9694-5ee8-49a7-a4b9-22914a350e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26940
3294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.269403294
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2238516868
Short name T503
Test name
Test status
Simulation time 767658791 ps
CPU time 43.88 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:49 PM PST 24
Peak memory 248404 kb
Host smart-804a89b6-0a40-413c-9e81-e39249d0afbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
16868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2238516868
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3569035778
Short name T32
Test name
Test status
Simulation time 683780464 ps
CPU time 20.81 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:38 PM PST 24
Peak memory 270240 kb
Host smart-c8bb23f8-4e8c-41c4-90bc-e7776786b018
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3569035778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3569035778
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1919489272
Short name T611
Test name
Test status
Simulation time 479205963 ps
CPU time 6.76 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:25 PM PST 24
Peak memory 249056 kb
Host smart-bfa35e14-9c5a-467a-8689-1d7d5bff60d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19194
89272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1919489272
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2679034296
Short name T456
Test name
Test status
Simulation time 194528672 ps
CPU time 22.94 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 255400 kb
Host smart-5f1999d9-979f-42ea-a197-c4b60f536111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26790
34296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2679034296
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.68973877
Short name T244
Test name
Test status
Simulation time 238551255594 ps
CPU time 7123.17 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 02:40:02 PM PST 24
Peak memory 350728 kb
Host smart-31d6d751-87b3-4553-9f17-dc376e14cc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68973877 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.68973877
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3138219389
Short name T461
Test name
Test status
Simulation time 32687096863 ps
CPU time 699.62 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:53:30 PM PST 24
Peak memory 273044 kb
Host smart-711058ae-d035-4ae3-be60-52924976f1ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138219389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3138219389
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.575683067
Short name T402
Test name
Test status
Simulation time 24770439052 ps
CPU time 286.25 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:46:38 PM PST 24
Peak memory 256472 kb
Host smart-21c3e875-42ce-4aa2-9638-c1e0397fe735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57568
3067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.575683067
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2565485198
Short name T613
Test name
Test status
Simulation time 687511756 ps
CPU time 27.77 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:16 PM PST 24
Peak memory 254484 kb
Host smart-fb985aa7-d187-435c-bcce-8c305f02ad7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
85198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2565485198
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1267358399
Short name T665
Test name
Test status
Simulation time 23382413875 ps
CPU time 1430.86 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 01:05:43 PM PST 24
Peak memory 273340 kb
Host smart-e395af7b-3e82-47b5-91d7-51c3455aac12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267358399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1267358399
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3484634962
Short name T66
Test name
Test status
Simulation time 42945317442 ps
CPU time 2614.71 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 01:25:31 PM PST 24
Peak memory 283788 kb
Host smart-49db5542-ec19-4d0b-a79f-90dba7c04a4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484634962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3484634962
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2639750406
Short name T303
Test name
Test status
Simulation time 11178909239 ps
CPU time 150.09 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:44:28 PM PST 24
Peak memory 247736 kb
Host smart-c55c4d77-f80a-498b-800d-d96e0df6c662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639750406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2639750406
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2014347122
Short name T413
Test name
Test status
Simulation time 284642021 ps
CPU time 23.91 seconds
Started Mar 03 12:41:48 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 248684 kb
Host smart-cb6647ba-0df5-4a47-8d3d-24d22e4bb5f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20143
47122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2014347122
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1961901515
Short name T30
Test name
Test status
Simulation time 888348113 ps
CPU time 59.82 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:42:54 PM PST 24
Peak memory 255532 kb
Host smart-9bc73750-5388-49e6-9a22-0dc0985b623c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19619
01515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1961901515
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1716692547
Short name T498
Test name
Test status
Simulation time 2576366526 ps
CPU time 40.97 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 255620 kb
Host smart-ea7cb1f4-bd8b-4b4b-b34a-4d896d2373b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17166
92547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1716692547
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2749333073
Short name T457
Test name
Test status
Simulation time 333207593343 ps
CPU time 2253.66 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 01:19:25 PM PST 24
Peak memory 269564 kb
Host smart-5b02e3b4-6d51-46cb-81d1-6f125ca32c69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749333073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2749333073
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3600575430
Short name T606
Test name
Test status
Simulation time 24953213832 ps
CPU time 328.31 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:47:28 PM PST 24
Peak memory 256168 kb
Host smart-8ed44800-df68-4532-ae79-9b6e1766cafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36005
75430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3600575430
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.381807367
Short name T65
Test name
Test status
Simulation time 134159404 ps
CPU time 9.1 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:07 PM PST 24
Peak memory 249312 kb
Host smart-6843e317-735d-4f21-b0b1-f8a7226507ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
7367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.381807367
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2919380175
Short name T95
Test name
Test status
Simulation time 127539319835 ps
CPU time 1106.14 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 01:00:26 PM PST 24
Peak memory 265224 kb
Host smart-5659752c-0a07-4e42-97bb-81c8ef377fdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919380175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2919380175
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2623092877
Short name T646
Test name
Test status
Simulation time 9019689158 ps
CPU time 775.15 seconds
Started Mar 03 12:41:51 PM PST 24
Finished Mar 03 12:54:47 PM PST 24
Peak memory 273420 kb
Host smart-c726a565-7c5e-4a43-83b3-854a427750d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623092877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2623092877
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3795781294
Short name T690
Test name
Test status
Simulation time 3713413848 ps
CPU time 163.24 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:44:37 PM PST 24
Peak memory 247488 kb
Host smart-2b96571d-edbd-4e58-80e4-f5046a3c3481
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795781294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3795781294
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3650932402
Short name T515
Test name
Test status
Simulation time 313494614 ps
CPU time 31.15 seconds
Started Mar 03 12:41:59 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 256956 kb
Host smart-42299ff4-0ea4-4b82-b983-d54c4aadb93b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
32402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3650932402
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4211288825
Short name T43
Test name
Test status
Simulation time 537571539 ps
CPU time 15.66 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:42:16 PM PST 24
Peak memory 254524 kb
Host smart-dd625e9e-5714-4be5-80b6-c84e530c6bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42112
88825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4211288825
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1843425831
Short name T122
Test name
Test status
Simulation time 255275304 ps
CPU time 8.78 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 253692 kb
Host smart-d5e437d1-6d7c-4e14-952b-77b7620f32dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18434
25831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1843425831
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4077406713
Short name T504
Test name
Test status
Simulation time 575435781 ps
CPU time 36.66 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 248744 kb
Host smart-eedd386b-5188-4657-8e75-dc28c281d1d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
06713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4077406713
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1784200570
Short name T577
Test name
Test status
Simulation time 56780802389 ps
CPU time 3177.49 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 01:34:49 PM PST 24
Peak memory 289520 kb
Host smart-9d79033d-6843-436d-8856-20bc6aa43f1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784200570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1784200570
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.109668645
Short name T77
Test name
Test status
Simulation time 74962718159 ps
CPU time 1253.75 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 01:02:54 PM PST 24
Peak memory 281720 kb
Host smart-60eb7730-7b84-4ae3-b0a1-b3ba643671e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109668645 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.109668645
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.4150172602
Short name T572
Test name
Test status
Simulation time 4497547262 ps
CPU time 593.09 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:51:46 PM PST 24
Peak memory 272256 kb
Host smart-d3d72997-d6c7-4dfa-9394-12bc2950ba60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150172602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.4150172602
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.230483010
Short name T634
Test name
Test status
Simulation time 15391796794 ps
CPU time 252.96 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 250900 kb
Host smart-24a97ea7-023c-4851-918c-fa02f698bc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23048
3010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.230483010
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1160236507
Short name T691
Test name
Test status
Simulation time 71761036 ps
CPU time 4.87 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:03 PM PST 24
Peak memory 238908 kb
Host smart-455ab33f-7fc4-4469-950d-f94691bfa12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11602
36507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1160236507
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1506299197
Short name T224
Test name
Test status
Simulation time 28441632279 ps
CPU time 601.47 seconds
Started Mar 03 12:41:50 PM PST 24
Finished Mar 03 12:51:53 PM PST 24
Peak memory 272988 kb
Host smart-4ec3467e-7bd9-4f3c-9095-b87b0c34ac19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506299197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1506299197
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3106744002
Short name T495
Test name
Test status
Simulation time 67554127519 ps
CPU time 2203.85 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 01:18:40 PM PST 24
Peak memory 272360 kb
Host smart-01e97823-85a0-4b8a-8d4a-03a927422541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106744002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3106744002
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3614620493
Short name T304
Test name
Test status
Simulation time 6689738894 ps
CPU time 266.73 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:46:22 PM PST 24
Peak memory 247628 kb
Host smart-73be4b4e-f089-4c4f-ad89-44dd7a4291ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614620493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3614620493
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2676898572
Short name T467
Test name
Test status
Simulation time 565780533 ps
CPU time 34.77 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 248776 kb
Host smart-3f07ec3a-584d-4816-afc4-a68a2d25c22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26768
98572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2676898572
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1139753963
Short name T431
Test name
Test status
Simulation time 412190632 ps
CPU time 28.02 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 254448 kb
Host smart-b3ee6136-14ae-44c5-8dd5-3f956da0ba39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
53963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1139753963
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4266870628
Short name T550
Test name
Test status
Simulation time 520032381 ps
CPU time 32.46 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 248760 kb
Host smart-1d81c9ff-f073-49c8-ab7c-1061598642bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42668
70628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4266870628
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3461184499
Short name T284
Test name
Test status
Simulation time 617029090 ps
CPU time 34.59 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 255500 kb
Host smart-9ef7fbd0-5c75-40ea-aaf0-e63f581a1255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34611
84499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3461184499
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2360454092
Short name T78
Test name
Test status
Simulation time 7200878340 ps
CPU time 800.54 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:55:20 PM PST 24
Peak memory 265216 kb
Host smart-2262359d-3658-433e-a054-bdc3758e3e1c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360454092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2360454092
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4062773626
Short name T628
Test name
Test status
Simulation time 8461922709 ps
CPU time 132.98 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 12:44:15 PM PST 24
Peak memory 256496 kb
Host smart-2cba9cd9-e626-44a8-b6c2-41480ac11a2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40627
73626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4062773626
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2230747945
Short name T79
Test name
Test status
Simulation time 132390061 ps
CPU time 12.74 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:08 PM PST 24
Peak memory 255216 kb
Host smart-fc6bb7a2-4d8b-41aa-8d79-06cd34015e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
47945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2230747945
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3429436588
Short name T334
Test name
Test status
Simulation time 19482004494 ps
CPU time 1114.5 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 01:00:34 PM PST 24
Peak memory 273044 kb
Host smart-a81042ba-d6a1-4035-bcc2-23622bf40bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429436588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3429436588
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.265171777
Short name T8
Test name
Test status
Simulation time 15564440104 ps
CPU time 1433.95 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 01:06:00 PM PST 24
Peak memory 289072 kb
Host smart-7118661d-53bb-4c28-9ea5-bac66e71e24a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265171777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.265171777
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1598904624
Short name T525
Test name
Test status
Simulation time 26884907400 ps
CPU time 300.56 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:47:01 PM PST 24
Peak memory 247504 kb
Host smart-fc6b133c-62be-48fd-bb33-140c69ad3261
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598904624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1598904624
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3159783455
Short name T505
Test name
Test status
Simulation time 3053722372 ps
CPU time 47.9 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:42:57 PM PST 24
Peak memory 255736 kb
Host smart-fc609dba-376f-40e9-aa37-71e3288160d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31597
83455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3159783455
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2101125632
Short name T67
Test name
Test status
Simulation time 1415990427 ps
CPU time 39.43 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 247612 kb
Host smart-2cef1b2c-1d6e-4651-861c-45c4dfb4d2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
25632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2101125632
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2334167455
Short name T649
Test name
Test status
Simulation time 1076665212 ps
CPU time 38.31 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 255624 kb
Host smart-a246e07d-bfb5-4bf4-973a-9e758378bd0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23341
67455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2334167455
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.253343068
Short name T98
Test name
Test status
Simulation time 622711152 ps
CPU time 46.42 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 255736 kb
Host smart-64264a05-5b7e-4378-9cd5-33c5f9f56550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
3068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.253343068
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.493409570
Short name T110
Test name
Test status
Simulation time 28764365306 ps
CPU time 1595.45 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 01:08:33 PM PST 24
Peak memory 288856 kb
Host smart-9985b82a-f4a3-4ae5-996f-2bb004e331ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493409570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.493409570
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1224252644
Short name T481
Test name
Test status
Simulation time 1959715081 ps
CPU time 157.05 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:44:35 PM PST 24
Peak memory 256520 kb
Host smart-23c34221-0b78-4ee6-bf8c-ac02b903fea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12242
52644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1224252644
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3815864117
Short name T469
Test name
Test status
Simulation time 392458369 ps
CPU time 24.73 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:24 PM PST 24
Peak memory 254260 kb
Host smart-82895c5e-2c22-4575-81c0-66bee033c057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158
64117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3815864117
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2338713648
Short name T694
Test name
Test status
Simulation time 54018604776 ps
CPU time 1316.88 seconds
Started Mar 03 12:42:03 PM PST 24
Finished Mar 03 01:04:00 PM PST 24
Peak memory 282356 kb
Host smart-affb201d-2b66-4861-a463-4f057379e4e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338713648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2338713648
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.1501658741
Short name T509
Test name
Test status
Simulation time 28538456979 ps
CPU time 1602.46 seconds
Started Mar 03 12:41:59 PM PST 24
Finished Mar 03 01:08:43 PM PST 24
Peak memory 288288 kb
Host smart-d0fd4085-a44e-4f9b-9a2a-7ee33daffa9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501658741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.1501658741
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3397612078
Short name T596
Test name
Test status
Simulation time 616834854 ps
CPU time 35.91 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 248936 kb
Host smart-4a2ee86d-d2f6-46d5-bd41-5522e469a40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976
12078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3397612078
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.864141475
Short name T392
Test name
Test status
Simulation time 576449755 ps
CPU time 33.02 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 248280 kb
Host smart-3452510d-e0e1-4716-bf77-fdb2c473cfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86414
1475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.864141475
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3168410233
Short name T22
Test name
Test status
Simulation time 1087630551 ps
CPU time 25.03 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 12:42:26 PM PST 24
Peak memory 254612 kb
Host smart-46612b00-74b1-4d1d-b83a-587fce79f50f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
10233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3168410233
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2899549581
Short name T473
Test name
Test status
Simulation time 780958810 ps
CPU time 28.11 seconds
Started Mar 03 12:42:08 PM PST 24
Finished Mar 03 12:42:36 PM PST 24
Peak memory 248776 kb
Host smart-12724e2b-a33c-431a-afe3-c0ec10757731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28995
49581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2899549581
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.612464948
Short name T279
Test name
Test status
Simulation time 443982758 ps
CPU time 16.95 seconds
Started Mar 03 12:41:54 PM PST 24
Finished Mar 03 12:42:11 PM PST 24
Peak memory 254464 kb
Host smart-27bd1269-6385-483d-b50d-8e161a9bdf13
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612464948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.612464948
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1041243612
Short name T571
Test name
Test status
Simulation time 19977993316 ps
CPU time 2105.1 seconds
Started Mar 03 12:42:07 PM PST 24
Finished Mar 03 01:17:13 PM PST 24
Peak memory 306116 kb
Host smart-a3cb42f4-bfcc-4526-b06a-d3bec14dff15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041243612 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1041243612
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4117216970
Short name T223
Test name
Test status
Simulation time 96383778348 ps
CPU time 1429.32 seconds
Started Mar 03 12:41:53 PM PST 24
Finished Mar 03 01:05:44 PM PST 24
Peak memory 265244 kb
Host smart-352844d2-8923-4606-a09b-062f97ebca6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117216970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4117216970
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.275217976
Short name T497
Test name
Test status
Simulation time 3055395066 ps
CPU time 131.49 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:44:11 PM PST 24
Peak memory 250908 kb
Host smart-3a969274-b4b0-4665-9f8d-45f95a4f822e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
7976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.275217976
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2421489225
Short name T444
Test name
Test status
Simulation time 398792032 ps
CPU time 30.48 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 255048 kb
Host smart-48f9b6b5-b6fa-40bc-80ed-1253683b63ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24214
89225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2421489225
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2144767892
Short name T321
Test name
Test status
Simulation time 93845765661 ps
CPU time 1566.26 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 01:08:06 PM PST 24
Peak memory 273524 kb
Host smart-a0bf73b6-c585-4373-88d7-9a95b9d7f8a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144767892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2144767892
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2972292897
Short name T447
Test name
Test status
Simulation time 58233075469 ps
CPU time 1285.5 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 01:03:31 PM PST 24
Peak memory 285736 kb
Host smart-6a4d98b6-a01b-4d96-9231-73f616307b48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972292897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2972292897
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3199339113
Short name T299
Test name
Test status
Simulation time 13481859661 ps
CPU time 297.26 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:46:54 PM PST 24
Peak memory 247736 kb
Host smart-58b9deb0-f482-4d99-9e33-17cb33290df0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199339113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3199339113
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.409487881
Short name T480
Test name
Test status
Simulation time 126871626 ps
CPU time 4.77 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:04 PM PST 24
Peak memory 240576 kb
Host smart-cf66f552-35ee-47e8-9148-e57f4c4510ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40948
7881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.409487881
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.781663810
Short name T594
Test name
Test status
Simulation time 643080873 ps
CPU time 12.87 seconds
Started Mar 03 12:42:00 PM PST 24
Finished Mar 03 12:42:13 PM PST 24
Peak memory 246928 kb
Host smart-80648d9d-ed77-44b3-84a4-935bb096b66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78166
3810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.781663810
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1150529173
Short name T115
Test name
Test status
Simulation time 648036393 ps
CPU time 41.72 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 255612 kb
Host smart-cb25a6d4-1d2c-455d-ba5d-5387136b6577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11505
29173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1150529173
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3712064872
Short name T366
Test name
Test status
Simulation time 80698374 ps
CPU time 5.84 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:41:59 PM PST 24
Peak memory 240560 kb
Host smart-f046d322-59cb-4538-b388-826b4dd2052e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37120
64872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3712064872
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2357721
Short name T674
Test name
Test status
Simulation time 47341137856 ps
CPU time 1520.31 seconds
Started Mar 03 12:42:02 PM PST 24
Finished Mar 03 01:07:23 PM PST 24
Peak memory 273288 kb
Host smart-2a0fe3d6-3a7f-4855-8ccb-ee1a7e1ae253
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2357721
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1613307726
Short name T588
Test name
Test status
Simulation time 3777443547 ps
CPU time 226.21 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:45:46 PM PST 24
Peak memory 256260 kb
Host smart-28d8554f-bef6-4b8f-8aa0-59a75ae1c92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16133
07726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1613307726
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3688530647
Short name T382
Test name
Test status
Simulation time 578164804 ps
CPU time 33.74 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 256432 kb
Host smart-21e5be7e-4b56-4b6c-99ff-eaa4101b22f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885
30647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3688530647
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2440023165
Short name T652
Test name
Test status
Simulation time 88132606583 ps
CPU time 746.2 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:54:36 PM PST 24
Peak memory 265236 kb
Host smart-e339f4d4-e6f3-4398-9040-49669c4e7334
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440023165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2440023165
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3901131101
Short name T437
Test name
Test status
Simulation time 9684378277 ps
CPU time 330.97 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:47:36 PM PST 24
Peak memory 248828 kb
Host smart-5d52e8d2-73d6-4aba-b6b0-246a40cad9e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901131101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3901131101
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1558834494
Short name T704
Test name
Test status
Simulation time 51032283 ps
CPU time 4.38 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:00 PM PST 24
Peak memory 248780 kb
Host smart-1a2ee1bf-51a6-4aab-a784-50a926bd869f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15588
34494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1558834494
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1367882554
Short name T511
Test name
Test status
Simulation time 218399738 ps
CPU time 8.91 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 12:42:09 PM PST 24
Peak memory 250348 kb
Host smart-5dc435f8-3996-43c8-9def-d660d058a077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
82554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1367882554
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.399372473
Short name T420
Test name
Test status
Simulation time 224978276 ps
CPU time 9.39 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:07 PM PST 24
Peak memory 252212 kb
Host smart-34344566-1cdf-465c-9b75-9c5eca991e7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39937
2473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.399372473
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2764534265
Short name T446
Test name
Test status
Simulation time 71950612 ps
CPU time 8.04 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:42:08 PM PST 24
Peak memory 248872 kb
Host smart-9839f042-b5ff-437e-958d-ae9362db36b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27645
34265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2764534265
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.3879120904
Short name T703
Test name
Test status
Simulation time 440331609 ps
CPU time 30.06 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 255376 kb
Host smart-1dcacac6-d849-42fb-9805-d7f8421678ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879120904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.3879120904
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3472995734
Short name T104
Test name
Test status
Simulation time 44402260522 ps
CPU time 2646.96 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 01:26:07 PM PST 24
Peak memory 281752 kb
Host smart-5ff78675-573a-454e-b5fd-2b821876f441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472995734 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3472995734
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3528287525
Short name T103
Test name
Test status
Simulation time 150167903543 ps
CPU time 2831.06 seconds
Started Mar 03 12:41:59 PM PST 24
Finished Mar 03 01:29:12 PM PST 24
Peak memory 289164 kb
Host smart-f5fe4a95-892f-4144-b84b-581ac04eab82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528287525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3528287525
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3230235289
Short name T64
Test name
Test status
Simulation time 2810837735 ps
CPU time 175.46 seconds
Started Mar 03 12:42:07 PM PST 24
Finished Mar 03 12:45:02 PM PST 24
Peak memory 257072 kb
Host smart-b918dcd6-4206-4bec-8b14-c38b45610707
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32302
35289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3230235289
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1010061671
Short name T425
Test name
Test status
Simulation time 4630463026 ps
CPU time 36.76 seconds
Started Mar 03 12:41:55 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 255300 kb
Host smart-c7967345-2e3d-4864-998c-580160ab5995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100
61671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1010061671
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3698136791
Short name T702
Test name
Test status
Simulation time 36338514277 ps
CPU time 771.89 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:55:01 PM PST 24
Peak memory 272696 kb
Host smart-7d166307-4bc8-4bf7-a585-e83db465cca2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698136791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3698136791
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.500345877
Short name T278
Test name
Test status
Simulation time 27786835615 ps
CPU time 1738.17 seconds
Started Mar 03 12:42:03 PM PST 24
Finished Mar 03 01:11:01 PM PST 24
Peak memory 272972 kb
Host smart-e03797f7-fe4e-4607-a1a3-09ede08cacbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500345877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.500345877
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2445294504
Short name T506
Test name
Test status
Simulation time 15400302778 ps
CPU time 155.2 seconds
Started Mar 03 12:41:56 PM PST 24
Finished Mar 03 12:44:34 PM PST 24
Peak memory 247716 kb
Host smart-423e2520-3743-47bd-befb-698b20f74c66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445294504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2445294504
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3109815894
Short name T125
Test name
Test status
Simulation time 187167193 ps
CPU time 15.47 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 248776 kb
Host smart-cd80e705-ec64-415f-bf05-1e6d730bb214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31098
15894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3109815894
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2569643931
Short name T80
Test name
Test status
Simulation time 1320571144 ps
CPU time 37.62 seconds
Started Mar 03 12:42:00 PM PST 24
Finished Mar 03 12:42:38 PM PST 24
Peak memory 254648 kb
Host smart-4ba07bf5-744a-4e34-83d2-fb7e880cb732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
43931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2569643931
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3559517961
Short name T545
Test name
Test status
Simulation time 2460476220 ps
CPU time 34.78 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 247484 kb
Host smart-280edd42-02d8-4c97-977d-243d61abf128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35595
17961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3559517961
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.430946206
Short name T633
Test name
Test status
Simulation time 3109807209 ps
CPU time 48.18 seconds
Started Mar 03 12:41:58 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 255772 kb
Host smart-8e63ac8f-89a8-48c4-8e62-19b4c72bae2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43094
6206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.430946206
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3794842203
Short name T292
Test name
Test status
Simulation time 56205087109 ps
CPU time 1784.1 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 01:11:53 PM PST 24
Peak memory 288992 kb
Host smart-4496a936-1d37-43b0-a9d4-5b198c66b48a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794842203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3794842203
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1464524074
Short name T418
Test name
Test status
Simulation time 3153861720 ps
CPU time 207.5 seconds
Started Mar 03 12:42:02 PM PST 24
Finished Mar 03 12:45:30 PM PST 24
Peak memory 256596 kb
Host smart-c9fd3c81-87d0-4645-a338-6f16c013a95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14645
24074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1464524074
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1810334162
Short name T489
Test name
Test status
Simulation time 324731659 ps
CPU time 8.73 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 249480 kb
Host smart-560b535f-a240-4c6f-8614-0af4e699059b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18103
34162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1810334162
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3431213548
Short name T659
Test name
Test status
Simulation time 92128594671 ps
CPU time 1604.89 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 01:08:54 PM PST 24
Peak memory 273104 kb
Host smart-363c27cc-dda2-435d-81fb-c5f6a0c772ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431213548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3431213548
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1791488766
Short name T583
Test name
Test status
Simulation time 200003175997 ps
CPU time 1615.29 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 01:09:12 PM PST 24
Peak memory 267388 kb
Host smart-0902bf3f-ac49-43e0-9706-029fcff943b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791488766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1791488766
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3009517204
Short name T599
Test name
Test status
Simulation time 74326647593 ps
CPU time 468.28 seconds
Started Mar 03 12:42:02 PM PST 24
Finished Mar 03 12:49:51 PM PST 24
Peak memory 247604 kb
Host smart-3c7ef40d-bae8-4923-91aa-c24e8d29e317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009517204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3009517204
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3177137816
Short name T383
Test name
Test status
Simulation time 1391657344 ps
CPU time 29.7 seconds
Started Mar 03 12:41:57 PM PST 24
Finished Mar 03 12:42:29 PM PST 24
Peak memory 255336 kb
Host smart-e06a44a9-8632-44f8-9ad1-435392bb8ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31771
37816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3177137816
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1904486090
Short name T645
Test name
Test status
Simulation time 96487734 ps
CPU time 4.44 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:42:10 PM PST 24
Peak memory 250796 kb
Host smart-e38ab91b-646d-4844-b8fb-c0aaa653aaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19044
86090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1904486090
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3987147316
Short name T84
Test name
Test status
Simulation time 660775395 ps
CPU time 23.25 seconds
Started Mar 03 12:42:02 PM PST 24
Finished Mar 03 12:42:26 PM PST 24
Peak memory 255088 kb
Host smart-2d0614c0-583b-4572-8221-bb729b9ea50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39871
47316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3987147316
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.920487100
Short name T678
Test name
Test status
Simulation time 317891932 ps
CPU time 22.01 seconds
Started Mar 03 12:42:04 PM PST 24
Finished Mar 03 12:42:26 PM PST 24
Peak memory 255572 kb
Host smart-a4792920-663e-4eb8-9c62-ed7af52ad01e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92048
7100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.920487100
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.152985034
Short name T548
Test name
Test status
Simulation time 9824890610 ps
CPU time 983.14 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 12:58:39 PM PST 24
Peak memory 289156 kb
Host smart-5b44b265-9c9c-45a0-b70a-a55207e55290
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152985034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.152985034
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.976511773
Short name T235
Test name
Test status
Simulation time 20606041184 ps
CPU time 1320.14 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 01:04:05 PM PST 24
Peak memory 273264 kb
Host smart-1c4f627b-92f7-4dc8-880b-4e1da71aa324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976511773 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.976511773
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3900008105
Short name T433
Test name
Test status
Simulation time 196703137937 ps
CPU time 2906.99 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 01:30:37 PM PST 24
Peak memory 289604 kb
Host smart-3a8a0b40-5995-45a8-bd96-e6ae8d7b9964
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900008105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3900008105
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1931074528
Short name T459
Test name
Test status
Simulation time 1311797816 ps
CPU time 68.42 seconds
Started Mar 03 12:42:04 PM PST 24
Finished Mar 03 12:43:12 PM PST 24
Peak memory 256064 kb
Host smart-2431fdb5-ec49-4374-9131-ef1452194290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19310
74528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1931074528
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.892470393
Short name T598
Test name
Test status
Simulation time 4456772936 ps
CPU time 75.18 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:43:25 PM PST 24
Peak memory 255296 kb
Host smart-ad381fa5-2119-46cc-88c0-bd382d1d09c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89247
0393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.892470393
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.442991265
Short name T76
Test name
Test status
Simulation time 13458557225 ps
CPU time 799.14 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 12:55:20 PM PST 24
Peak memory 272544 kb
Host smart-3cf3efbf-1710-4790-9069-d45024e24db3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442991265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.442991265
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2886225338
Short name T230
Test name
Test status
Simulation time 13365994450 ps
CPU time 1081.85 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 01:00:18 PM PST 24
Peak memory 282256 kb
Host smart-ad0e7e1b-1438-49c7-b25c-d0cdea759c7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886225338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2886225338
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4239122736
Short name T684
Test name
Test status
Simulation time 8660007205 ps
CPU time 321.19 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:47:30 PM PST 24
Peak memory 247704 kb
Host smart-59358b99-d814-4be0-8798-b4e56c3c9839
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239122736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4239122736
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1755187581
Short name T661
Test name
Test status
Simulation time 209638633 ps
CPU time 18.76 seconds
Started Mar 03 12:42:03 PM PST 24
Finished Mar 03 12:42:22 PM PST 24
Peak memory 248776 kb
Host smart-7c38987f-f8e7-43a7-8610-c026f7c6fcd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17551
87581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1755187581
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3511688336
Short name T410
Test name
Test status
Simulation time 215934868 ps
CPU time 28.71 seconds
Started Mar 03 12:42:08 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 246888 kb
Host smart-7349cb67-a84e-45e1-9184-513b012171d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35116
88336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3511688336
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2185703325
Short name T389
Test name
Test status
Simulation time 3731712892 ps
CPU time 66.46 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 12:43:12 PM PST 24
Peak memory 255820 kb
Host smart-791e6171-3c55-4d95-a4cf-0d94d0c4f912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
03325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2185703325
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1851607148
Short name T92
Test name
Test status
Simulation time 1513583403 ps
CPU time 48.28 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:42:54 PM PST 24
Peak memory 248784 kb
Host smart-58a0546d-ba08-4b32-9efa-de6452185a21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851607148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1851607148
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.4257443436
Short name T692
Test name
Test status
Simulation time 428730132561 ps
CPU time 7080.34 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 02:40:10 PM PST 24
Peak memory 355232 kb
Host smart-c981271f-2b1a-420f-943c-9571ebd10798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257443436 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.4257443436
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3221204709
Short name T206
Test name
Test status
Simulation time 56908961 ps
CPU time 2.87 seconds
Started Mar 03 12:41:07 PM PST 24
Finished Mar 03 12:41:15 PM PST 24
Peak memory 248864 kb
Host smart-2dd309c7-d9fc-4c9d-b3e7-82173accadcb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3221204709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3221204709
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2076646866
Short name T618
Test name
Test status
Simulation time 39098740148 ps
CPU time 762.1 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:53:56 PM PST 24
Peak memory 265232 kb
Host smart-0b4770bc-0f74-435a-9f37-d653ed26119d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076646866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2076646866
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1151326231
Short name T16
Test name
Test status
Simulation time 410926534 ps
CPU time 11.09 seconds
Started Mar 03 12:41:14 PM PST 24
Finished Mar 03 12:41:25 PM PST 24
Peak memory 248776 kb
Host smart-5babc3b8-bdd6-4ee4-9ce9-1b8f7a50af96
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1151326231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1151326231
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1112646865
Short name T580
Test name
Test status
Simulation time 819993043 ps
CPU time 67.12 seconds
Started Mar 03 12:41:07 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 256196 kb
Host smart-ae8dd1e2-49d3-4581-ad9b-5678172c637a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11126
46865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1112646865
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3885979991
Short name T124
Test name
Test status
Simulation time 38263038 ps
CPU time 5.16 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:24 PM PST 24
Peak memory 251636 kb
Host smart-30f24d13-54b3-4cf6-a82b-755fe98a3358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38859
79991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3885979991
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2706972451
Short name T294
Test name
Test status
Simulation time 44611872215 ps
CPU time 1694.89 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 01:09:32 PM PST 24
Peak memory 289348 kb
Host smart-553adde8-5e56-4f98-a170-a323ea34f890
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706972451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2706972451
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1277306269
Short name T534
Test name
Test status
Simulation time 8859752851 ps
CPU time 830.25 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:55:08 PM PST 24
Peak memory 271364 kb
Host smart-d5924d03-06f4-4c46-a168-9687a9360e82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277306269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1277306269
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1308721372
Short name T581
Test name
Test status
Simulation time 816072322 ps
CPU time 45.93 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:42:13 PM PST 24
Peak memory 249064 kb
Host smart-3c3e64a9-430f-4872-8982-9c16bf320aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13087
21372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1308721372
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3553165765
Short name T394
Test name
Test status
Simulation time 193184211 ps
CPU time 12.65 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 252256 kb
Host smart-bced9df5-6422-4519-95d7-98dfcdb9c65d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35531
65765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3553165765
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3334461540
Short name T626
Test name
Test status
Simulation time 33665277 ps
CPU time 4.45 seconds
Started Mar 03 12:41:12 PM PST 24
Finished Mar 03 12:41:17 PM PST 24
Peak memory 250476 kb
Host smart-34f75b8b-26dc-4dce-a46e-8fcd9e05a103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33344
61540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3334461540
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.636789523
Short name T436
Test name
Test status
Simulation time 255690212 ps
CPU time 18.9 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 248756 kb
Host smart-24d4c1a3-c1de-4386-987d-6740fa8e6789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63678
9523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.636789523
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.3978740753
Short name T221
Test name
Test status
Simulation time 17193221207 ps
CPU time 277.86 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:45:44 PM PST 24
Peak memory 253228 kb
Host smart-aba0fb27-7601-4971-8627-ee09be3c1ddb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978740753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.3978740753
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3725707521
Short name T484
Test name
Test status
Simulation time 31619044732 ps
CPU time 2181.15 seconds
Started Mar 03 12:42:03 PM PST 24
Finished Mar 03 01:18:25 PM PST 24
Peak memory 289636 kb
Host smart-9a7854b6-c8c0-4252-b9af-5c39c8bcbf5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725707521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3725707521
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2108003119
Short name T408
Test name
Test status
Simulation time 7987929783 ps
CPU time 211.85 seconds
Started Mar 03 12:42:02 PM PST 24
Finished Mar 03 12:45:34 PM PST 24
Peak memory 257012 kb
Host smart-14437af7-cb27-43c3-9f87-3bf81fe8f24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21080
03119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2108003119
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.404051821
Short name T642
Test name
Test status
Simulation time 175997239 ps
CPU time 2.96 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 12:42:28 PM PST 24
Peak memory 238848 kb
Host smart-0498cc22-1839-4e3e-92e5-1c36c645756b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40405
1821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.404051821
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2553863869
Short name T322
Test name
Test status
Simulation time 48164396961 ps
CPU time 2613.66 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 01:25:44 PM PST 24
Peak memory 287008 kb
Host smart-6c28ba4a-c75b-4d96-ae79-c97158186af9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553863869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2553863869
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.1302039521
Short name T592
Test name
Test status
Simulation time 14143145681 ps
CPU time 638.06 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:52:43 PM PST 24
Peak memory 264856 kb
Host smart-0843d72b-71ad-46ee-94c0-1f12f16e7e2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302039521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.1302039521
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.516456903
Short name T602
Test name
Test status
Simulation time 13952310743 ps
CPU time 155.24 seconds
Started Mar 03 12:42:05 PM PST 24
Finished Mar 03 12:44:40 PM PST 24
Peak memory 247508 kb
Host smart-04fa02d4-d59b-49ef-afc4-13b20edc0d84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516456903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.516456903
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3225919334
Short name T401
Test name
Test status
Simulation time 484279815 ps
CPU time 27.24 seconds
Started Mar 03 12:42:03 PM PST 24
Finished Mar 03 12:42:31 PM PST 24
Peak memory 248760 kb
Host smart-e49adece-4adf-4f62-b916-760ce58cfb6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
19334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3225919334
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.2847441315
Short name T624
Test name
Test status
Simulation time 8508058225 ps
CPU time 54.58 seconds
Started Mar 03 12:45:13 PM PST 24
Finished Mar 03 12:46:07 PM PST 24
Peak memory 254872 kb
Host smart-a23ccb5f-3a91-4458-887e-de8a45a93d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
41315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2847441315
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3230436045
Short name T85
Test name
Test status
Simulation time 100123466 ps
CPU time 11.31 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 12:42:22 PM PST 24
Peak memory 253508 kb
Host smart-3ff89530-611f-402f-9222-111944826a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32304
36045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3230436045
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.875366107
Short name T359
Test name
Test status
Simulation time 6519106964 ps
CPU time 61.92 seconds
Started Mar 03 12:42:00 PM PST 24
Finished Mar 03 12:43:02 PM PST 24
Peak memory 248840 kb
Host smart-a1f80e5a-d59a-4716-b2cc-fe9956c59043
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87536
6107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.875366107
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3284416670
Short name T555
Test name
Test status
Simulation time 5490540578 ps
CPU time 500.15 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:50:30 PM PST 24
Peak memory 265220 kb
Host smart-3e7f20fc-267f-4a34-86cc-b6506b3e0073
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284416670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3284416670
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3790649460
Short name T656
Test name
Test status
Simulation time 26117517764 ps
CPU time 1678.57 seconds
Started Mar 03 12:42:17 PM PST 24
Finished Mar 03 01:10:16 PM PST 24
Peak memory 282256 kb
Host smart-b1548b69-f36b-4648-84e8-82bf23eb3861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790649460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3790649460
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3853682807
Short name T468
Test name
Test status
Simulation time 1402166223 ps
CPU time 94.43 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:43:43 PM PST 24
Peak memory 256356 kb
Host smart-7ff63fc3-a819-4e83-a05e-e39a26d973ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
82807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3853682807
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2336264857
Short name T567
Test name
Test status
Simulation time 445637551 ps
CPU time 47.6 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 12:42:53 PM PST 24
Peak memory 255332 kb
Host smart-cc99ccbc-92f9-4984-8ef3-28978faa9113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
64857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2336264857
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3134480476
Short name T100
Test name
Test status
Simulation time 84394344964 ps
CPU time 2858.27 seconds
Started Mar 03 12:42:01 PM PST 24
Finished Mar 03 01:29:40 PM PST 24
Peak memory 289356 kb
Host smart-c4bf739b-318a-416b-83ee-5ff65efa3941
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134480476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3134480476
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.95640915
Short name T427
Test name
Test status
Simulation time 175731290595 ps
CPU time 2542.68 seconds
Started Mar 03 12:41:59 PM PST 24
Finished Mar 03 01:24:23 PM PST 24
Peak memory 287824 kb
Host smart-e6fd0b4e-3220-42f1-a3c4-f2ded209204f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95640915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.95640915
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1434426498
Short name T354
Test name
Test status
Simulation time 6426153126 ps
CPU time 71.22 seconds
Started Mar 03 12:42:06 PM PST 24
Finished Mar 03 12:43:17 PM PST 24
Peak memory 247820 kb
Host smart-e26beef4-fa53-4d9b-bd0f-bc3fdbd1669c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434426498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1434426498
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3501037810
Short name T562
Test name
Test status
Simulation time 854882753 ps
CPU time 28.97 seconds
Started Mar 03 12:42:15 PM PST 24
Finished Mar 03 12:42:44 PM PST 24
Peak memory 255728 kb
Host smart-38b3339d-c04c-416f-ad5e-0cea0a67217f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35010
37810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3501037810
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4107128957
Short name T629
Test name
Test status
Simulation time 165189831 ps
CPU time 4 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:42:14 PM PST 24
Peak memory 238708 kb
Host smart-e220c4a6-8772-45dd-8c3a-8fc41d209218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41071
28957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4107128957
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4128173353
Short name T699
Test name
Test status
Simulation time 1918972039 ps
CPU time 60.46 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 12:43:17 PM PST 24
Peak memory 247356 kb
Host smart-3192ee84-3338-4f81-8b02-e31065f66c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
73353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4128173353
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1686729461
Short name T600
Test name
Test status
Simulation time 320217995 ps
CPU time 22.84 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 256932 kb
Host smart-9d6e9bfb-2ea3-49ea-a755-4ac55a315c78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16867
29461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1686729461
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2137006567
Short name T549
Test name
Test status
Simulation time 106613254327 ps
CPU time 1549.05 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 01:08:01 PM PST 24
Peak memory 283220 kb
Host smart-7ac23240-797a-40aa-8f30-3f35cbf3dda7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137006567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2137006567
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.468532745
Short name T52
Test name
Test status
Simulation time 13669791111 ps
CPU time 1214.8 seconds
Started Mar 03 12:42:17 PM PST 24
Finished Mar 03 01:02:32 PM PST 24
Peak memory 289948 kb
Host smart-a1a4ff82-0fb1-4f92-95dd-2919052a3f19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468532745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.468532745
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1445480251
Short name T225
Test name
Test status
Simulation time 17117634908 ps
CPU time 134.04 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 12:44:25 PM PST 24
Peak memory 257012 kb
Host smart-7e5dc54a-d977-47be-bcbc-b300fc7042c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14454
80251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1445480251
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2125592565
Short name T641
Test name
Test status
Simulation time 349697069 ps
CPU time 13 seconds
Started Mar 03 12:42:21 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 255172 kb
Host smart-4df9dde3-73ee-45ed-9537-f81b9039f07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21255
92565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2125592565
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4270437609
Short name T653
Test name
Test status
Simulation time 19946288862 ps
CPU time 1560.34 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 01:08:21 PM PST 24
Peak memory 289172 kb
Host smart-228c7e87-9dca-4de8-8db6-4576a945c8fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270437609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4270437609
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.736780928
Short name T478
Test name
Test status
Simulation time 6980797867 ps
CPU time 725.41 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 12:54:17 PM PST 24
Peak memory 273360 kb
Host smart-9d135517-0e7c-4342-a10d-ff744f475ff8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736780928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.736780928
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.989101248
Short name T560
Test name
Test status
Simulation time 45882156378 ps
CPU time 337.88 seconds
Started Mar 03 12:42:08 PM PST 24
Finished Mar 03 12:47:46 PM PST 24
Peak memory 247660 kb
Host smart-a33ef74a-6743-4f94-b540-8259b56ff98d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989101248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.989101248
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4104948713
Short name T398
Test name
Test status
Simulation time 598964807 ps
CPU time 35.49 seconds
Started Mar 03 12:42:19 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 248756 kb
Host smart-2081ed6f-81eb-402d-a379-7e0f23be71dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41049
48713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4104948713
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.4212218558
Short name T237
Test name
Test status
Simulation time 734379251 ps
CPU time 9 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 12:42:21 PM PST 24
Peak memory 250744 kb
Host smart-95634e8f-6045-497f-b2c7-bd64930331d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122
18558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.4212218558
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2755645906
Short name T573
Test name
Test status
Simulation time 1775005692 ps
CPU time 33.68 seconds
Started Mar 03 12:42:15 PM PST 24
Finished Mar 03 12:42:49 PM PST 24
Peak memory 254612 kb
Host smart-cf80488f-7ab1-4768-b317-97f979df3daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27556
45906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2755645906
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1396806262
Short name T502
Test name
Test status
Simulation time 381761984 ps
CPU time 21.82 seconds
Started Mar 03 12:42:17 PM PST 24
Finished Mar 03 12:42:39 PM PST 24
Peak memory 255584 kb
Host smart-fcc51d65-46a6-4a52-9859-c21ba59ae46a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13968
06262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1396806262
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2172380782
Short name T411
Test name
Test status
Simulation time 35766921021 ps
CPU time 2320.39 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 01:20:52 PM PST 24
Peak memory 288924 kb
Host smart-c22385ce-fb10-4c43-bf51-4e61882d1e09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172380782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2172380782
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.827978915
Short name T291
Test name
Test status
Simulation time 383561727941 ps
CPU time 3137.14 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 01:34:29 PM PST 24
Peak memory 289680 kb
Host smart-8440227a-9193-4077-bffa-a6155662ca70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827978915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.827978915
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.302027985
Short name T414
Test name
Test status
Simulation time 6082770227 ps
CPU time 305.62 seconds
Started Mar 03 12:42:21 PM PST 24
Finished Mar 03 12:47:27 PM PST 24
Peak memory 257016 kb
Host smart-1cd26c2e-4655-4266-a794-a1c2d10907ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30202
7985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.302027985
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.111378511
Short name T404
Test name
Test status
Simulation time 4536697733 ps
CPU time 58.6 seconds
Started Mar 03 12:42:17 PM PST 24
Finished Mar 03 12:43:15 PM PST 24
Peak memory 255212 kb
Host smart-678859a4-1875-4639-822f-172889903af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11137
8511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.111378511
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1244187791
Short name T331
Test name
Test status
Simulation time 18630750809 ps
CPU time 1553.97 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 01:08:04 PM PST 24
Peak memory 288936 kb
Host smart-fca8747d-c76d-4913-98ef-01d01556557e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244187791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1244187791
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3316014772
Short name T397
Test name
Test status
Simulation time 37224090073 ps
CPU time 1149.88 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 01:01:21 PM PST 24
Peak memory 272504 kb
Host smart-4b28efe4-af5e-4807-b5b3-ca4760490bc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316014772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3316014772
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.275022344
Short name T556
Test name
Test status
Simulation time 66052260558 ps
CPU time 374.96 seconds
Started Mar 03 12:42:07 PM PST 24
Finished Mar 03 12:48:22 PM PST 24
Peak memory 247840 kb
Host smart-4539277b-aa52-495d-80f9-e6b496a24124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275022344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.275022344
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2285224421
Short name T620
Test name
Test status
Simulation time 2686047282 ps
CPU time 18.27 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:42:27 PM PST 24
Peak memory 248844 kb
Host smart-5baa8883-69e9-4106-ab5a-87264ad0d7ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22852
24421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2285224421
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2055782779
Short name T286
Test name
Test status
Simulation time 1424246696 ps
CPU time 31.49 seconds
Started Mar 03 12:42:09 PM PST 24
Finished Mar 03 12:42:41 PM PST 24
Peak memory 254944 kb
Host smart-db4b761b-b7e0-4291-8e9c-1f881c87bec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20557
82779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2055782779
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3595612752
Short name T479
Test name
Test status
Simulation time 787420277 ps
CPU time 49.36 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:42:59 PM PST 24
Peak memory 248780 kb
Host smart-9134188b-67c1-4648-b358-59fa6197821a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35956
12752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3595612752
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.208771276
Short name T60
Test name
Test status
Simulation time 262721371638 ps
CPU time 2860.12 seconds
Started Mar 03 12:42:18 PM PST 24
Finished Mar 03 01:29:58 PM PST 24
Peak memory 289380 kb
Host smart-c1d6bcc3-4920-46f6-be81-a7fbf0245744
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208771276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.208771276
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1532083403
Short name T458
Test name
Test status
Simulation time 78285634343 ps
CPU time 1811.29 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 01:12:32 PM PST 24
Peak memory 289804 kb
Host smart-f5276a8c-7d8a-4b06-a431-a9057a66b77f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532083403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1532083403
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.479623033
Short name T507
Test name
Test status
Simulation time 4807201996 ps
CPU time 289.34 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 12:47:00 PM PST 24
Peak memory 256980 kb
Host smart-df211e89-1205-4637-b73c-b9a7ef92e31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47962
3033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.479623033
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.84541031
Short name T586
Test name
Test status
Simulation time 443054323 ps
CPU time 10.92 seconds
Started Mar 03 12:42:26 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 248880 kb
Host smart-940e1675-01b7-46a2-9725-df12dd6b9e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84541
031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.84541031
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3886732869
Short name T686
Test name
Test status
Simulation time 38269333705 ps
CPU time 901.77 seconds
Started Mar 03 12:42:11 PM PST 24
Finished Mar 03 12:57:13 PM PST 24
Peak memory 272888 kb
Host smart-0a52829d-5842-497c-a718-392d3ff26683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886732869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3886732869
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2977013373
Short name T563
Test name
Test status
Simulation time 102243633860 ps
CPU time 1371.79 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 01:05:12 PM PST 24
Peak memory 272428 kb
Host smart-08d0b529-0a92-4abf-b7b6-4640b0839cb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977013373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2977013373
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4177115858
Short name T12
Test name
Test status
Simulation time 11121737905 ps
CPU time 386.81 seconds
Started Mar 03 12:42:24 PM PST 24
Finished Mar 03 12:48:51 PM PST 24
Peak memory 247528 kb
Host smart-199851b0-09a4-4e97-98bd-f9402085606d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177115858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4177115858
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3723770311
Short name T438
Test name
Test status
Simulation time 4132313804 ps
CPU time 66.29 seconds
Started Mar 03 12:42:08 PM PST 24
Finished Mar 03 12:43:14 PM PST 24
Peak memory 255912 kb
Host smart-7425ab85-444a-4217-96e0-92a92c1df99d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37237
70311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3723770311
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1377426486
Short name T696
Test name
Test status
Simulation time 1458598056 ps
CPU time 29.05 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 12:42:41 PM PST 24
Peak memory 255668 kb
Host smart-ff888047-d5c0-41f6-b3d6-d1f567628f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13774
26486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1377426486
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1754733296
Short name T671
Test name
Test status
Simulation time 1421417845 ps
CPU time 26.46 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 255676 kb
Host smart-6f377a12-6d84-4e27-bd56-3e565c789c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17547
33296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1754733296
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2845444402
Short name T650
Test name
Test status
Simulation time 43347783069 ps
CPU time 1488.2 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 01:07:13 PM PST 24
Peak memory 289704 kb
Host smart-296a6806-0a13-4f81-96a6-dd4256ee3502
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845444402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2845444402
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3193718707
Short name T688
Test name
Test status
Simulation time 45960078630 ps
CPU time 1165.52 seconds
Started Mar 03 12:42:19 PM PST 24
Finished Mar 03 01:01:45 PM PST 24
Peak memory 290080 kb
Host smart-6ba7a4e9-311e-48c2-b98c-4aaa0313475c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193718707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3193718707
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.208548173
Short name T660
Test name
Test status
Simulation time 1307417390 ps
CPU time 108.98 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 12:44:14 PM PST 24
Peak memory 256572 kb
Host smart-8f55a749-5005-4101-9b62-2e6aaba242d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20854
8173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.208548173
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2286603833
Short name T369
Test name
Test status
Simulation time 123553552 ps
CPU time 11.66 seconds
Started Mar 03 12:42:18 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 252576 kb
Host smart-b1ad0259-e250-4228-99ce-6487d968e962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22866
03833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2286603833
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.58389975
Short name T348
Test name
Test status
Simulation time 35791103991 ps
CPU time 913.32 seconds
Started Mar 03 12:42:19 PM PST 24
Finished Mar 03 12:57:32 PM PST 24
Peak memory 272924 kb
Host smart-3931231b-cdaf-4ccd-a16e-3cd47c6d1db1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58389975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.58389975
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3379719918
Short name T282
Test name
Test status
Simulation time 54614638554 ps
CPU time 1697.94 seconds
Started Mar 03 12:42:23 PM PST 24
Finished Mar 03 01:10:41 PM PST 24
Peak memory 271480 kb
Host smart-9651b4b4-9da9-4ce0-a076-ac19ffdf4c24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379719918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3379719918
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.4041983232
Short name T302
Test name
Test status
Simulation time 31060597674 ps
CPU time 328.86 seconds
Started Mar 03 12:42:17 PM PST 24
Finished Mar 03 12:47:46 PM PST 24
Peak memory 247740 kb
Host smart-43a08ec8-63f5-4817-9094-6e154ef5ebc4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041983232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.4041983232
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1097198345
Short name T381
Test name
Test status
Simulation time 1900611832 ps
CPU time 25.02 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 248776 kb
Host smart-80a37f36-8b4a-4d8b-9ad6-b3622fa067a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10971
98345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1097198345
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2286218717
Short name T500
Test name
Test status
Simulation time 3812633478 ps
CPU time 63.27 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:43:25 PM PST 24
Peak memory 255796 kb
Host smart-5cb0d0f5-f4ba-4004-a078-8aa6c49bf31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
18717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2286218717
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1558684556
Short name T541
Test name
Test status
Simulation time 1213220354 ps
CPU time 18.53 seconds
Started Mar 03 12:42:10 PM PST 24
Finished Mar 03 12:42:28 PM PST 24
Peak memory 248748 kb
Host smart-e4aee969-7926-4bc9-8fab-20edd2e27e8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
84556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1558684556
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3155442153
Short name T267
Test name
Test status
Simulation time 34983766883 ps
CPU time 905.38 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:57:27 PM PST 24
Peak memory 273404 kb
Host smart-d3194b47-1102-4587-9bcd-8a4020e231f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155442153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3155442153
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3464991773
Short name T53
Test name
Test status
Simulation time 46750192041 ps
CPU time 1086.84 seconds
Started Mar 03 12:42:16 PM PST 24
Finished Mar 03 01:00:23 PM PST 24
Peak memory 288876 kb
Host smart-e12f1d7a-f589-4a94-a63b-9eae1febc64e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464991773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3464991773
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1595131442
Short name T426
Test name
Test status
Simulation time 1657088951 ps
CPU time 139.6 seconds
Started Mar 03 12:42:12 PM PST 24
Finished Mar 03 12:44:32 PM PST 24
Peak memory 256368 kb
Host smart-3e7f3c2d-7a15-447c-994c-dae3a102fa56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951
31442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1595131442
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3903138427
Short name T114
Test name
Test status
Simulation time 446643328 ps
CPU time 16.23 seconds
Started Mar 03 12:42:18 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 252268 kb
Host smart-4c32d321-84ef-4ff9-bc92-dcb2893a0884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39031
38427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3903138427
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1107594377
Short name T637
Test name
Test status
Simulation time 55132665617 ps
CPU time 1184.62 seconds
Started Mar 03 12:42:13 PM PST 24
Finished Mar 03 01:01:58 PM PST 24
Peak memory 284308 kb
Host smart-1b125738-7659-48b2-af36-e7c95eae403e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107594377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1107594377
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.205419502
Short name T298
Test name
Test status
Simulation time 10118600659 ps
CPU time 381.16 seconds
Started Mar 03 12:42:24 PM PST 24
Finished Mar 03 12:48:46 PM PST 24
Peak memory 254876 kb
Host smart-d9b348e3-24fa-4a1b-923f-dd8746c53bab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205419502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.205419502
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.628701320
Short name T412
Test name
Test status
Simulation time 762982079 ps
CPU time 22.76 seconds
Started Mar 03 12:42:14 PM PST 24
Finished Mar 03 12:42:37 PM PST 24
Peak memory 248880 kb
Host smart-6d803e57-89a9-4663-b4d2-57ab07a88814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62870
1320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.628701320
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2955136441
Short name T543
Test name
Test status
Simulation time 142361752 ps
CPU time 14.03 seconds
Started Mar 03 12:42:18 PM PST 24
Finished Mar 03 12:42:32 PM PST 24
Peak memory 246980 kb
Host smart-6ab640c9-2265-4647-bfe9-0f9a8a3fd97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29551
36441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2955136441
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3928563965
Short name T54
Test name
Test status
Simulation time 536077527 ps
CPU time 24.99 seconds
Started Mar 03 12:42:23 PM PST 24
Finished Mar 03 12:42:48 PM PST 24
Peak memory 247520 kb
Host smart-13539651-75aa-4e41-af90-497275494443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39285
63965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3928563965
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.538126800
Short name T361
Test name
Test status
Simulation time 151084813 ps
CPU time 11.32 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:42:33 PM PST 24
Peak memory 248740 kb
Host smart-3b27e887-0a23-4ba7-8ac8-f239a73e84fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53812
6800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.538126800
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.321026257
Short name T258
Test name
Test status
Simulation time 220604890210 ps
CPU time 3109.63 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 01:34:10 PM PST 24
Peak memory 289452 kb
Host smart-80d7b1ad-085b-40d7-b47c-b6c250edbced
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321026257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.321026257
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.330945574
Short name T105
Test name
Test status
Simulation time 431969585906 ps
CPU time 5693.1 seconds
Started Mar 03 12:42:18 PM PST 24
Finished Mar 03 02:17:11 PM PST 24
Peak memory 306252 kb
Host smart-d6669d9c-0870-4e73-bfc3-62da3ce59ed9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330945574 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.330945574
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3147532801
Short name T424
Test name
Test status
Simulation time 25727567450 ps
CPU time 1182.73 seconds
Started Mar 03 12:42:23 PM PST 24
Finished Mar 03 01:02:06 PM PST 24
Peak memory 265220 kb
Host smart-b6197143-d9bd-4807-838d-28a052ec132a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147532801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3147532801
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.824516308
Short name T385
Test name
Test status
Simulation time 2175850574 ps
CPU time 115.17 seconds
Started Mar 03 12:42:24 PM PST 24
Finished Mar 03 12:44:20 PM PST 24
Peak memory 256468 kb
Host smart-bb1ebbb2-aa66-433f-a54f-74615f89db7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82451
6308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.824516308
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1002616070
Short name T508
Test name
Test status
Simulation time 172729615 ps
CPU time 19.6 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:42:41 PM PST 24
Peak memory 255276 kb
Host smart-54b08392-83a5-4f90-9854-824682a50cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10026
16070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1002616070
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2311377700
Short name T693
Test name
Test status
Simulation time 189024474290 ps
CPU time 2522.29 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 01:24:30 PM PST 24
Peak memory 288556 kb
Host smart-e2e0787b-bb7c-4ea0-953c-128883cc1662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311377700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2311377700
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.737998017
Short name T487
Test name
Test status
Simulation time 61997661973 ps
CPU time 1928.89 seconds
Started Mar 03 12:42:21 PM PST 24
Finished Mar 03 01:14:30 PM PST 24
Peak memory 272452 kb
Host smart-4912f1dd-6a71-4496-89bd-dba58b037861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737998017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.737998017
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2151132343
Short name T625
Test name
Test status
Simulation time 6483179814 ps
CPU time 266.29 seconds
Started Mar 03 12:42:24 PM PST 24
Finished Mar 03 12:46:51 PM PST 24
Peak memory 247472 kb
Host smart-ffb4e44b-66fc-4c01-b378-2a5109d22764
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151132343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2151132343
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.387263621
Short name T706
Test name
Test status
Simulation time 2905947506 ps
CPU time 47.39 seconds
Started Mar 03 12:42:13 PM PST 24
Finished Mar 03 12:43:01 PM PST 24
Peak memory 255796 kb
Host smart-d60b3a96-55e5-41e9-a622-a1652f524601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38726
3621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.387263621
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.3705548491
Short name T474
Test name
Test status
Simulation time 894548529 ps
CPU time 43.49 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:43:05 PM PST 24
Peak memory 255280 kb
Host smart-ca57c9ec-3ade-4c43-9065-b03cdbbea651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37055
48491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.3705548491
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3193262155
Short name T283
Test name
Test status
Simulation time 881230707 ps
CPU time 26.28 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:42:55 PM PST 24
Peak memory 255596 kb
Host smart-511b52f0-6f17-4a8a-968a-ba56e00c6ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31932
62155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3193262155
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.267336975
Short name T62
Test name
Test status
Simulation time 328185485 ps
CPU time 24.88 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 12:42:45 PM PST 24
Peak memory 248844 kb
Host smart-826ad30e-8a99-430f-ae9c-2cb1618b820d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26733
6975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.267336975
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3467759796
Short name T687
Test name
Test status
Simulation time 15689860342 ps
CPU time 241.17 seconds
Started Mar 03 12:42:22 PM PST 24
Finished Mar 03 12:46:23 PM PST 24
Peak memory 250788 kb
Host smart-359931fc-1c23-44ae-80d4-c605a3164218
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467759796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3467759796
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1771810715
Short name T643
Test name
Test status
Simulation time 106355757505 ps
CPU time 1055.14 seconds
Started Mar 03 12:42:21 PM PST 24
Finished Mar 03 12:59:56 PM PST 24
Peak memory 272572 kb
Host smart-cb2d4d1c-f95b-4f52-aeeb-1559b5105ae3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771810715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1771810715
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1995919656
Short name T429
Test name
Test status
Simulation time 2702545053 ps
CPU time 160.72 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 12:45:01 PM PST 24
Peak memory 256108 kb
Host smart-8beadeab-908e-4f95-a7a4-66200fe04cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19959
19656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1995919656
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1447644367
Short name T648
Test name
Test status
Simulation time 47418203 ps
CPU time 6.89 seconds
Started Mar 03 12:42:27 PM PST 24
Finished Mar 03 12:42:34 PM PST 24
Peak memory 253788 kb
Host smart-3e06212b-386f-4282-a107-349181ca850f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476
44367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1447644367
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1328407350
Short name T590
Test name
Test status
Simulation time 209530451183 ps
CPU time 3042.19 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 01:33:08 PM PST 24
Peak memory 289604 kb
Host smart-2c92a9b3-7472-4971-ae32-b92246f328b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328407350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1328407350
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2076295524
Short name T94
Test name
Test status
Simulation time 7824245992 ps
CPU time 834.12 seconds
Started Mar 03 12:42:23 PM PST 24
Finished Mar 03 12:56:17 PM PST 24
Peak memory 273184 kb
Host smart-48b1236c-f8f9-4b0a-8ca5-ccb602165739
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076295524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2076295524
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1768995660
Short name T47
Test name
Test status
Simulation time 1959714860 ps
CPU time 56.78 seconds
Started Mar 03 12:42:25 PM PST 24
Finished Mar 03 12:43:22 PM PST 24
Peak memory 255180 kb
Host smart-683fd037-c322-4841-91e5-bdb2822bb9a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17689
95660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1768995660
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1952204571
Short name T673
Test name
Test status
Simulation time 1505281543 ps
CPU time 20.45 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:42:50 PM PST 24
Peak memory 254328 kb
Host smart-69a26b5f-f61a-47e9-a56f-0ebfcfea8e83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19522
04571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1952204571
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.619379266
Short name T616
Test name
Test status
Simulation time 1786002874 ps
CPU time 58.86 seconds
Started Mar 03 12:42:20 PM PST 24
Finished Mar 03 12:43:19 PM PST 24
Peak memory 257052 kb
Host smart-cf7ce950-c6e0-4f61-9096-ddf180e765c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61937
9266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.619379266
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.419133350
Short name T250
Test name
Test status
Simulation time 140548942136 ps
CPU time 1975.8 seconds
Started Mar 03 12:42:26 PM PST 24
Finished Mar 03 01:15:22 PM PST 24
Peak memory 269464 kb
Host smart-746405a0-7113-46df-8f1b-f9630988ba8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419133350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.419133350
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2991182012
Short name T362
Test name
Test status
Simulation time 39426962522 ps
CPU time 2741.79 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 01:28:10 PM PST 24
Peak memory 289856 kb
Host smart-6acaf1e2-1587-4aa8-b2ad-6df239415126
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991182012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2991182012
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3974059125
Short name T83
Test name
Test status
Simulation time 8049094736 ps
CPU time 108.63 seconds
Started Mar 03 12:42:36 PM PST 24
Finished Mar 03 12:44:25 PM PST 24
Peak memory 256460 kb
Host smart-e20d4ead-2e5a-4ec8-a1d9-b53e6d35c1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39740
59125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3974059125
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.2804226419
Short name T614
Test name
Test status
Simulation time 452990326 ps
CPU time 35.91 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:43:04 PM PST 24
Peak memory 254524 kb
Host smart-5aeb3199-b70e-4469-806e-ecc8d163bbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28042
26419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.2804226419
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3840146873
Short name T333
Test name
Test status
Simulation time 11570785714 ps
CPU time 987.51 seconds
Started Mar 03 12:42:32 PM PST 24
Finished Mar 03 12:59:00 PM PST 24
Peak memory 273412 kb
Host smart-9e2cd8b5-257c-4362-aa7d-e8cf08d935f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840146873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3840146873
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1322852382
Short name T603
Test name
Test status
Simulation time 17901725162 ps
CPU time 376.52 seconds
Started Mar 03 12:42:35 PM PST 24
Finished Mar 03 12:48:51 PM PST 24
Peak memory 248024 kb
Host smart-ece3d95c-9765-4cf0-92f7-fc828d49f911
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322852382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1322852382
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1965296320
Short name T546
Test name
Test status
Simulation time 1195876058 ps
CPU time 30.71 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:42:59 PM PST 24
Peak memory 248876 kb
Host smart-9e6d1d65-0cb1-4f7f-9bdc-309e18c67f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19652
96320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1965296320
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2789405451
Short name T514
Test name
Test status
Simulation time 1092547977 ps
CPU time 21.06 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:42:49 PM PST 24
Peak memory 253196 kb
Host smart-0bfefb9b-e2e6-4850-9e6d-0ab688fcfb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27894
05451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2789405451
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2463102683
Short name T349
Test name
Test status
Simulation time 769432275 ps
CPU time 50.13 seconds
Started Mar 03 12:42:28 PM PST 24
Finished Mar 03 12:43:18 PM PST 24
Peak memory 254656 kb
Host smart-6c0e822f-fcad-428b-99ba-a3eea6ec1e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24631
02683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2463102683
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1564382083
Short name T668
Test name
Test status
Simulation time 250765593 ps
CPU time 5.31 seconds
Started Mar 03 12:42:30 PM PST 24
Finished Mar 03 12:42:35 PM PST 24
Peak memory 248776 kb
Host smart-be30fc52-fee5-4b21-aecd-250f6d0c9a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
82083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1564382083
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1166093491
Short name T378
Test name
Test status
Simulation time 27058276367 ps
CPU time 129.2 seconds
Started Mar 03 12:42:29 PM PST 24
Finished Mar 03 12:44:39 PM PST 24
Peak memory 257008 kb
Host smart-4546b88b-5c52-4174-9102-61371ad9a87d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166093491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1166093491
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2965188864
Short name T113
Test name
Test status
Simulation time 443061293626 ps
CPU time 2791.81 seconds
Started Mar 03 12:42:34 PM PST 24
Finished Mar 03 01:29:07 PM PST 24
Peak memory 305772 kb
Host smart-1b0f76d8-ae30-4bd4-961d-da6e82318c7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965188864 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2965188864
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1435568347
Short name T209
Test name
Test status
Simulation time 51108248 ps
CPU time 2.2 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 248920 kb
Host smart-b8cbe14b-5252-4f97-a0f3-5a7c9ab69b61
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1435568347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1435568347
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3102084129
Short name T513
Test name
Test status
Simulation time 51094973328 ps
CPU time 1865.82 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 01:12:30 PM PST 24
Peak memory 282460 kb
Host smart-d49d07b1-6134-4364-ad60-0906093076b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102084129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3102084129
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4250362571
Short name T494
Test name
Test status
Simulation time 1644065676 ps
CPU time 9.38 seconds
Started Mar 03 12:41:13 PM PST 24
Finished Mar 03 12:41:23 PM PST 24
Peak memory 240568 kb
Host smart-91680507-15fe-457f-ba2f-25ed5289b796
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4250362571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4250362571
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.254153016
Short name T540
Test name
Test status
Simulation time 498881138 ps
CPU time 44.14 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:42:01 PM PST 24
Peak memory 256392 kb
Host smart-d1482a2e-f185-4b6d-9c3a-eb3053f30f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25415
3016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.254153016
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2172081249
Short name T81
Test name
Test status
Simulation time 550162712 ps
CPU time 39.34 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 12:42:00 PM PST 24
Peak memory 254452 kb
Host smart-cbc0947f-6c94-48ee-af55-9081e18e2e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21720
81249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2172081249
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2852423238
Short name T320
Test name
Test status
Simulation time 45405066527 ps
CPU time 717.06 seconds
Started Mar 03 12:41:08 PM PST 24
Finished Mar 03 12:53:06 PM PST 24
Peak memory 265224 kb
Host smart-3bbe166d-6032-4f7c-be96-d6e5d5f48cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852423238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2852423238
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.45752500
Short name T387
Test name
Test status
Simulation time 41956127335 ps
CPU time 1040.48 seconds
Started Mar 03 12:41:31 PM PST 24
Finished Mar 03 12:58:52 PM PST 24
Peak memory 289048 kb
Host smart-0e968ca2-f2fe-4c2c-99e5-89ea4f31cfa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45752500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.45752500
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1856609209
Short name T520
Test name
Test status
Simulation time 559592439 ps
CPU time 33.12 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:42:04 PM PST 24
Peak memory 248832 kb
Host smart-fc3e6212-6212-41d5-92e8-cb8c4c290588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18566
09209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1856609209
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2846621244
Short name T610
Test name
Test status
Simulation time 981557711 ps
CPU time 61.8 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 12:42:30 PM PST 24
Peak memory 255748 kb
Host smart-05080a07-4bd6-4fbb-87fa-6fb5d356ed69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28466
21244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2846621244
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3421152420
Short name T639
Test name
Test status
Simulation time 2119135338 ps
CPU time 61.3 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:42:20 PM PST 24
Peak memory 248500 kb
Host smart-539e2f95-2880-44c6-85db-c104d7d11797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34211
52420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3421152420
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3662055036
Short name T416
Test name
Test status
Simulation time 5934734651 ps
CPU time 115.08 seconds
Started Mar 03 12:41:34 PM PST 24
Finished Mar 03 12:43:29 PM PST 24
Peak memory 257140 kb
Host smart-ef7d82f1-cfd6-42f7-b7b4-735650b755d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662055036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3662055036
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.407671603
Short name T218
Test name
Test status
Simulation time 19709843 ps
CPU time 2.82 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:20 PM PST 24
Peak memory 248948 kb
Host smart-57414622-983a-441b-a236-7a93fea58177
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=407671603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.407671603
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3832965422
Short name T445
Test name
Test status
Simulation time 14971953353 ps
CPU time 671.99 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:52:34 PM PST 24
Peak memory 265236 kb
Host smart-67f0b2ab-8f4b-4b90-a5c6-d9a418144142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832965422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3832965422
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.40550392
Short name T417
Test name
Test status
Simulation time 1035153289 ps
CPU time 9.82 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:19 PM PST 24
Peak memory 240568 kb
Host smart-94d4de9a-694c-49d0-b8be-05d7412cc2be
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=40550392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.40550392
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1722885438
Short name T630
Test name
Test status
Simulation time 7925421836 ps
CPU time 155.71 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:43:58 PM PST 24
Peak memory 256436 kb
Host smart-b11b3adb-c82e-4617-b127-c30ee5f18fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
85438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1722885438
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1806205735
Short name T499
Test name
Test status
Simulation time 3247850978 ps
CPU time 50.59 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 12:42:24 PM PST 24
Peak memory 255404 kb
Host smart-dd90fd13-44a6-478a-b34b-01b237025e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18062
05735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1806205735
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2315091484
Short name T640
Test name
Test status
Simulation time 18466013143 ps
CPU time 1403.45 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 01:04:33 PM PST 24
Peak memory 288672 kb
Host smart-0e354bf2-dc1d-48cf-b169-cfa2124e656a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315091484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2315091484
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2538115166
Short name T93
Test name
Test status
Simulation time 49267166232 ps
CPU time 1125.72 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 01:00:05 PM PST 24
Peak memory 272836 kb
Host smart-b37af20b-3fff-42ef-a1d8-0aa5c734fd7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538115166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2538115166
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.711237922
Short name T666
Test name
Test status
Simulation time 9939234396 ps
CPU time 405.99 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:48:04 PM PST 24
Peak memory 247648 kb
Host smart-38b87822-f51d-4c64-aeda-a7d0b43f4d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711237922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.711237922
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1797471347
Short name T537
Test name
Test status
Simulation time 160619083 ps
CPU time 15.05 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:32 PM PST 24
Peak memory 255340 kb
Host smart-721f285f-0718-4181-b2a9-7bf5fd0e491d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17974
71347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1797471347
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3585387220
Short name T579
Test name
Test status
Simulation time 2039191998 ps
CPU time 35.41 seconds
Started Mar 03 12:41:40 PM PST 24
Finished Mar 03 12:42:15 PM PST 24
Peak memory 255436 kb
Host smart-3eb31878-0707-416f-a9e7-9c61063ffa64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35853
87220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3585387220
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.204753120
Short name T395
Test name
Test status
Simulation time 831042685 ps
CPU time 29.13 seconds
Started Mar 03 12:41:31 PM PST 24
Finished Mar 03 12:42:00 PM PST 24
Peak memory 254520 kb
Host smart-992a620f-1922-4e42-8c54-6cb2279b3951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20475
3120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.204753120
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2983060744
Short name T680
Test name
Test status
Simulation time 948874828 ps
CPU time 47.98 seconds
Started Mar 03 12:41:23 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 255204 kb
Host smart-8147688c-a5e7-4287-b0d5-bc1e9f7624e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29830
60744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2983060744
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3441588161
Short name T263
Test name
Test status
Simulation time 162004395798 ps
CPU time 1730.96 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 01:10:09 PM PST 24
Peak memory 283300 kb
Host smart-fbf642f7-6963-41f8-9a0d-666182206a0a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441588161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3441588161
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.103164387
Short name T213
Test name
Test status
Simulation time 25131678 ps
CPU time 2.33 seconds
Started Mar 03 12:41:25 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 257088 kb
Host smart-8901c888-a2b4-4869-a06c-5254316777ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=103164387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.103164387
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.912182601
Short name T531
Test name
Test status
Simulation time 11742168005 ps
CPU time 654.79 seconds
Started Mar 03 12:41:28 PM PST 24
Finished Mar 03 12:52:23 PM PST 24
Peak memory 265232 kb
Host smart-92839cc2-f998-4282-a386-6ff80d5bc5b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912182601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.912182601
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.953534698
Short name T701
Test name
Test status
Simulation time 614385577 ps
CPU time 9.75 seconds
Started Mar 03 12:41:52 PM PST 24
Finished Mar 03 12:42:02 PM PST 24
Peak memory 240552 kb
Host smart-7ff94a5b-00a1-4499-b809-faebe281f7eb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=953534698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.953534698
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1834009990
Short name T631
Test name
Test status
Simulation time 19322636390 ps
CPU time 197.08 seconds
Started Mar 03 12:41:45 PM PST 24
Finished Mar 03 12:45:03 PM PST 24
Peak memory 256944 kb
Host smart-8a815a33-8e05-49f6-bf0c-2f6e7a1a4601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18340
09990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1834009990
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3313282321
Short name T259
Test name
Test status
Simulation time 227015870 ps
CPU time 18.28 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:41:36 PM PST 24
Peak memory 255616 kb
Host smart-74170dc7-d158-4d5c-8abd-3fb3c412a96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33132
82321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3313282321
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3764425585
Short name T485
Test name
Test status
Simulation time 21426131213 ps
CPU time 1778.61 seconds
Started Mar 03 12:41:15 PM PST 24
Finished Mar 03 01:10:54 PM PST 24
Peak memory 289232 kb
Host smart-a308d48f-9ddb-4965-8a01-17bced7bf94d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764425585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3764425585
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2679914418
Short name T108
Test name
Test status
Simulation time 132978207839 ps
CPU time 2461.54 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 01:22:35 PM PST 24
Peak memory 289276 kb
Host smart-98e0aa53-7465-470f-bcab-be4fb65cf77d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679914418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2679914418
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1561535000
Short name T651
Test name
Test status
Simulation time 7556288510 ps
CPU time 318.27 seconds
Started Mar 03 12:41:36 PM PST 24
Finished Mar 03 12:46:55 PM PST 24
Peak memory 246896 kb
Host smart-a1013045-a313-4b9e-831f-0562ae1aa80c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561535000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1561535000
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.116375247
Short name T564
Test name
Test status
Simulation time 13471827754 ps
CPU time 40.77 seconds
Started Mar 03 12:41:13 PM PST 24
Finished Mar 03 12:41:54 PM PST 24
Peak memory 248836 kb
Host smart-5064eddf-aad1-4dce-9d0b-85435cb526d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11637
5247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.116375247
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4272686351
Short name T101
Test name
Test status
Simulation time 1497932796 ps
CPU time 19.96 seconds
Started Mar 03 12:41:30 PM PST 24
Finished Mar 03 12:41:50 PM PST 24
Peak memory 254516 kb
Host smart-b6e53517-7466-4dda-9c8f-feafbd6bc917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42726
86351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4272686351
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3626652077
Short name T61
Test name
Test status
Simulation time 696464457 ps
CPU time 35.39 seconds
Started Mar 03 12:41:27 PM PST 24
Finished Mar 03 12:42:03 PM PST 24
Peak memory 248884 kb
Host smart-f93d8467-90d9-4e4e-96f7-c18fc024fcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36266
52077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3626652077
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2326731768
Short name T21
Test name
Test status
Simulation time 12260944784 ps
CPU time 38.52 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:58 PM PST 24
Peak memory 248848 kb
Host smart-ed58b6ad-a9da-4397-adbe-1a58c80b01d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23267
31768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2326731768
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3959294152
Short name T585
Test name
Test status
Simulation time 64967687604 ps
CPU time 2051.68 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 01:15:29 PM PST 24
Peak memory 281596 kb
Host smart-7148ef79-9d32-4261-9103-009ece76d692
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959294152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3959294152
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1183887212
Short name T214
Test name
Test status
Simulation time 64927685 ps
CPU time 2.73 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:22 PM PST 24
Peak memory 248916 kb
Host smart-4dee159e-03b8-42d5-a627-a441d6115ecd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1183887212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1183887212
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1113424510
Short name T390
Test name
Test status
Simulation time 671228163 ps
CPU time 15.49 seconds
Started Mar 03 12:41:32 PM PST 24
Finished Mar 03 12:41:48 PM PST 24
Peak memory 248784 kb
Host smart-c78ebe17-db1e-4c82-82c2-0eeaa9a6ad13
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1113424510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1113424510
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3127990874
Short name T409
Test name
Test status
Simulation time 21297250682 ps
CPU time 139.11 seconds
Started Mar 03 12:40:59 PM PST 24
Finished Mar 03 12:43:18 PM PST 24
Peak memory 248820 kb
Host smart-ca24dce0-f012-4312-aa3f-63266ee0299b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31279
90874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3127990874
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3026218511
Short name T375
Test name
Test status
Simulation time 383175791 ps
CPU time 30.03 seconds
Started Mar 03 12:41:33 PM PST 24
Finished Mar 03 12:42:04 PM PST 24
Peak memory 254780 kb
Host smart-252416f2-f833-4caf-a92f-1f29c4db6c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
18511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3026218511
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.4020271210
Short name T329
Test name
Test status
Simulation time 281387758902 ps
CPU time 2748.61 seconds
Started Mar 03 12:41:05 PM PST 24
Finished Mar 03 01:26:54 PM PST 24
Peak memory 287760 kb
Host smart-f71ee3b6-edc1-46c7-a71e-bbd6b9314433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020271210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.4020271210
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2239406425
Short name T682
Test name
Test status
Simulation time 107763162749 ps
CPU time 2462.52 seconds
Started Mar 03 12:41:24 PM PST 24
Finished Mar 03 01:22:27 PM PST 24
Peak memory 289572 kb
Host smart-544d1697-a351-47ae-bd30-083ebcae47c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239406425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2239406425
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2917278881
Short name T309
Test name
Test status
Simulation time 77944044400 ps
CPU time 594.18 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:51:04 PM PST 24
Peak memory 246984 kb
Host smart-6ad8cf33-8b39-45be-b00d-3eeb090a607f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917278881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2917278881
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3206649158
Short name T120
Test name
Test status
Simulation time 1341381779 ps
CPU time 44.77 seconds
Started Mar 03 12:41:21 PM PST 24
Finished Mar 03 12:42:06 PM PST 24
Peak memory 248684 kb
Host smart-0795e1c5-cf72-4685-a73f-ee3c74dbb7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
49158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3206649158
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.169567396
Short name T441
Test name
Test status
Simulation time 946069040 ps
CPU time 21.12 seconds
Started Mar 03 12:41:06 PM PST 24
Finished Mar 03 12:41:27 PM PST 24
Peak memory 255592 kb
Host smart-d0326383-c46b-486a-bb41-6eb57be15a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16956
7396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.169567396
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1571584698
Short name T566
Test name
Test status
Simulation time 8023240504 ps
CPU time 62.84 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:42:12 PM PST 24
Peak memory 255236 kb
Host smart-c4410b75-d219-4c69-af14-7caf35229e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15715
84698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1571584698
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1983048624
Short name T570
Test name
Test status
Simulation time 1443299964 ps
CPU time 12.4 seconds
Started Mar 03 12:41:16 PM PST 24
Finished Mar 03 12:41:28 PM PST 24
Peak memory 253664 kb
Host smart-a5770113-a318-405d-9c43-88d59b4b0b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19830
48624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1983048624
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2765045431
Short name T681
Test name
Test status
Simulation time 36375530206 ps
CPU time 1912.1 seconds
Started Mar 03 12:41:22 PM PST 24
Finished Mar 03 01:13:15 PM PST 24
Peak memory 289776 kb
Host smart-7f7f7e82-d16e-4ca2-a61b-0b7d16d8150e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765045431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2765045431
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3561738268
Short name T253
Test name
Test status
Simulation time 10196808887 ps
CPU time 705.45 seconds
Started Mar 03 12:41:31 PM PST 24
Finished Mar 03 12:53:16 PM PST 24
Peak memory 272760 kb
Host smart-c8cafae6-858f-427a-a00b-268a7d9929f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561738268 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3561738268
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.253997329
Short name T203
Test name
Test status
Simulation time 39940962 ps
CPU time 2.16 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:21 PM PST 24
Peak memory 248916 kb
Host smart-f8ff9884-38f8-4814-a511-906455fb8ec9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=253997329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.253997329
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1640018879
Short name T595
Test name
Test status
Simulation time 26595573618 ps
CPU time 1850.23 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 01:12:11 PM PST 24
Peak memory 273128 kb
Host smart-e90a16b1-3f1d-458d-b16f-2b230f83dc3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640018879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1640018879
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3424612984
Short name T622
Test name
Test status
Simulation time 1042118350 ps
CPU time 23.75 seconds
Started Mar 03 12:41:19 PM PST 24
Finished Mar 03 12:41:43 PM PST 24
Peak memory 240540 kb
Host smart-91b6e2d2-3fa2-42fc-b30d-5109b61fa04e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3424612984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3424612984
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3451634880
Short name T384
Test name
Test status
Simulation time 1697308507 ps
CPU time 137.65 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:43:26 PM PST 24
Peak memory 256488 kb
Host smart-ebfac784-d8e3-441a-9948-6e44f621e289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
34880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3451634880
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1435815526
Short name T477
Test name
Test status
Simulation time 279896402 ps
CPU time 15.09 seconds
Started Mar 03 12:41:49 PM PST 24
Finished Mar 03 12:42:06 PM PST 24
Peak memory 255236 kb
Host smart-135970c0-a534-4cfd-8e49-7444adf36da0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14358
15526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1435815526
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.1097207818
Short name T621
Test name
Test status
Simulation time 27519146807 ps
CPU time 1518.55 seconds
Started Mar 03 12:41:20 PM PST 24
Finished Mar 03 01:06:39 PM PST 24
Peak memory 272872 kb
Host smart-9226fcf7-b78f-4437-99b9-820c65059bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097207818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.1097207818
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1410888296
Short name T593
Test name
Test status
Simulation time 26822801010 ps
CPU time 615.27 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:51:34 PM PST 24
Peak memory 265208 kb
Host smart-94df8b45-ec56-41a0-a60b-5e735b9a668f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410888296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1410888296
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.400522472
Short name T318
Test name
Test status
Simulation time 39731345360 ps
CPU time 333.71 seconds
Started Mar 03 12:41:17 PM PST 24
Finished Mar 03 12:46:52 PM PST 24
Peak memory 246860 kb
Host smart-16b3f8a6-5c35-456a-8ea7-61799c60be0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400522472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.400522472
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2856886040
Short name T536
Test name
Test status
Simulation time 2205345119 ps
CPU time 31.7 seconds
Started Mar 03 12:41:09 PM PST 24
Finished Mar 03 12:41:41 PM PST 24
Peak memory 255664 kb
Host smart-315319e5-a839-4756-a468-fe98114f79f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28568
86040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2856886040
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.565813190
Short name T584
Test name
Test status
Simulation time 256105773 ps
CPU time 21.4 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 12:41:40 PM PST 24
Peak memory 247092 kb
Host smart-ac50dd40-b960-4fdd-b6df-e8b1a9b660e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56581
3190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.565813190
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1377032028
Short name T268
Test name
Test status
Simulation time 142485220 ps
CPU time 15.75 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 12:41:53 PM PST 24
Peak memory 254464 kb
Host smart-000f3c5e-abec-41e1-87ec-a00b02797306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13770
32028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1377032028
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4111266775
Short name T589
Test name
Test status
Simulation time 69808440 ps
CPU time 5 seconds
Started Mar 03 12:41:37 PM PST 24
Finished Mar 03 12:41:42 PM PST 24
Peak memory 240576 kb
Host smart-401250e4-5a2b-40fa-8d67-b392a9bc5be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41112
66775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4111266775
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.4236057555
Short name T558
Test name
Test status
Simulation time 21251294116 ps
CPU time 1942.91 seconds
Started Mar 03 12:41:18 PM PST 24
Finished Mar 03 01:13:42 PM PST 24
Peak memory 305276 kb
Host smart-cea0cd04-6bf0-4ecb-9e49-fba1a2a75cda
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236057555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.4236057555
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.3009911205
Short name T229
Test name
Test status
Simulation time 328058998425 ps
CPU time 1992.76 seconds
Started Mar 03 12:41:40 PM PST 24
Finished Mar 03 01:14:53 PM PST 24
Peak memory 289260 kb
Host smart-26a26150-79dc-4df3-b476-09379150ff58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009911205 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3009911205
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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