Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	63501	1			T7	7		T8	17		T16	446
class_i[0x1]	31873	1			T7	7		T15	22		T8	8
class_i[0x2]	55205	1			T7	1157		T15	2142		T16	764
class_i[0x3]	55906	1			T1	2		T7	4363		T15	1

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	53294	1			T1	1		T7	1734		T15	538
alert[0x1]	47022	1			T7	1071		T15	547		T8	7
alert[0x2]	52222	1			T1	1		T7	1604		T15	526
alert[0x3]	53947	1			T7	1125		T15	554		T8	6

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

206216

1

T7

5534

T15

2165

T8

15

esc_ping_fail

269

1

T1

2

T8

10

T9

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	53219	1			T7	1734		T15	538		T8	3
esc_integrity_fail	alert[0x1]	46959	1			T7	1071		T15	547		T8	5
esc_integrity_fail	alert[0x2]	52153	1			T7	1604		T15	526		T8	4
esc_integrity_fail	alert[0x3]	53885	1			T7	1125		T15	554		T8	3
esc_ping_fail	alert[0x0]	75	1			T1	1		T8	2		T67	1
esc_ping_fail	alert[0x1]	63	1			T8	2		T9	1		T196	3
esc_ping_fail	alert[0x2]	69	1			T1	1		T8	3		T196	1
esc_ping_fail	alert[0x3]	62	1			T8	3		T9	1		T196	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	63415	1			T7	7		T8	15		T16	446
esc_integrity_fail	class_i[0x1]	31822	1			T7	7		T15	22		T16	883
esc_integrity_fail	class_i[0x2]	55128	1			T7	1157		T15	2142		T16	764
esc_integrity_fail	class_i[0x3]	55851	1			T7	4363		T15	1		T16	34
esc_ping_fail	class_i[0x0]	86	1			T8	2		T67	1		T210	10
esc_ping_fail	class_i[0x1]	51	1			T8	8		T9	2		T196	6
esc_ping_fail	class_i[0x2]	77	1			T297	6		T98	9		T241	8
esc_ping_fail	class_i[0x3]	55	1			T1	2		T308	2		T98	1