Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	697426547	0	0	627
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	697426547	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	697426547	697240114	0	0
tb.dut.CheckAccuCntDw	0	0	627	627	0	0
tb.dut.CheckEscCntDw	0	0	627	627	0	0
tb.dut.CheckNAlerts	0	0	627	627	0	0
tb.dut.CheckNClasses	0	0	627	627	0	0
tb.dut.CheckNEscSev	0	0	627	627	0	0
tb.dut.CrashdumpKnownO_A	0	0	697426547	697240114	0	0
tb.dut.EdnKnownO_A	0	0	697426547	697240114	0	0
tb.dut.EscPKnownO_A	0	0	697426547	697240114	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	697426547	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	697426547	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	697426547	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	697426547	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	697426547	90	0	0
tb.dut.IrqAKnownO_A	0	0	697426547	697240114	0	0
tb.dut.IrqBKnownO_A	0	0	697426547	697240114	0	0
tb.dut.IrqCKnownO_A	0	0	697426547	697240114	0	0
tb.dut.IrqDKnownO_A	0	0	697426547	697240114	0	0
tb.dut.TlAReadyKnownO_A	0	0	697426547	697240114	0	0
tb.dut.TlDValidKnownO_A	0	0	697426547	697240114	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	725455826	2675047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	725455826	23623	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	725455826	23439	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	725455826	23275	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	725455826	23052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	725455826	22938	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	725455826	23799	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	725455826	23187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	725455826	23513	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	725455826	23134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	725455826	23559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	725455826	23972	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	725455826	23193	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	725455826	24358	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	725455826	24386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	725455826	23394	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	725455826	24449	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	725455826	23004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	725455826	23217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	725455826	23615	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	725455826	24006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	725455826	23763	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	725455826	23253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	725455826	23175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	725455826	23120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	725455826	22847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	725455826	24601	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	725455826	23246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	725455826	23577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	725455826	24606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	725455826	24266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	725455826	23525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	725455826	23550	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	725455826	23523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	725455826	23738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	725455826	23208	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	725455826	23157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	725455826	24543	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	725455826	22936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	725455826	24223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	725455826	24073	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	725455826	24633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	725455826	24219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	725455826	23691	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	725455826	22998	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	725455826	23523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	725455826	23544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	725455826	23205	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	725455826	23541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	725455826	23893	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	725455826	23364	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	725455826	23182	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	725455826	23062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	725455826	23701	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	725455826	24398	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	725455826	23831	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	725455826	24296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	725455826	24458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	725455826	22753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	725455826	23440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	725455826	23678	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	725455826	23423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	725455826	23474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	725455826	24350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	725455826	24632	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	725455826	23129	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	725455826	24321	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	725455826	23671	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	725455826	23645	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	725455826	24471	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	725455826	44080	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	725455826	23552	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	725455826	23308	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	725455826	24608	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	725455826	23192	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	725455826	24376	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	725455826	23084	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	725455826	23421	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	725455826	24114	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	697426547	5550	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	697426547	206710	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	697426547	369261454	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	697426547	329	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	697426547	832	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	697426547	49	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	697426547	394	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	697146246	257086939	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	697426547	941	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	697426547	915	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	697426547	892	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	697426547	874	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	697426547	863	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	697426547	106126	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	697426547	731	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	697426547	82	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	697426547	1608	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	697426547	1338	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	697426547	697240114	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	697426547	2947	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	697426547	172381	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	697426547	400050755	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	697426547	277	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	697426547	520	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	697426547	25	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	697426547	234	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	697146246	300638882	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	697426547	596	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	697426547	588	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	697426547	576	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	697426547	569	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	697426547	623	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	697426547	82320	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	697426547	537	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	697426547	59	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	697426547	1625	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	697426547	1355	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	697426547	697240114	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	697426547	2767	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	697426547	169000	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	697426547	394460973	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	697426547	273	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	697426547	535	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	697426547	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	697426547	255	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	697146246	291905940	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	697426547	615	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	697426547	599	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	697426547	585	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	697426547	578	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	697426547	1346	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	697426547	158132	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	697426547	1255	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	697426547	64	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	697426547	1596	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	697426547	1326	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	697426547	697240114	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	697426547	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	697426547	2422	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	697426547	168030	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	697426547	390870430	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	697426547	302	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	697426547	489	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	697426547	27	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	697426547	231	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	697146246	303115397	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	697426547	563	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	697426547	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	697426547	535	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	697426547	526	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	697426547	1000	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	697426547	104201	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	697426547	910	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	697426547	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	697426547	1629	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	697426547	1359	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	697426547	697240114	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	725455826	125505233	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	725455826	724793695	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	725455826	724793695	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	725455826	190946654	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	725455826	724793695	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	725455826	724793695	0	0
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tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
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tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0

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