Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	159	1			T14	1		T16	2		T21	1
index[0x1]	165	1			T5	1		T17	1		T14	1
index[0x2]	182	1			T17	1		T7	2		T14	3
index[0x3]	152	1			T14	1		T8	1		T45	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	213	1			T5	1		T7	2		T44	1
lens_less_than_1000[1]	131	1			T14	3		T8	2		T21	1
lens_less_than_1000[2]	95	1			T16	1		T45	1		T20	1
lens_less_than_1000[3]	54	1			T14	1		T16	1		T21	2
lens_less_than_1000[4]	53	1			T14	1		T92	2		T86	1
lens_less_than_1000[5]	26	1			T48	1		T52	1		T57	1
lens_less_than_1000[6]	42	1			T17	1		T14	1		T28	1
lens_less_than_1000[7]	26	1			T17	1		T16	1		T45	1
lens_less_than_1000[8]	5	1			T266	1		T267	1		T200	1
lens_less_than_1000[9]	7	1			T268	1		T46	1		T248	1
len_2	6	1			T27	1		T105	1		T245	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[8]]	0	1	1
[index[0x1]]	[lens_less_than_1000[9] , len_2]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	49	1			T16	1		T21	1		T28	2
index[0x0]	lens_less_than_1000[1]	30	1			T68	1		T23	2		T198	1
index[0x0]	lens_less_than_1000[2]	19	1			T51	1		T269	1		T270	1
index[0x0]	lens_less_than_1000[3]	21	1			T16	1		T25	1		T71	1
index[0x0]	lens_less_than_1000[4]	12	1			T92	1		T271	1		T272	1
index[0x0]	lens_less_than_1000[5]	7	1			T48	1		T273	1		T274	1
index[0x0]	lens_less_than_1000[6]	9	1			T14	1		T22	1		T275	1
index[0x0]	lens_less_than_1000[7]	8	1			T52	1		T58	1		T276	4
index[0x0]	lens_less_than_1000[9]	3	1			T268	1		T37	1		T277	1
index[0x0]	len_2	1	1			T27	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	56	1			T5	1		T44	1		T268	1
index[0x1]	lens_less_than_1000[1]	30	1			T14	1		T8	1		T72	1
index[0x1]	lens_less_than_1000[2]	25	1			T16	1		T45	1		T23	1
index[0x1]	lens_less_than_1000[3]	10	1			T278	1		T110	1		T55	1
index[0x1]	lens_less_than_1000[4]	20	1			T54	1		T55	1		T57	3
index[0x1]	lens_less_than_1000[5]	7	1			T279	1		T244	1		T280	3
index[0x1]	lens_less_than_1000[6]	14	1			T17	1		T110	1		T281	1
index[0x1]	lens_less_than_1000[7]	2	1			T89	1		T282	1		-	-
index[0x1]	lens_less_than_1000[8]	1	1			T266	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	58	1			T7	2		T16	1		T28	1
index[0x2]	lens_less_than_1000[1]	35	1			T14	1		T51	1		T54	1
index[0x2]	lens_less_than_1000[2]	33	1			T20	1		T92	2		T86	5
index[0x2]	lens_less_than_1000[3]	8	1			T14	1		T21	1		T283	1
index[0x2]	lens_less_than_1000[4]	14	1			T14	1		T92	1		T105	2
index[0x2]	lens_less_than_1000[5]	7	1			T57	1		T284	1		T109	1
index[0x2]	lens_less_than_1000[6]	13	1			T28	1		T54	1		T285	9
index[0x2]	lens_less_than_1000[7]	9	1			T17	1		T16	1		T27	1
index[0x2]	lens_less_than_1000[8]	1	1			T264	1		-	-		-	-
index[0x2]	lens_less_than_1000[9]	3	1			T46	1		T248	1		T286	1
index[0x2]	len_2	1	1			T245	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	50	1			T29	1		T28	4		T46	1
index[0x3]	lens_less_than_1000[1]	36	1			T14	1		T8	1		T21	1
index[0x3]	lens_less_than_1000[2]	18	1			T47	1		T92	1		T55	1
index[0x3]	lens_less_than_1000[3]	15	1			T21	1		T68	1		T56	1
index[0x3]	lens_less_than_1000[4]	7	1			T86	1		T287	1		T56	1
index[0x3]	lens_less_than_1000[5]	5	1			T52	1		T266	1		T37	1
index[0x3]	lens_less_than_1000[6]	6	1			T110	1		T55	1		T203	1
index[0x3]	lens_less_than_1000[7]	7	1			T45	1		T47	1		T288	1
index[0x3]	lens_less_than_1000[8]	3	1			T267	1		T200	1		T289	1
index[0x3]	lens_less_than_1000[9]	1	1			T290	1		-	-		-	-
index[0x3]	len_2	4	1			T105	1		T291	1		T292	1