Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	82	1			T7	2		T16	3		T20	1
class_index[0x1]	59	1			T7	1		T16	1		T46	1
class_index[0x2]	64	1			T27	1		T28	1		T23	1
class_index[0x3]	62	1			T16	1		T46	1		T23	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	86	1			T20	1		T27	2		T28	1
intr_timeout_cnt[1]	70	1			T73	1		T23	2		T47	3
intr_timeout_cnt[2]	36	1			T7	2		T16	2		T22	1
intr_timeout_cnt[3]	17	1			T16	1		T46	1		T23	1
intr_timeout_cnt[4]	15	1			T7	1		T16	2		T106	4
intr_timeout_cnt[5]	8	1			T46	1		T203	1		T247	1
intr_timeout_cnt[6]	13	1			T54	1		T81	1		T57	2
intr_timeout_cnt[7]	9	1			T57	1		T248	1		T102	1
intr_timeout_cnt[8]	7	1			T46	1		T202	1		T105	1
intr_timeout_cnt[9]	6	1			T78	1		T101	1		T244	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[4]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	22	1			T20	1		T27	1		T46	1
class_index[0x0]	intr_timeout_cnt[1]	28	1			T23	1		T47	1		T57	1
class_index[0x0]	intr_timeout_cnt[2]	12	1			T7	2		T16	1		T22	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T46	1		T52	1		T57	1
class_index[0x0]	intr_timeout_cnt[4]	8	1			T16	2		T78	1		T197	1
class_index[0x0]	intr_timeout_cnt[5]	1	1			T249	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	3	1			T250	1		T203	1		T40	1
class_index[0x0]	intr_timeout_cnt[8]	3	1			T202	1		T105	1		T251	1
class_index[0x1]	intr_timeout_cnt[0]	22	1			T77	1		T54	1		T80	1
class_index[0x1]	intr_timeout_cnt[1]	12	1			T73	1		T23	1		T47	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T23	1		T80	1		T103	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T16	1		T80	1		T245	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T7	1		T206	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	3	1			T46	1		T203	1		T252	1
class_index[0x1]	intr_timeout_cnt[6]	4	1			T57	2		T253	1		T254	1
class_index[0x1]	intr_timeout_cnt[7]	4	1			T61	2		T255	1		T256	1
class_index[0x2]	intr_timeout_cnt[0]	20	1			T27	1		T28	1		T79	1
class_index[0x2]	intr_timeout_cnt[1]	17	1			T47	1		T75	1		T76	1
class_index[0x2]	intr_timeout_cnt[2]	10	1			T257	1		T24	1		T258	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T23	1		T81	1		T247	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T259	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	3	1			T54	1		T253	1		T256	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T248	1		T247	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T37	2		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	5	1			T78	1		T101	1		T244	1
class_index[0x3]	intr_timeout_cnt[0]	22	1			T23	1		T80	1		T81	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T107	1		T260	2		T261	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T16	1		T248	1		T262	1
class_index[0x3]	intr_timeout_cnt[3]	4	1			T50	2		T54	1		T252	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T106	4		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T247	1		T34	1		T263	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T81	1		T177	1		T197	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T57	1		T102	1		T101	1
class_index[0x3]	intr_timeout_cnt[8]	2	1			T46	1		T253	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T264	1		-	-		-	-