Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	342289	1			T1	21		T2	13		T3	1417
all_values[1]	342289	1			T1	21		T2	13		T3	1417
all_values[2]	342289	1			T1	21		T2	13		T3	1417
all_values[3]	342289	1			T1	21		T2	13		T3	1417

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

681071

1

T2

22

T3

2763

T5

11

auto[1]

688085

1

T1

84

T2

30

T3

2905

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

815187

1

T1

74

T2

29

T3

4231

auto[1]

553969

1

T1

10

T2

23

T3

1437

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97504	1			T2	3		T3	532		T5	1
all_values[0]	auto[0]	auto[1]	72849	1			T2	2		T3	185		T5	1
all_values[0]	auto[1]	auto[0]	99011	1			T1	21		T2	4		T3	523
all_values[0]	auto[1]	auto[1]	72925	1			T2	4		T3	177		T5	3
all_values[1]	auto[0]	auto[0]	102173	1			T2	3		T3	649		T5	2
all_values[1]	auto[0]	auto[1]	68175	1			T2	3		T4	215		T17	5
all_values[1]	auto[1]	auto[0]	103817	1			T1	21		T2	4		T3	767
all_values[1]	auto[1]	auto[1]	68124	1			T2	3		T3	1		T4	209
all_values[2]	auto[0]	auto[0]	103568	1			T2	1		T3	437		T5	4
all_values[2]	auto[0]	auto[1]	67037	1			T2	1		T3	257		T4	127
all_values[2]	auto[1]	auto[0]	104738	1			T1	13		T2	6		T3	455
all_values[2]	auto[1]	auto[1]	66946	1			T1	8		T2	5		T3	268
all_values[3]	auto[0]	auto[0]	101142	1			T2	6		T3	432		T5	3
all_values[3]	auto[0]	auto[1]	68623	1			T2	3		T3	271		T4	111
all_values[3]	auto[1]	auto[0]	103234	1			T1	19		T2	2		T3	436
all_values[3]	auto[1]	auto[1]	69290	1			T1	2		T2	2		T3	278