Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	342289	1			T1	21		T2	13		T3	1417
all_pins[1]	342289	1			T1	21		T2	13		T3	1417
all_pins[2]	342289	1			T1	21		T2	13		T3	1417
all_pins[3]	342289	1			T1	21		T2	13		T3	1417

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1091871	1			T1	74		T2	38		T3	4944
values[0x1]	277285	1			T1	10		T2	14		T3	724
transitions[0x0=>0x1]	185198	1			T1	10		T2	7		T3	619
transitions[0x1=>0x0]	185456	1			T1	10		T2	7		T3	619

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	269364	1			T1	21		T2	9		T3	1240
all_pins[0]	values[0x1]	72925	1			T2	4		T3	177		T5	3
all_pins[0]	transitions[0x0=>0x1]	72317	1			T2	4		T3	177		T5	2
all_pins[0]	transitions[0x1=>0x0]	68940	1			T1	2		T2	2		T3	278
all_pins[1]	values[0x0]	274165	1			T1	21		T2	10		T3	1416
all_pins[1]	values[0x1]	68124	1			T2	3		T3	1		T4	209
all_pins[1]	transitions[0x0=>0x1]	37260	1			T2	1		T3	1		T4	153
all_pins[1]	transitions[0x1=>0x0]	42061	1			T2	2		T3	177		T5	3
all_pins[2]	values[0x0]	275343	1			T1	13		T2	8		T3	1149
all_pins[2]	values[0x1]	66946	1			T1	8		T2	5		T3	268
all_pins[2]	transitions[0x0=>0x1]	36803	1			T1	8		T2	2		T3	268
all_pins[2]	transitions[0x1=>0x0]	37981	1			T3	1		T4	166		T17	1
all_pins[3]	values[0x0]	272999	1			T1	19		T2	11		T3	1139
all_pins[3]	values[0x1]	69290	1			T1	2		T2	2		T3	278
all_pins[3]	transitions[0x0=>0x1]	38818	1			T1	2		T3	173		T4	88
all_pins[3]	transitions[0x1=>0x0]	36474	1			T1	8		T2	3		T3	163