Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	90240	1			T7	1665		T14	1158		T16	171
accum_cnt_1000	211317	1			T3	1608		T4	435		T7	1759
accum_cnt_100	27141	1			T3	254		T4	134		T7	202
accum_cnt_50	61826	1			T3	180		T4	122		T17	10
accum_cnt_10	202513	1			T1	13		T2	20		T3	1110
accum_cnt_0	380165	1			T1	55		T2	4		T3	1072

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	252258	1			T1	17		T2	6		T3	1056
class_index[0x1]	252258	1			T1	17		T2	6		T3	1056
class_index[0x2]	252258	1			T1	17		T2	6		T3	1056
class_index[0x3]	252258	1			T1	17		T2	6		T3	1056

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23993	1			T7	552		T14	591		T16	171
class_index[0x0]	accum_cnt_1000	58914	1			T3	764		T7	589		T14	623
class_index[0x0]	accum_cnt_100	7485	1			T3	142		T7	86		T14	41
class_index[0x0]	accum_cnt_50	19515	1			T3	110		T17	10		T7	100
class_index[0x0]	accum_cnt_10	45725	1			T2	5		T3	30		T5	7
class_index[0x0]	accum_cnt_0	87422	1			T1	17		T2	1		T3	10
class_index[0x1]	accum_cnt_2000	23170	1			T7	566		T27	479		T25	229
class_index[0x1]	accum_cnt_1000	52289	1			T7	594		T13	597		T16	256
class_index[0x1]	accum_cnt_100	7246	1			T7	61		T13	148		T16	46
class_index[0x1]	accum_cnt_50	16263	1			T18	22		T7	71		T13	121
class_index[0x1]	accum_cnt_10	48340	1			T2	3		T3	1051		T17	2
class_index[0x1]	accum_cnt_0	96440	1			T1	17		T2	3		T3	5
class_index[0x2]	accum_cnt_2000	21710	1			T7	547		T14	567		T21	522
class_index[0x2]	accum_cnt_1000	50907	1			T3	844		T7	533		T14	522
class_index[0x2]	accum_cnt_100	6861	1			T3	112		T7	24		T14	32
class_index[0x2]	accum_cnt_50	14168	1			T3	70		T18	30		T7	20
class_index[0x2]	accum_cnt_10	57994	1			T1	13		T2	6		T3	29
class_index[0x2]	accum_cnt_0	91596	1			T1	4		T3	1		T5	8
class_index[0x3]	accum_cnt_2000	21367	1			T45	454		T21	602		T27	452
class_index[0x3]	accum_cnt_1000	49207	1			T4	435		T7	43		T15	532
class_index[0x3]	accum_cnt_100	5549	1			T4	134		T7	31		T15	57
class_index[0x3]	accum_cnt_50	11880	1			T4	122		T18	22		T7	30
class_index[0x3]	accum_cnt_10	50454	1			T2	6		T4	37		T17	2
class_index[0x3]	accum_cnt_0	104707	1			T1	17		T3	1056		T5	8