Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	4940	1			T16	4		T27	107		T28	19
alert[0x1]	6630	1			T7	28		T16	415		T196	1
alert[0x2]	4231	1			T1	1		T7	27		T15	18
alert[0x3]	10924	1			T7	84		T16	4		T27	22
alert[0x4]	7682	1			T7	22		T16	2		T67	1
alert[0x5]	9206	1			T4	1		T7	111		T196	1
alert[0x6]	7744	1			T8	1		T16	2		T67	1
alert[0x7]	3767	1			T28	48		T211	1		T22	4
alert[0x8]	4374	1			T20	1		T196	1		T28	2
alert[0x9]	5334	1			T7	15		T15	609		T9	1
alert[0xa]	4805	1			T20	15		T27	234		T210	1
alert[0xb]	3756	1			T16	19		T21	21		T28	47
alert[0xc]	2750	1			T7	31		T16	5		T28	177
alert[0xd]	3575	1			T16	93		T27	30		T25	12
alert[0xe]	6215	1			T1	1		T7	432		T8	1
alert[0xf]	8254	1			T8	1		T16	111		T25	5
alert[0x10]	4641	1			T25	18		T28	1940		T211	1
alert[0x11]	5402	1			T8	2		T16	5		T211	1
alert[0x12]	3293	1			T7	1278		T15	11		T16	7
alert[0x13]	4360	1			T7	1723		T15	8		T30	50
alert[0x14]	11369	1			T7	218		T16	2		T27	747
alert[0x15]	6773	1			T15	274		T8	1		T16	23
alert[0x16]	12078	1			T8	1		T20	2		T194	1
alert[0x17]	10906	1			T15	2861		T16	531		T27	1836
alert[0x18]	4867	1			T27	64		T67	1		T25	10
alert[0x19]	1819	1			T1	1		T7	14		T16	4
alert[0x1a]	4418	1			T15	553		T9	1		T25	3
alert[0x1b]	6949	1			T7	93		T8	1		T16	1
alert[0x1c]	8026	1			T16	84		T27	63		T51	30
alert[0x1d]	5170	1			T25	11		T210	1		T28	52
alert[0x1e]	3580	1			T1	1		T8	1		T16	23
alert[0x1f]	1834	1			T194	5		T196	1		T22	1
alert[0x20]	5523	1			T7	96		T15	722		T16	161
alert[0x21]	12968	1			T7	28		T27	11		T25	49
alert[0x22]	3932	1			T3	2		T16	1		T25	7
alert[0x23]	14569	1			T7	101		T16	23		T25	1
alert[0x24]	4398	1			T9	1		T27	220		T196	3
alert[0x25]	6503	1			T7	65		T8	1		T16	1
alert[0x26]	3712	1			T7	640		T16	13		T20	3
alert[0x27]	5526	1			T27	55		T28	23		T46	5
alert[0x28]	10136	1			T7	321		T15	66		T20	2
alert[0x29]	3088	1			T7	98		T15	7		T21	2
alert[0x2a]	5024	1			T3	1		T27	615		T210	1
alert[0x2b]	8553	1			T7	143		T20	4		T27	16
alert[0x2c]	5341	1			T15	30		T8	1		T210	2
alert[0x2d]	6217	1			T7	12		T9	1		T28	42
alert[0x2e]	6562	1			T7	54		T16	932		T9	1
alert[0x2f]	4519	1			T3	1		T13	1		T8	1
alert[0x30]	3988	1			T7	22		T8	1		T28	95
alert[0x31]	4432	1			T7	42		T21	1		T67	1
alert[0x32]	8742	1			T7	202		T16	23		T20	5
alert[0x33]	4115	1			T7	792		T8	1		T25	9
alert[0x34]	5138	1			T7	29		T8	1		T21	1
alert[0x35]	1687	1			T1	1		T27	1		T28	3
alert[0x36]	3529	1			T16	138		T67	1		T25	7
alert[0x37]	2956	1			T9	1		T27	23		T210	1
alert[0x38]	5450	1			T15	74		T16	82		T27	81
alert[0x39]	5509	1			T7	856		T16	1		T27	157
alert[0x3a]	1937	1			T16	23		T210	1		T28	5
alert[0x3b]	4474	1			T15	15		T16	611		T27	281
alert[0x3c]	4364	1			T1	2		T16	14		T27	535
alert[0x3d]	4109	1			T1	1		T7	151		T8	1
alert[0x3e]	7857	1			T15	24		T8	1		T16	69
alert[0x3f]	6931	1			T7	155		T15	31		T16	17
alert[0x40]	10086	1			T7	1277		T16	179		T25	43

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	49699	1			T4	1		T15	27		T8	1
class_i[0x1]	94064	1			T8	1		T16	9		T20	34
class_i[0x2]	144805	1			T1	8		T3	4		T13	1
class_i[0x3]	92979	1			T7	9160		T15	25		T8	14

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

380835

1

T7

9160

T15

5303

T16

3648

alert_ping_fail

712

1

T1

8

T3

4

T4

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	4930	1			T16	4		T27	107		T28	19
alert_integrity_fail	alert[0x1]	6623	1			T7	28		T16	415		T28	99
alert_integrity_fail	alert[0x2]	4222	1			T7	27		T15	18		T21	33
alert_integrity_fail	alert[0x3]	10917	1			T7	84		T16	4		T27	22
alert_integrity_fail	alert[0x4]	7669	1			T7	22		T16	2		T25	6
alert_integrity_fail	alert[0x5]	9196	1			T7	111		T28	93		T30	163
alert_integrity_fail	alert[0x6]	7737	1			T16	2		T23	75		T235	12
alert_integrity_fail	alert[0x7]	3754	1			T28	48		T22	4		T51	12
alert_integrity_fail	alert[0x8]	4362	1			T20	1		T28	2		T23	345
alert_integrity_fail	alert[0x9]	5321	1			T7	15		T15	609		T27	245
alert_integrity_fail	alert[0xa]	4793	1			T20	15		T27	234		T28	33
alert_integrity_fail	alert[0xb]	3748	1			T16	19		T21	21		T28	47
alert_integrity_fail	alert[0xc]	2741	1			T7	31		T16	5		T28	177
alert_integrity_fail	alert[0xd]	3570	1			T16	93		T27	30		T25	12
alert_integrity_fail	alert[0xe]	6202	1			T7	432		T21	1		T27	104
alert_integrity_fail	alert[0xf]	8246	1			T16	111		T25	5		T30	796
alert_integrity_fail	alert[0x10]	4627	1			T25	18		T28	1940		T72	1
alert_integrity_fail	alert[0x11]	5384	1			T16	5		T46	2		T30	141
alert_integrity_fail	alert[0x12]	3283	1			T7	1278		T15	11		T16	7
alert_integrity_fail	alert[0x13]	4343	1			T7	1723		T15	8		T30	50
alert_integrity_fail	alert[0x14]	11359	1			T7	218		T16	2		T27	747
alert_integrity_fail	alert[0x15]	6765	1			T15	274		T16	23		T27	17
alert_integrity_fail	alert[0x16]	12065	1			T20	2		T194	1		T28	1239
alert_integrity_fail	alert[0x17]	10897	1			T15	2861		T16	531		T27	1836
alert_integrity_fail	alert[0x18]	4857	1			T27	64		T25	10		T28	27
alert_integrity_fail	alert[0x19]	1807	1			T7	14		T16	4		T21	5
alert_integrity_fail	alert[0x1a]	4406	1			T15	553		T25	3		T28	44
alert_integrity_fail	alert[0x1b]	6940	1			T7	93		T16	1		T27	14
alert_integrity_fail	alert[0x1c]	8017	1			T16	84		T27	63		T51	30
alert_integrity_fail	alert[0x1d]	5163	1			T25	11		T28	52		T22	2
alert_integrity_fail	alert[0x1e]	3567	1			T16	23		T30	2		T235	51
alert_integrity_fail	alert[0x1f]	1824	1			T194	5		T22	1		T235	41
alert_integrity_fail	alert[0x20]	5511	1			T7	96		T15	722		T16	161
alert_integrity_fail	alert[0x21]	12958	1			T7	28		T27	11		T25	49
alert_integrity_fail	alert[0x22]	3913	1			T16	1		T25	7		T30	1208
alert_integrity_fail	alert[0x23]	14558	1			T7	101		T16	23		T25	1
alert_integrity_fail	alert[0x24]	4386	1			T27	220		T28	9		T23	347
alert_integrity_fail	alert[0x25]	6487	1			T7	65		T16	1		T27	457
alert_integrity_fail	alert[0x26]	3704	1			T7	640		T16	13		T20	3
alert_integrity_fail	alert[0x27]	5513	1			T27	55		T28	23		T46	5
alert_integrity_fail	alert[0x28]	10124	1			T7	321		T15	66		T20	2
alert_integrity_fail	alert[0x29]	3080	1			T7	98		T15	7		T21	2
alert_integrity_fail	alert[0x2a]	5005	1			T27	615		T28	14		T30	6
alert_integrity_fail	alert[0x2b]	8543	1			T7	143		T20	4		T27	16
alert_integrity_fail	alert[0x2c]	5327	1			T15	30		T23	20		T47	1
alert_integrity_fail	alert[0x2d]	6201	1			T7	12		T28	42		T23	10
alert_integrity_fail	alert[0x2e]	6550	1			T7	54		T16	932		T27	549
alert_integrity_fail	alert[0x2f]	4504	1			T21	2		T194	2		T28	234
alert_integrity_fail	alert[0x30]	3979	1			T7	22		T28	95		T30	37
alert_integrity_fail	alert[0x31]	4428	1			T7	42		T21	1		T23	254
alert_integrity_fail	alert[0x32]	8731	1			T7	202		T16	23		T20	5
alert_integrity_fail	alert[0x33]	4100	1			T7	792		T25	9		T28	15
alert_integrity_fail	alert[0x34]	5127	1			T7	29		T21	1		T27	9
alert_integrity_fail	alert[0x35]	1678	1			T27	1		T28	3		T30	79
alert_integrity_fail	alert[0x36]	3514	1			T16	138		T25	7		T55	15
alert_integrity_fail	alert[0x37]	2942	1			T27	23		T28	46		T22	22
alert_integrity_fail	alert[0x38]	5438	1			T15	74		T16	82		T27	81
alert_integrity_fail	alert[0x39]	5499	1			T7	856		T16	1		T27	157
alert_integrity_fail	alert[0x3a]	1924	1			T16	23		T28	5		T30	421
alert_integrity_fail	alert[0x3b]	4471	1			T15	15		T16	611		T27	281
alert_integrity_fail	alert[0x3c]	4353	1			T16	14		T27	535		T195	19
alert_integrity_fail	alert[0x3d]	4099	1			T7	151		T16	25		T20	2
alert_integrity_fail	alert[0x3e]	7847	1			T15	24		T16	69		T25	46
alert_integrity_fail	alert[0x3f]	6924	1			T7	155		T15	31		T16	17
alert_integrity_fail	alert[0x40]	10082	1			T7	1277		T16	179		T25	43
alert_ping_fail	alert[0x0]	10	1			T297	1		T241	1		T281	1
alert_ping_fail	alert[0x1]	7	1			T196	1		T298	1		T299	1
alert_ping_fail	alert[0x2]	9	1			T1	1		T98	1		T300	1
alert_ping_fail	alert[0x3]	7	1			T241	2		T301	1		T302	1
alert_ping_fail	alert[0x4]	13	1			T67	1		T93	1		T297	1
alert_ping_fail	alert[0x5]	10	1			T4	1		T196	1		T303	1
alert_ping_fail	alert[0x6]	7	1			T8	1		T67	1		T304	1
alert_ping_fail	alert[0x7]	13	1			T211	1		T98	1		T241	1
alert_ping_fail	alert[0x8]	12	1			T196	1		T305	1		T306	1
alert_ping_fail	alert[0x9]	13	1			T9	1		T210	1		T98	1
alert_ping_fail	alert[0xa]	12	1			T210	1		T281	1		T307	1
alert_ping_fail	alert[0xb]	8	1			T308	1		T301	2		T300	1
alert_ping_fail	alert[0xc]	9	1			T297	1		T309	1		T301	1
alert_ping_fail	alert[0xd]	5	1			T310	1		T311	1		T312	1
alert_ping_fail	alert[0xe]	13	1			T1	1		T8	1		T313	1
alert_ping_fail	alert[0xf]	8	1			T8	1		T314	1		T315	1
alert_ping_fail	alert[0x10]	14	1			T211	1		T297	1		T309	2
alert_ping_fail	alert[0x11]	18	1			T8	2		T211	1		T303	1
alert_ping_fail	alert[0x12]	10	1			T67	1		T297	1		T309	1
alert_ping_fail	alert[0x13]	17	1			T93	3		T297	1		T281	1
alert_ping_fail	alert[0x14]	10	1			T196	1		T308	1		T310	1
alert_ping_fail	alert[0x15]	8	1			T8	1		T316	1		T99	1
alert_ping_fail	alert[0x16]	13	1			T8	1		T196	2		T303	1
alert_ping_fail	alert[0x17]	9	1			T210	1		T300	2		T305	1
alert_ping_fail	alert[0x18]	10	1			T67	1		T196	1		T308	1
alert_ping_fail	alert[0x19]	12	1			T1	1		T297	1		T309	1
alert_ping_fail	alert[0x1a]	12	1			T9	1		T297	1		T317	1
alert_ping_fail	alert[0x1b]	9	1			T8	1		T9	1		T210	1
alert_ping_fail	alert[0x1c]	9	1			T317	1		T318	2		T304	1
alert_ping_fail	alert[0x1d]	7	1			T210	1		T319	2		T88	1
alert_ping_fail	alert[0x1e]	13	1			T1	1		T8	1		T9	2
alert_ping_fail	alert[0x1f]	10	1			T196	1		T313	1		T320	1
alert_ping_fail	alert[0x20]	12	1			T9	1		T196	1		T309	1
alert_ping_fail	alert[0x21]	10	1			T196	1		T309	1		T98	1
alert_ping_fail	alert[0x22]	19	1			T3	2		T210	1		T93	1
alert_ping_fail	alert[0x23]	11	1			T297	1		T98	4		T317	1
alert_ping_fail	alert[0x24]	12	1			T9	1		T196	3		T297	1
alert_ping_fail	alert[0x25]	16	1			T8	1		T308	1		T297	1
alert_ping_fail	alert[0x26]	8	1			T210	1		T98	1		T315	1
alert_ping_fail	alert[0x27]	13	1			T309	3		T301	1		T314	1
alert_ping_fail	alert[0x28]	12	1			T211	1		T93	1		T296	1
alert_ping_fail	alert[0x29]	8	1			T196	1		T301	1		T315	1
alert_ping_fail	alert[0x2a]	19	1			T3	1		T210	1		T93	1
alert_ping_fail	alert[0x2b]	10	1			T303	1		T321	1		T306	2
alert_ping_fail	alert[0x2c]	14	1			T8	1		T210	2		T241	1
alert_ping_fail	alert[0x2d]	16	1			T9	1		T297	1		T309	1
alert_ping_fail	alert[0x2e]	12	1			T9	1		T322	1		T88	1
alert_ping_fail	alert[0x2f]	15	1			T3	1		T13	1		T8	1
alert_ping_fail	alert[0x30]	9	1			T8	1		T308	1		T241	1
alert_ping_fail	alert[0x31]	4	1			T67	1		T317	1		T300	1
alert_ping_fail	alert[0x32]	11	1			T9	1		T196	3		T309	1
alert_ping_fail	alert[0x33]	15	1			T8	1		T210	2		T297	1
alert_ping_fail	alert[0x34]	11	1			T8	1		T67	1		T297	1
alert_ping_fail	alert[0x35]	9	1			T1	1		T281	1		T314	1
alert_ping_fail	alert[0x36]	15	1			T67	1		T196	1		T211	2
alert_ping_fail	alert[0x37]	14	1			T9	1		T210	1		T281	1
alert_ping_fail	alert[0x38]	12	1			T297	1		T303	1		T241	1
alert_ping_fail	alert[0x39]	10	1			T196	1		T309	1		T98	1
alert_ping_fail	alert[0x3a]	13	1			T210	1		T98	1		T281	1
alert_ping_fail	alert[0x3b]	3	1			T317	1		T323	1		T324	1
alert_ping_fail	alert[0x3c]	11	1			T1	2		T196	1		T210	1
alert_ping_fail	alert[0x3d]	10	1			T1	1		T8	1		T303	1
alert_ping_fail	alert[0x3e]	10	1			T8	1		T196	1		T297	1
alert_ping_fail	alert[0x3f]	7	1			T303	1		T98	1		T325	2
alert_ping_fail	alert[0x40]	4	1			T306	1		T326	1		T299	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	49505	1			T15	27		T16	3521		T21	11
alert_integrity_fail	class_i[0x1]	93921	1			T16	9		T20	34		T27	14
alert_integrity_fail	class_i[0x2]	144628	1			T15	5251		T16	9		T21	55
alert_integrity_fail	class_i[0x3]	92781	1			T7	9160		T15	25		T16	109
alert_ping_fail	class_i[0x0]	194	1			T4	1		T8	1		T9	2
alert_ping_fail	class_i[0x1]	143	1			T8	1		T9	4		T67	1
alert_ping_fail	class_i[0x2]	177	1			T1	8		T3	4		T13	1
alert_ping_fail	class_i[0x3]	198	1			T8	14		T9	3		T67	2