Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.65 99.99 98.72 99.97 100.00 100.00 99.38 99.48


Total test records in report: 832
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T771 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.795117090 Mar 05 01:22:36 PM PST 24 Mar 05 01:22:45 PM PST 24 115260743 ps
T772 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1255334298 Mar 05 01:22:43 PM PST 24 Mar 05 01:23:05 PM PST 24 247078470 ps
T773 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.443682312 Mar 05 01:22:50 PM PST 24 Mar 05 01:22:58 PM PST 24 108140689 ps
T144 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3581903231 Mar 05 01:22:42 PM PST 24 Mar 05 01:25:42 PM PST 24 9761732601 ps
T774 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4258748555 Mar 05 01:22:58 PM PST 24 Mar 05 01:23:19 PM PST 24 846075281 ps
T775 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.702522930 Mar 05 01:22:02 PM PST 24 Mar 05 01:22:07 PM PST 24 111759957 ps
T143 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2931745387 Mar 05 01:22:54 PM PST 24 Mar 05 01:42:07 PM PST 24 17066204693 ps
T142 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3062556764 Mar 05 01:22:49 PM PST 24 Mar 05 01:25:44 PM PST 24 2199966486 ps
T776 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3485725333 Mar 05 01:22:25 PM PST 24 Mar 05 01:22:33 PM PST 24 311792317 ps
T777 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2853569635 Mar 05 01:22:20 PM PST 24 Mar 05 01:24:09 PM PST 24 13504025303 ps
T778 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2200737791 Mar 05 01:22:29 PM PST 24 Mar 05 01:22:36 PM PST 24 161073602 ps
T779 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2029600605 Mar 05 01:22:24 PM PST 24 Mar 05 01:23:06 PM PST 24 1235443867 ps
T780 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2439097034 Mar 05 01:22:40 PM PST 24 Mar 05 01:22:50 PM PST 24 1070775292 ps
T157 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2751350126 Mar 05 01:22:37 PM PST 24 Mar 05 01:23:20 PM PST 24 2527974500 ps
T781 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3114478830 Mar 05 01:22:25 PM PST 24 Mar 05 01:22:26 PM PST 24 25230605 ps
T782 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2001688104 Mar 05 01:22:42 PM PST 24 Mar 05 01:22:55 PM PST 24 294922441 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3320262293 Mar 05 01:22:39 PM PST 24 Mar 05 01:23:30 PM PST 24 13473135755 ps
T146 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.262520494 Mar 05 01:22:46 PM PST 24 Mar 05 01:30:54 PM PST 24 11684797161 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1690866733 Mar 05 01:22:33 PM PST 24 Mar 05 01:22:38 PM PST 24 539816190 ps
T785 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1394389865 Mar 05 01:22:37 PM PST 24 Mar 05 01:22:42 PM PST 24 35327426 ps
T786 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3648400382 Mar 05 01:22:11 PM PST 24 Mar 05 01:22:20 PM PST 24 109574946 ps
T162 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1754812309 Mar 05 01:22:20 PM PST 24 Mar 05 01:22:55 PM PST 24 2510599673 ps
T168 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3952205253 Mar 05 01:22:24 PM PST 24 Mar 05 01:22:27 PM PST 24 113247696 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1868715596 Mar 05 01:22:30 PM PST 24 Mar 05 01:22:36 PM PST 24 199495566 ps
T788 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.763064397 Mar 05 01:22:46 PM PST 24 Mar 05 01:22:58 PM PST 24 147738862 ps
T789 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3668515318 Mar 05 01:22:35 PM PST 24 Mar 05 01:22:43 PM PST 24 204796685 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.244523943 Mar 05 01:22:43 PM PST 24 Mar 05 01:22:44 PM PST 24 19652582 ps
T791 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1224126971 Mar 05 01:22:42 PM PST 24 Mar 05 01:22:49 PM PST 24 77260148 ps
T148 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1484581091 Mar 05 01:22:44 PM PST 24 Mar 05 01:28:45 PM PST 24 2173999503 ps
T792 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2820219478 Mar 05 01:22:59 PM PST 24 Mar 05 01:23:00 PM PST 24 6465517 ps
T793 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2627722576 Mar 05 01:22:29 PM PST 24 Mar 05 01:22:54 PM PST 24 1499910639 ps
T794 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1062282167 Mar 05 01:23:01 PM PST 24 Mar 05 01:23:03 PM PST 24 9210911 ps
T795 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3456036646 Mar 05 01:23:01 PM PST 24 Mar 05 01:23:02 PM PST 24 15670139 ps
T796 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1606606453 Mar 05 01:22:56 PM PST 24 Mar 05 01:22:58 PM PST 24 13464887 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1257096249 Mar 05 01:22:31 PM PST 24 Mar 05 01:22:36 PM PST 24 21555752 ps
T798 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2081715609 Mar 05 01:22:21 PM PST 24 Mar 05 01:22:31 PM PST 24 526024450 ps
T169 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2256761334 Mar 05 01:22:24 PM PST 24 Mar 05 01:22:26 PM PST 24 34186519 ps
T799 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2005161768 Mar 05 01:23:03 PM PST 24 Mar 05 01:23:06 PM PST 24 65866695 ps
T800 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3833341429 Mar 05 01:22:10 PM PST 24 Mar 05 01:23:19 PM PST 24 3753669885 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4141123000 Mar 05 01:22:19 PM PST 24 Mar 05 01:31:38 PM PST 24 28466393060 ps
T802 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2638849829 Mar 05 01:23:02 PM PST 24 Mar 05 01:23:04 PM PST 24 27697196 ps
T803 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3464556936 Mar 05 01:22:22 PM PST 24 Mar 05 01:22:53 PM PST 24 2891913200 ps
T804 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1334198086 Mar 05 01:22:59 PM PST 24 Mar 05 01:23:01 PM PST 24 6861104 ps
T133 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1865660395 Mar 05 01:22:25 PM PST 24 Mar 05 01:27:31 PM PST 24 7576790733 ps
T805 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2670493375 Mar 05 01:22:23 PM PST 24 Mar 05 01:22:29 PM PST 24 64365956 ps
T158 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.836259417 Mar 05 01:22:31 PM PST 24 Mar 05 01:23:54 PM PST 24 2533052864 ps
T806 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.930604791 Mar 05 01:22:30 PM PST 24 Mar 05 01:22:34 PM PST 24 22971792 ps
T807 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4128912670 Mar 05 01:22:13 PM PST 24 Mar 05 01:22:18 PM PST 24 66188387 ps
T166 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2567393516 Mar 05 01:22:41 PM PST 24 Mar 05 01:23:47 PM PST 24 3602285295 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1468553287 Mar 05 01:22:53 PM PST 24 Mar 05 01:23:04 PM PST 24 185344133 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3948018977 Mar 05 01:22:17 PM PST 24 Mar 05 01:22:46 PM PST 24 1931933139 ps
T810 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.43142159 Mar 05 01:23:12 PM PST 24 Mar 05 01:23:13 PM PST 24 11820374 ps
T811 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2847999418 Mar 05 01:22:28 PM PST 24 Mar 05 01:22:30 PM PST 24 46565914 ps
T812 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1046358905 Mar 05 01:23:16 PM PST 24 Mar 05 01:23:18 PM PST 24 7539070 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4128019210 Mar 05 01:22:26 PM PST 24 Mar 05 01:26:22 PM PST 24 3416549830 ps
T150 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3436223736 Mar 05 01:22:47 PM PST 24 Mar 05 01:25:42 PM PST 24 37045298155 ps
T814 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4135849454 Mar 05 01:23:01 PM PST 24 Mar 05 01:23:02 PM PST 24 8742572 ps
T815 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4282976683 Mar 05 01:23:03 PM PST 24 Mar 05 01:23:05 PM PST 24 10101384 ps
T816 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4266781284 Mar 05 01:22:22 PM PST 24 Mar 05 01:22:29 PM PST 24 143118589 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3290952415 Mar 05 01:22:33 PM PST 24 Mar 05 01:22:56 PM PST 24 1375334027 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.854912153 Mar 05 01:22:26 PM PST 24 Mar 05 01:22:31 PM PST 24 39479908 ps
T819 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1440623534 Mar 05 01:22:17 PM PST 24 Mar 05 01:22:25 PM PST 24 121927872 ps
T129 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1647087575 Mar 05 01:22:52 PM PST 24 Mar 05 01:26:54 PM PST 24 3982997502 ps
T176 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3373030800 Mar 05 01:22:06 PM PST 24 Mar 05 01:22:50 PM PST 24 643799894 ps
T820 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.569330556 Mar 05 01:22:34 PM PST 24 Mar 05 01:22:36 PM PST 24 8181140 ps
T821 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1893363735 Mar 05 01:23:02 PM PST 24 Mar 05 01:23:04 PM PST 24 8907448 ps
T822 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1087822132 Mar 05 01:22:53 PM PST 24 Mar 05 01:22:57 PM PST 24 22040068 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2663113077 Mar 05 01:22:30 PM PST 24 Mar 05 01:24:21 PM PST 24 1671025103 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1063693497 Mar 05 01:22:52 PM PST 24 Mar 05 01:22:53 PM PST 24 18641356 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3176885856 Mar 05 01:22:30 PM PST 24 Mar 05 01:22:32 PM PST 24 11496149 ps
T353 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3566391926 Mar 05 01:22:27 PM PST 24 Mar 05 01:27:10 PM PST 24 2517219719 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4161648073 Mar 05 01:22:28 PM PST 24 Mar 05 01:28:00 PM PST 24 4636212816 ps
T827 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2070935734 Mar 05 01:22:28 PM PST 24 Mar 05 01:22:30 PM PST 24 13453335 ps
T828 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.590668596 Mar 05 01:22:40 PM PST 24 Mar 05 01:22:46 PM PST 24 64449790 ps
T829 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3860254916 Mar 05 01:22:26 PM PST 24 Mar 05 01:22:39 PM PST 24 188602295 ps
T830 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3280785924 Mar 05 01:22:35 PM PST 24 Mar 05 01:22:36 PM PST 24 10882670 ps
T145 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.665476585 Mar 05 01:22:21 PM PST 24 Mar 05 01:42:51 PM PST 24 68959627755 ps
T140 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.951430482 Mar 05 01:22:42 PM PST 24 Mar 05 01:25:11 PM PST 24 27021622993 ps
T147 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2264319972 Mar 05 01:22:52 PM PST 24 Mar 05 01:31:18 PM PST 24 24995607326 ps
T149 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.490212471 Mar 05 01:22:27 PM PST 24 Mar 05 01:31:25 PM PST 24 109910845027 ps
T831 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.993240045 Mar 05 01:22:12 PM PST 24 Mar 05 01:22:19 PM PST 24 46963242 ps
T832 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3339555942 Mar 05 01:23:03 PM PST 24 Mar 05 01:23:04 PM PST 24 15306652 ps

Test location /workspace/coverage/default/13.alert_handler_stress_all.1499661296
Short name T7
Test name
Test status
Simulation time 74551093076 ps
CPU time 1625.35 seconds
Started Mar 05 01:58:48 PM PST 24
Finished Mar 05 02:25:53 PM PST 24
Peak memory 289220 kb
Host smart-61204bbe-f0bd-48ff-93d2-0bcc60abb617
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499661296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1499661296
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1538426267
Short name T16
Test name
Test status
Simulation time 191535933514 ps
CPU time 6002.98 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 03:38:38 PM PST 24
Peak memory 322300 kb
Host smart-fd63c299-15a9-436b-9260-b12a343dd2a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538426267 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1538426267
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1305230899
Short name T10
Test name
Test status
Simulation time 2225044312 ps
CPU time 30.19 seconds
Started Mar 05 01:57:54 PM PST 24
Finished Mar 05 01:58:25 PM PST 24
Peak memory 271808 kb
Host smart-431319f1-35ff-4eea-a14b-860b590d978d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1305230899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1305230899
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.918978457
Short name T159
Test name
Test status
Simulation time 581200702 ps
CPU time 23.66 seconds
Started Mar 05 01:22:45 PM PST 24
Finished Mar 05 01:23:09 PM PST 24
Peak memory 248296 kb
Host smart-19468648-32e4-4989-a824-f3d728c6604d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=918978457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.918978457
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1408065009
Short name T27
Test name
Test status
Simulation time 47173064667 ps
CPU time 2852.13 seconds
Started Mar 05 01:59:35 PM PST 24
Finished Mar 05 02:47:08 PM PST 24
Peak memory 289856 kb
Host smart-3cefa55d-7391-4052-af48-c84159d25563
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408065009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1408065009
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.949829285
Short name T57
Test name
Test status
Simulation time 98209431494 ps
CPU time 6277.03 seconds
Started Mar 05 02:01:33 PM PST 24
Finished Mar 05 03:46:11 PM PST 24
Peak memory 335540 kb
Host smart-6740663d-a2e8-4c2a-a110-4aee39e9de34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949829285 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.949829285
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1629368353
Short name T452
Test name
Test status
Simulation time 49122561883 ps
CPU time 1075 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:18:00 PM PST 24
Peak memory 282380 kb
Host smart-c740723b-c973-4479-86f5-19e19b005c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629368353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1629368353
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3320681779
Short name T25
Test name
Test status
Simulation time 287079519907 ps
CPU time 4450.09 seconds
Started Mar 05 01:59:56 PM PST 24
Finished Mar 05 03:14:06 PM PST 24
Peak memory 331144 kb
Host smart-aed02808-dc1e-460a-ba00-fb661daaa64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320681779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3320681779
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.461410880
Short name T126
Test name
Test status
Simulation time 48313493663 ps
CPU time 353.18 seconds
Started Mar 05 01:22:51 PM PST 24
Finished Mar 05 01:28:45 PM PST 24
Peak memory 265248 kb
Host smart-80abcdd9-acba-49fd-ab04-8d21b279951e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=461410880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.461410880
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2824321199
Short name T3
Test name
Test status
Simulation time 184744931647 ps
CPU time 2083.31 seconds
Started Mar 05 01:59:21 PM PST 24
Finished Mar 05 02:34:05 PM PST 24
Peak memory 289580 kb
Host smart-60335871-38f5-48e1-b2e1-780dbe43e3e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824321199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2824321199
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3811323093
Short name T134
Test name
Test status
Simulation time 59399810686 ps
CPU time 969.32 seconds
Started Mar 05 01:22:32 PM PST 24
Finished Mar 05 01:38:42 PM PST 24
Peak memory 265284 kb
Host smart-2fe22399-21f8-41fa-8d1b-f6e6d945331a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811323093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3811323093
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.3211037882
Short name T30
Test name
Test status
Simulation time 57390023804 ps
CPU time 3516.28 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:59:44 PM PST 24
Peak memory 289748 kb
Host smart-4148ce1d-c502-4b36-bc1c-6c6a7044fae7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211037882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.3211037882
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2288595264
Short name T117
Test name
Test status
Simulation time 9136525251 ps
CPU time 697.46 seconds
Started Mar 05 01:22:45 PM PST 24
Finished Mar 05 01:34:23 PM PST 24
Peak memory 272904 kb
Host smart-7616e135-f386-4020-b350-530f5c75ef25
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288595264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2288595264
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3796468747
Short name T54
Test name
Test status
Simulation time 186094309233 ps
CPU time 2963.61 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:49:07 PM PST 24
Peak memory 289844 kb
Host smart-76fe9fb3-2cd3-4def-8ff2-147dfebafff8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796468747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3796468747
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.213192982
Short name T120
Test name
Test status
Simulation time 6052663066 ps
CPU time 198.98 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:25:49 PM PST 24
Peak memory 269980 kb
Host smart-cd21276b-33f5-4654-8066-db0395371534
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=213192982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.213192982
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.546631460
Short name T196
Test name
Test status
Simulation time 13399310447 ps
CPU time 555.76 seconds
Started Mar 05 02:01:27 PM PST 24
Finished Mar 05 02:10:44 PM PST 24
Peak memory 254908 kb
Host smart-49ae76dc-d0b7-4f3f-b3d2-79789a430326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546631460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.546631460
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2091878102
Short name T322
Test name
Test status
Simulation time 716079802506 ps
CPU time 1976.64 seconds
Started Mar 05 01:59:33 PM PST 24
Finished Mar 05 02:32:30 PM PST 24
Peak memory 281276 kb
Host smart-0308d3c4-e181-496e-a555-1e658e637f06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091878102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2091878102
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.402124939
Short name T154
Test name
Test status
Simulation time 58973404 ps
CPU time 1.64 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 235544 kb
Host smart-b3efb516-6ab9-4b2b-b401-b1e2d9518998
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=402124939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.402124939
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2018099757
Short name T124
Test name
Test status
Simulation time 17615633366 ps
CPU time 1231.71 seconds
Started Mar 05 01:22:59 PM PST 24
Finished Mar 05 01:43:31 PM PST 24
Peak memory 265340 kb
Host smart-e07b52a1-4fab-4875-9c4f-7c2133e4638b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018099757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2018099757
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2762811377
Short name T46
Test name
Test status
Simulation time 40828562377 ps
CPU time 2511.82 seconds
Started Mar 05 02:00:08 PM PST 24
Finished Mar 05 02:42:01 PM PST 24
Peak memory 289976 kb
Host smart-347848ec-c06d-4af5-bc9f-e8d2d1c75ac3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762811377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2762811377
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1055906813
Short name T304
Test name
Test status
Simulation time 57790772316 ps
CPU time 1721.69 seconds
Started Mar 05 01:57:52 PM PST 24
Finished Mar 05 02:26:35 PM PST 24
Peak memory 272352 kb
Host smart-42bd4e14-5b21-4bf4-88c1-a5cb07131f30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055906813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1055906813
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1069412182
Short name T8
Test name
Test status
Simulation time 49855217847 ps
CPU time 515.58 seconds
Started Mar 05 01:57:53 PM PST 24
Finished Mar 05 02:06:29 PM PST 24
Peak memory 247848 kb
Host smart-03f12ca2-d12b-4a7e-a39f-7cd3a702d237
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069412182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1069412182
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2163014330
Short name T139
Test name
Test status
Simulation time 6463293294 ps
CPU time 507.78 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:30:59 PM PST 24
Peak memory 265360 kb
Host smart-ebb9158a-eebb-426d-a622-d2a408f6c671
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163014330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2163014330
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1110247847
Short name T328
Test name
Test status
Simulation time 60543770063 ps
CPU time 1845.29 seconds
Started Mar 05 01:58:31 PM PST 24
Finished Mar 05 02:29:17 PM PST 24
Peak memory 272000 kb
Host smart-8bba77ab-a6da-46be-a946-6fc61c350304
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110247847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1110247847
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2906683935
Short name T485
Test name
Test status
Simulation time 15430665904 ps
CPU time 647.24 seconds
Started Mar 05 01:57:56 PM PST 24
Finished Mar 05 02:08:44 PM PST 24
Peak memory 247940 kb
Host smart-ab9eb284-9461-497c-8230-c75583943f59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906683935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2906683935
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2855803435
Short name T132
Test name
Test status
Simulation time 2132951671 ps
CPU time 225.14 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:26:46 PM PST 24
Peak memory 273152 kb
Host smart-e59818f0-572e-44d6-b6c2-07f3c548e5a7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2855803435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2855803435
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3821177685
Short name T115
Test name
Test status
Simulation time 25189455883 ps
CPU time 510.62 seconds
Started Mar 05 01:22:15 PM PST 24
Finished Mar 05 01:30:46 PM PST 24
Peak memory 269600 kb
Host smart-516b3058-e820-4ee7-ab3c-180243dd2dce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821177685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3821177685
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2275402318
Short name T98
Test name
Test status
Simulation time 56730844525 ps
CPU time 590.18 seconds
Started Mar 05 01:59:35 PM PST 24
Finished Mar 05 02:09:25 PM PST 24
Peak memory 247692 kb
Host smart-c4022224-be6d-4426-a9a1-9c2b2b76bf37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275402318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2275402318
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1851411372
Short name T23
Test name
Test status
Simulation time 54847377553 ps
CPU time 3408.9 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:58:13 PM PST 24
Peak memory 298096 kb
Host smart-c1b12c77-61bf-4c3e-9570-2d2e9ceb2830
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851411372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1851411372
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3122056337
Short name T93
Test name
Test status
Simulation time 161895622696 ps
CPU time 2331.28 seconds
Started Mar 05 02:00:12 PM PST 24
Finished Mar 05 02:39:04 PM PST 24
Peak memory 288216 kb
Host smart-c3dea534-3d60-48e9-b0af-d331bf9d80a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122056337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3122056337
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1916215289
Short name T122
Test name
Test status
Simulation time 17047593869 ps
CPU time 1145.02 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:41:34 PM PST 24
Peak memory 265200 kb
Host smart-f2ed9942-c9ef-4737-bccd-de603361cbc5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916215289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1916215289
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2263329697
Short name T266
Test name
Test status
Simulation time 245330510961 ps
CPU time 1922.24 seconds
Started Mar 05 02:00:02 PM PST 24
Finished Mar 05 02:32:05 PM PST 24
Peak memory 273588 kb
Host smart-f418b3d8-3f91-4c6c-b121-a37b8abefd0f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263329697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2263329697
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.628074635
Short name T345
Test name
Test status
Simulation time 19406088 ps
CPU time 1.59 seconds
Started Mar 05 01:23:03 PM PST 24
Finished Mar 05 01:23:05 PM PST 24
Peak memory 236424 kb
Host smart-16875d6d-e980-42a1-8812-2ec8252c7056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628074635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.628074635
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3815045307
Short name T320
Test name
Test status
Simulation time 124740868299 ps
CPU time 1696.45 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:27:22 PM PST 24
Peak memory 273268 kb
Host smart-6933ca59-cea6-410c-bbdf-0c91f4d34ab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815045307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3815045307
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3628588003
Short name T281
Test name
Test status
Simulation time 7641791110 ps
CPU time 324.37 seconds
Started Mar 05 02:00:00 PM PST 24
Finished Mar 05 02:05:24 PM PST 24
Peak memory 249020 kb
Host smart-2f6bd17c-3db2-4981-9932-08d4d4074097
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628588003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3628588003
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2765107115
Short name T105
Test name
Test status
Simulation time 271621578712 ps
CPU time 5561.95 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 03:33:02 PM PST 24
Peak memory 306212 kb
Host smart-17998f8a-572a-4773-86a9-3a86f398647f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765107115 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2765107115
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1865660395
Short name T133
Test name
Test status
Simulation time 7576790733 ps
CPU time 305.95 seconds
Started Mar 05 01:22:25 PM PST 24
Finished Mar 05 01:27:31 PM PST 24
Peak memory 265120 kb
Host smart-93ac51e8-e295-4576-aeb9-1733b2f075d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1865660395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1865660395
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2231657874
Short name T203
Test name
Test status
Simulation time 37866659048 ps
CPU time 2248.57 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 02:36:11 PM PST 24
Peak memory 289588 kb
Host smart-baa3b5cc-2168-4789-b794-b0bdf9fe7ed0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231657874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2231657874
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1065141828
Short name T264
Test name
Test status
Simulation time 223171385361 ps
CPU time 3952.42 seconds
Started Mar 05 01:58:49 PM PST 24
Finished Mar 05 03:04:42 PM PST 24
Peak memory 306224 kb
Host smart-4655e631-4fa3-4af9-b840-a14733fe0390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065141828 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1065141828
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3992229
Short name T642
Test name
Test status
Simulation time 31945451552 ps
CPU time 1743.38 seconds
Started Mar 05 02:00:17 PM PST 24
Finished Mar 05 02:29:20 PM PST 24
Peak memory 273396 kb
Host smart-15828311-50ad-46b6-bddf-1c7560ee0548
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3992229
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1156918459
Short name T153
Test name
Test status
Simulation time 55759162 ps
CPU time 2.18 seconds
Started Mar 05 01:22:36 PM PST 24
Finished Mar 05 01:22:38 PM PST 24
Peak memory 236304 kb
Host smart-4ed4ce0d-3792-46e0-ae16-235056d45813
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1156918459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1156918459
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2264319972
Short name T147
Test name
Test status
Simulation time 24995607326 ps
CPU time 505.82 seconds
Started Mar 05 01:22:52 PM PST 24
Finished Mar 05 01:31:18 PM PST 24
Peak memory 267320 kb
Host smart-9042a351-3e00-4756-8eac-c12fc0533e86
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264319972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2264319972
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1689575428
Short name T317
Test name
Test status
Simulation time 11972363995 ps
CPU time 469.06 seconds
Started Mar 05 01:59:11 PM PST 24
Finished Mar 05 02:07:00 PM PST 24
Peak memory 247852 kb
Host smart-76312e39-353f-4690-9e5c-a1621d632dae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689575428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1689575428
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3206916432
Short name T37
Test name
Test status
Simulation time 5478198162 ps
CPU time 331.64 seconds
Started Mar 05 02:00:12 PM PST 24
Finished Mar 05 02:05:43 PM PST 24
Peak memory 257192 kb
Host smart-f21d1b1d-6ae1-40f9-b321-d3e0f1bf1ad4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206916432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3206916432
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3340740689
Short name T247
Test name
Test status
Simulation time 1792230676 ps
CPU time 27.09 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:47 PM PST 24
Peak memory 255920 kb
Host smart-2012371c-697c-4eb5-9df8-0125feab3523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
40689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3340740689
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3436223736
Short name T150
Test name
Test status
Simulation time 37045298155 ps
CPU time 175.11 seconds
Started Mar 05 01:22:47 PM PST 24
Finished Mar 05 01:25:42 PM PST 24
Peak memory 265212 kb
Host smart-72df1f7a-1a94-4c86-84df-9e9246847b78
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3436223736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3436223736
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3562621796
Short name T229
Test name
Test status
Simulation time 117151745 ps
CPU time 3.17 seconds
Started Mar 05 01:57:37 PM PST 24
Finished Mar 05 01:57:41 PM PST 24
Peak memory 249148 kb
Host smart-2b221ff3-6860-479f-941e-2dc8818fda24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3562621796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3562621796
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3238025436
Short name T216
Test name
Test status
Simulation time 35247272 ps
CPU time 2.9 seconds
Started Mar 05 01:57:46 PM PST 24
Finished Mar 05 01:57:50 PM PST 24
Peak memory 249128 kb
Host smart-e27fe803-fec1-4888-bd66-927b0e55fbdc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3238025436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3238025436
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3526087094
Short name T213
Test name
Test status
Simulation time 51295085 ps
CPU time 3.05 seconds
Started Mar 05 01:58:30 PM PST 24
Finished Mar 05 01:58:34 PM PST 24
Peak memory 249012 kb
Host smart-3dcc80ec-e931-4271-a891-92be181f81a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3526087094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3526087094
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.474740061
Short name T217
Test name
Test status
Simulation time 133858815 ps
CPU time 3.56 seconds
Started Mar 05 01:58:47 PM PST 24
Finished Mar 05 01:58:51 PM PST 24
Peak memory 249012 kb
Host smart-d67daffb-d3dc-4f1c-976b-ed839e48e965
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=474740061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.474740061
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1376959551
Short name T99
Test name
Test status
Simulation time 105837904855 ps
CPU time 2546.76 seconds
Started Mar 05 01:58:31 PM PST 24
Finished Mar 05 02:40:58 PM PST 24
Peak memory 283048 kb
Host smart-2050f047-3780-434f-831d-9014b40eb381
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376959551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1376959551
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.872956337
Short name T244
Test name
Test status
Simulation time 119075359412 ps
CPU time 5550.89 seconds
Started Mar 05 01:58:55 PM PST 24
Finished Mar 05 03:31:27 PM PST 24
Peak memory 299300 kb
Host smart-62e9eab1-05de-49e7-9ccf-204d3a700789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872956337 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.872956337
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3858694314
Short name T306
Test name
Test status
Simulation time 10510429632 ps
CPU time 447.65 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 02:06:48 PM PST 24
Peak memory 255088 kb
Host smart-145e8d22-1533-4b11-884a-5a78a3544a7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858694314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3858694314
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.383764648
Short name T289
Test name
Test status
Simulation time 84071754914 ps
CPU time 2090.83 seconds
Started Mar 05 02:00:15 PM PST 24
Finished Mar 05 02:35:06 PM PST 24
Peak memory 287076 kb
Host smart-1bf7691e-ec20-4cea-8b20-d915d034b68f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383764648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.383764648
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.44740108
Short name T245
Test name
Test status
Simulation time 599759628899 ps
CPU time 4069.99 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 03:05:59 PM PST 24
Peak memory 298208 kb
Host smart-79bc0ee8-a54b-4599-82b2-ca3407ead54d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44740108 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.44740108
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.714943384
Short name T311
Test name
Test status
Simulation time 57511568179 ps
CPU time 614.92 seconds
Started Mar 05 01:58:25 PM PST 24
Finished Mar 05 02:08:40 PM PST 24
Peak memory 255156 kb
Host smart-c7ded8ad-2bc8-43a0-85ef-1bd2932f536b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714943384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.714943384
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1850080588
Short name T52
Test name
Test status
Simulation time 112352155181 ps
CPU time 1363.69 seconds
Started Mar 05 01:59:10 PM PST 24
Finished Mar 05 02:21:54 PM PST 24
Peak memory 289136 kb
Host smart-50d10414-6b5f-4236-852a-bf789f1ca391
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850080588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1850080588
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.81662141
Short name T165
Test name
Test status
Simulation time 1260085629 ps
CPU time 44.06 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:23:08 PM PST 24
Peak memory 236728 kb
Host smart-91b19d14-d72a-48de-b7ad-af942f170fcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=81662141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.81662141
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2751350126
Short name T157
Test name
Test status
Simulation time 2527974500 ps
CPU time 43.21 seconds
Started Mar 05 01:22:37 PM PST 24
Finished Mar 05 01:23:20 PM PST 24
Peak memory 239120 kb
Host smart-ebd750c5-5df3-414c-af4f-c0d21d8385a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2751350126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2751350126
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2931745387
Short name T143
Test name
Test status
Simulation time 17066204693 ps
CPU time 1152.6 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:42:07 PM PST 24
Peak memory 265208 kb
Host smart-175a176b-9537-4b52-b636-01d088cca5a5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931745387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2931745387
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1277108063
Short name T242
Test name
Test status
Simulation time 13395806 ps
CPU time 1.43 seconds
Started Mar 05 01:22:40 PM PST 24
Finished Mar 05 01:22:42 PM PST 24
Peak memory 236420 kb
Host smart-b5b6e74d-1a18-4565-8906-0d7854eacd9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1277108063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1277108063
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.4065488836
Short name T319
Test name
Test status
Simulation time 8661576799 ps
CPU time 184.4 seconds
Started Mar 05 01:57:37 PM PST 24
Finished Mar 05 02:00:42 PM PST 24
Peak memory 246712 kb
Host smart-6db01d4e-ade8-4979-b011-2998daf9c6b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065488836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.4065488836
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1782337623
Short name T81
Test name
Test status
Simulation time 183205550478 ps
CPU time 4654.35 seconds
Started Mar 05 01:58:30 PM PST 24
Finished Mar 05 03:16:05 PM PST 24
Peak memory 321444 kb
Host smart-fb4afed3-9b81-4721-a56a-a19a0ab9ad53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782337623 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1782337623
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3354880720
Short name T287
Test name
Test status
Simulation time 814083097 ps
CPU time 7.08 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 01:58:33 PM PST 24
Peak memory 248952 kb
Host smart-819ff6ba-f7e7-46a1-8c2f-1adb5ff32482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33548
80720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3354880720
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.307922363
Short name T461
Test name
Test status
Simulation time 789212951 ps
CPU time 28.84 seconds
Started Mar 05 01:58:32 PM PST 24
Finished Mar 05 01:59:01 PM PST 24
Peak memory 248992 kb
Host smart-9d9c541a-fa7c-4da1-aceb-2edd7aefc481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30792
2363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.307922363
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1168228324
Short name T256
Test name
Test status
Simulation time 14514648247 ps
CPU time 224.67 seconds
Started Mar 05 01:58:57 PM PST 24
Finished Mar 05 02:02:43 PM PST 24
Peak memory 257236 kb
Host smart-22c11d6a-c923-479c-b9d7-6049b8f2131b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168228324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1168228324
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.605188141
Short name T249
Test name
Test status
Simulation time 105061850 ps
CPU time 8.88 seconds
Started Mar 05 01:59:19 PM PST 24
Finished Mar 05 01:59:28 PM PST 24
Peak memory 240784 kb
Host smart-c33dcfaa-0dce-411d-95b0-f2733348801d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60518
8141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.605188141
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.650283717
Short name T282
Test name
Test status
Simulation time 103611494210 ps
CPU time 3067.97 seconds
Started Mar 05 01:59:26 PM PST 24
Finished Mar 05 02:50:35 PM PST 24
Peak memory 322784 kb
Host smart-ff24d5c4-724a-45b2-b866-9fe08beff3a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650283717 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.650283717
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4226744701
Short name T339
Test name
Test status
Simulation time 110729353276 ps
CPU time 1469.02 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:24:23 PM PST 24
Peak memory 286740 kb
Host smart-c5b1fb6d-ca22-460b-ab68-cc2051458f3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226744701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4226744701
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2737668176
Short name T106
Test name
Test status
Simulation time 646994193 ps
CPU time 44.6 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:01:11 PM PST 24
Peak memory 255608 kb
Host smart-0608a739-be86-4c19-86ae-31016d233dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27376
68176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2737668176
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.223989227
Short name T290
Test name
Test status
Simulation time 383260384998 ps
CPU time 2205.1 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:38:10 PM PST 24
Peak memory 306412 kb
Host smart-bc1c056a-4825-4a6b-bbab-b5392ce01058
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223989227 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.223989227
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.488431114
Short name T259
Test name
Test status
Simulation time 2197913219 ps
CPU time 55.98 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:59:06 PM PST 24
Peak memory 255512 kb
Host smart-ca00e483-e916-4a57-8e78-547b3b7c3bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48843
1114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.488431114
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.836259417
Short name T158
Test name
Test status
Simulation time 2533052864 ps
CPU time 83.13 seconds
Started Mar 05 01:22:31 PM PST 24
Finished Mar 05 01:23:54 PM PST 24
Peak memory 239380 kb
Host smart-c2a35596-779a-4419-8de5-0b80a14d89e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=836259417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.836259417
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3841687516
Short name T128
Test name
Test status
Simulation time 7642731831 ps
CPU time 324.88 seconds
Started Mar 05 01:22:41 PM PST 24
Finished Mar 05 01:28:06 PM PST 24
Peak memory 265216 kb
Host smart-1693819c-718a-4f0e-a8ab-7d35f1384533
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3841687516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3841687516
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.560816411
Short name T135
Test name
Test status
Simulation time 30124219584 ps
CPU time 1026.34 seconds
Started Mar 05 01:22:37 PM PST 24
Finished Mar 05 01:39:43 PM PST 24
Peak memory 272288 kb
Host smart-c3a10ae5-098a-4c02-b93e-b4c42676b76b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560816411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.560816411
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3528138406
Short name T151
Test name
Test status
Simulation time 122192270 ps
CPU time 4.61 seconds
Started Mar 05 01:22:40 PM PST 24
Finished Mar 05 01:22:45 PM PST 24
Peak memory 236420 kb
Host smart-ada9b283-aac7-4a91-804b-f68fce9cfc19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3528138406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3528138406
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2725047694
Short name T163
Test name
Test status
Simulation time 102606724 ps
CPU time 2.57 seconds
Started Mar 05 01:22:40 PM PST 24
Finished Mar 05 01:22:43 PM PST 24
Peak memory 235512 kb
Host smart-73ba2748-92c8-48a0-8b2f-80c32e786431
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2725047694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2725047694
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.3787161293
Short name T170
Test name
Test status
Simulation time 620043982 ps
CPU time 43.69 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:45 PM PST 24
Peak memory 239400 kb
Host smart-ead40ace-c3b3-4a3b-b2bb-c6b225d653b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3787161293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3787161293
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.1754812309
Short name T162
Test name
Test status
Simulation time 2510599673 ps
CPU time 34.97 seconds
Started Mar 05 01:22:20 PM PST 24
Finished Mar 05 01:22:55 PM PST 24
Peak memory 240292 kb
Host smart-58a1511c-414a-4437-a10d-4b398f90b323
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1754812309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1754812309
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1244089210
Short name T136
Test name
Test status
Simulation time 2711867842 ps
CPU time 186.27 seconds
Started Mar 05 01:22:06 PM PST 24
Finished Mar 05 01:25:12 PM PST 24
Peak memory 257012 kb
Host smart-072a0101-2171-4e52-8a01-842c7f49ddeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1244089210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1244089210
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2819276732
Short name T119
Test name
Test status
Simulation time 4457487670 ps
CPU time 312.79 seconds
Started Mar 05 01:22:21 PM PST 24
Finished Mar 05 01:27:34 PM PST 24
Peak memory 272564 kb
Host smart-93e65d1a-fe07-403f-b5f3-b1ea541b90cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2819276732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2819276732
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2154187278
Short name T137
Test name
Test status
Simulation time 10570695384 ps
CPU time 181.58 seconds
Started Mar 05 01:22:44 PM PST 24
Finished Mar 05 01:25:46 PM PST 24
Peak memory 257008 kb
Host smart-a90b7d1a-50f8-4ce4-bfa5-5c98e47a1d07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2154187278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2154187278
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2567393516
Short name T166
Test name
Test status
Simulation time 3602285295 ps
CPU time 66.38 seconds
Started Mar 05 01:22:41 PM PST 24
Finished Mar 05 01:23:47 PM PST 24
Peak memory 239428 kb
Host smart-c29b6e6d-5a88-4540-9bdb-e7f3f071fd97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2567393516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2567393516
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2256761334
Short name T169
Test name
Test status
Simulation time 34186519 ps
CPU time 2.16 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:22:26 PM PST 24
Peak memory 235540 kb
Host smart-6727a8f5-2f2b-442e-83e1-fb0cb1b0d053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2256761334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2256761334
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3394162707
Short name T167
Test name
Test status
Simulation time 102488384 ps
CPU time 2.89 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:22:27 PM PST 24
Peak memory 237308 kb
Host smart-7c6b0c27-279f-4b4a-af7c-0d3970786525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3394162707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3394162707
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2481757788
Short name T164
Test name
Test status
Simulation time 353881688 ps
CPU time 42.75 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:23:06 PM PST 24
Peak memory 236460 kb
Host smart-c89d1895-5420-4f66-8dbe-6035f1c2b297
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2481757788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2481757788
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3559359605
Short name T175
Test name
Test status
Simulation time 2365261382 ps
CPU time 42.13 seconds
Started Mar 05 01:22:56 PM PST 24
Finished Mar 05 01:23:38 PM PST 24
Peak memory 239356 kb
Host smart-6841504a-d7b1-444b-a058-dab84d6a253f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3559359605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3559359605
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1439617278
Short name T161
Test name
Test status
Simulation time 167915109 ps
CPU time 3.98 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:22:58 PM PST 24
Peak memory 236936 kb
Host smart-bd0e1ce4-70bd-44c6-a977-947a8c12117b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1439617278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1439617278
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3952205253
Short name T168
Test name
Test status
Simulation time 113247696 ps
CPU time 2.75 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:22:27 PM PST 24
Peak memory 236680 kb
Host smart-88dbe6de-a041-4351-8dc1-cfd81f276f5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3952205253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3952205253
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3042933391
Short name T22
Test name
Test status
Simulation time 41213728229 ps
CPU time 1074.41 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:17:00 PM PST 24
Peak memory 284392 kb
Host smart-9c45a642-fdfd-4623-b8b5-ab06340ee35f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042933391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3042933391
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3771783966
Short name T24
Test name
Test status
Simulation time 1276015199 ps
CPU time 31.31 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:00:16 PM PST 24
Peak memory 256012 kb
Host smart-0349a8e2-b40f-4ef8-991d-db9160bff56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37717
83966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3771783966
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.617801264
Short name T19
Test name
Test status
Simulation time 170008554 ps
CPU time 24.28 seconds
Started Mar 05 02:00:25 PM PST 24
Finished Mar 05 02:00:49 PM PST 24
Peak memory 255716 kb
Host smart-87beeeb8-8a60-479b-be3b-196d000c4884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61780
1264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.617801264
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3275942258
Short name T769
Test name
Test status
Simulation time 7410692529 ps
CPU time 56.83 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:23:19 PM PST 24
Peak memory 240296 kb
Host smart-0c5df67a-4003-4edb-9382-ee7b6002ef4d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3275942258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3275942258
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3782404817
Short name T354
Test name
Test status
Simulation time 4289000990 ps
CPU time 277.72 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:27:00 PM PST 24
Peak memory 236368 kb
Host smart-af23fab1-8816-4ec0-ba96-688389a811dc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3782404817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3782404817
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.4266781284
Short name T816
Test name
Test status
Simulation time 143118589 ps
CPU time 6.41 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:22:29 PM PST 24
Peak memory 240244 kb
Host smart-7034bf9f-b227-4c87-86a4-147e4db6d26c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4266781284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.4266781284
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2670493375
Short name T805
Test name
Test status
Simulation time 64365956 ps
CPU time 5.64 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:22:29 PM PST 24
Peak memory 240356 kb
Host smart-bfe10535-7ba8-4f42-bba8-ffad0503b2d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670493375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2670493375
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1936180456
Short name T173
Test name
Test status
Simulation time 95836142 ps
CPU time 8.11 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:22:32 PM PST 24
Peak memory 240192 kb
Host smart-a52ed764-d117-4a98-8aaf-99728b4af9e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1936180456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1936180456
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3980334778
Short name T750
Test name
Test status
Simulation time 17943927 ps
CPU time 1.44 seconds
Started Mar 05 01:22:26 PM PST 24
Finished Mar 05 01:22:28 PM PST 24
Peak memory 234516 kb
Host smart-9483efd6-ff6d-4176-bc4c-d831ff4d99cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3980334778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3980334778
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.874666070
Short name T190
Test name
Test status
Simulation time 87880595 ps
CPU time 10.4 seconds
Started Mar 05 01:22:07 PM PST 24
Finished Mar 05 01:22:19 PM PST 24
Peak memory 240336 kb
Host smart-b4f8d16a-16ea-4e5d-94fb-eba3410fc0d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=874666070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.874666070
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.702522930
Short name T775
Test name
Test status
Simulation time 111759957 ps
CPU time 4.75 seconds
Started Mar 05 01:22:02 PM PST 24
Finished Mar 05 01:22:07 PM PST 24
Peak memory 246572 kb
Host smart-86ebe307-365e-4f83-ab8f-c1990861d471
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702522930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.702522930
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.3373030800
Short name T176
Test name
Test status
Simulation time 643799894 ps
CPU time 43.72 seconds
Started Mar 05 01:22:06 PM PST 24
Finished Mar 05 01:22:50 PM PST 24
Peak memory 240328 kb
Host smart-8b429db5-b423-41b5-b8bf-af7c6ca0c992
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3373030800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3373030800
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2853569635
Short name T777
Test name
Test status
Simulation time 13504025303 ps
CPU time 108.75 seconds
Started Mar 05 01:22:20 PM PST 24
Finished Mar 05 01:24:09 PM PST 24
Peak memory 236404 kb
Host smart-e17fb256-c875-4ecd-8678-6c3b4a321680
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2853569635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2853569635
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2663113077
Short name T823
Test name
Test status
Simulation time 1671025103 ps
CPU time 110.32 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:24:21 PM PST 24
Peak memory 236360 kb
Host smart-992d9a44-23d2-4a8a-b1b5-903e546fc295
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2663113077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2663113077
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1868715596
Short name T787
Test name
Test status
Simulation time 199495566 ps
CPU time 5.32 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 240156 kb
Host smart-64e19d12-3cd2-414f-bb6f-71348bcb3a2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1868715596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1868715596
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3249570018
Short name T350
Test name
Test status
Simulation time 36548943 ps
CPU time 5.06 seconds
Started Mar 05 01:22:16 PM PST 24
Finished Mar 05 01:22:22 PM PST 24
Peak memory 241272 kb
Host smart-7a1a2c0c-5e9e-4816-89d9-28666a2382ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249570018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3249570018
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4128912670
Short name T807
Test name
Test status
Simulation time 66188387 ps
CPU time 4.86 seconds
Started Mar 05 01:22:13 PM PST 24
Finished Mar 05 01:22:18 PM PST 24
Peak memory 240136 kb
Host smart-31e339b5-aebf-46dc-869d-7bf469113332
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4128912670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4128912670
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.1558884772
Short name T745
Test name
Test status
Simulation time 13207538 ps
CPU time 1.36 seconds
Started Mar 05 01:22:16 PM PST 24
Finished Mar 05 01:22:18 PM PST 24
Peak memory 235372 kb
Host smart-42b5a5f9-6d0d-4452-9271-949446cda3b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1558884772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.1558884772
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1565940848
Short name T734
Test name
Test status
Simulation time 348422455 ps
CPU time 26.24 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:22:56 PM PST 24
Peak memory 244584 kb
Host smart-6ec9b57c-3ff7-4937-82d4-35eb85befc90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1565940848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1565940848
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.665476585
Short name T145
Test name
Test status
Simulation time 68959627755 ps
CPU time 1229.86 seconds
Started Mar 05 01:22:21 PM PST 24
Finished Mar 05 01:42:51 PM PST 24
Peak memory 271144 kb
Host smart-9552c681-c955-4ed4-914f-541fa72996eb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665476585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.665476585
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1440623534
Short name T819
Test name
Test status
Simulation time 121927872 ps
CPU time 7.99 seconds
Started Mar 05 01:22:17 PM PST 24
Finished Mar 05 01:22:25 PM PST 24
Peak memory 247328 kb
Host smart-f33f2c27-2df3-4878-acd4-d145e76d8785
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1440623534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1440623534
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3322114580
Short name T160
Test name
Test status
Simulation time 616785048 ps
CPU time 19.28 seconds
Started Mar 05 01:22:17 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 248388 kb
Host smart-469b5969-8181-4460-a814-92a74b5e09aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3322114580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3322114580
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.590668596
Short name T828
Test name
Test status
Simulation time 64449790 ps
CPU time 5.1 seconds
Started Mar 05 01:22:40 PM PST 24
Finished Mar 05 01:22:46 PM PST 24
Peak memory 239372 kb
Host smart-abb38730-ae24-4fa5-97fd-6044f174603d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590668596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.590668596
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2439097034
Short name T780
Test name
Test status
Simulation time 1070775292 ps
CPU time 9.08 seconds
Started Mar 05 01:22:40 PM PST 24
Finished Mar 05 01:22:50 PM PST 24
Peak memory 236348 kb
Host smart-a1c3a8dd-6b73-4d44-9bba-941c017a1c25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2439097034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2439097034
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.569330556
Short name T820
Test name
Test status
Simulation time 8181140 ps
CPU time 1.48 seconds
Started Mar 05 01:22:34 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 236392 kb
Host smart-f671e2fa-ddaf-41e8-84fe-8bcdfef4a8ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=569330556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.569330556
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3503913244
Short name T747
Test name
Test status
Simulation time 1203805447 ps
CPU time 41.62 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:23:24 PM PST 24
Peak memory 244224 kb
Host smart-33b35cfc-dc52-47ec-b7cb-bd9cf48d9c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3503913244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3503913244
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3906743593
Short name T116
Test name
Test status
Simulation time 23162508952 ps
CPU time 187.52 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:25:37 PM PST 24
Peak memory 257012 kb
Host smart-8f88ac6f-300f-4494-b188-c0cb949121b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3906743593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3906743593
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.795117090
Short name T771
Test name
Test status
Simulation time 115260743 ps
CPU time 8.26 seconds
Started Mar 05 01:22:36 PM PST 24
Finished Mar 05 01:22:45 PM PST 24
Peak memory 252088 kb
Host smart-cd9b1ab7-de83-4679-8b72-1c27ce2e4593
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=795117090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.795117090
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3879530038
Short name T733
Test name
Test status
Simulation time 571381901 ps
CPU time 11.55 seconds
Started Mar 05 01:22:38 PM PST 24
Finished Mar 05 01:22:50 PM PST 24
Peak memory 249628 kb
Host smart-8c3c62dc-b50b-4453-9d2d-d43d9476b3b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879530038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3879530038
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.4151293306
Short name T761
Test name
Test status
Simulation time 20358420 ps
CPU time 3.85 seconds
Started Mar 05 01:22:41 PM PST 24
Finished Mar 05 01:22:45 PM PST 24
Peak memory 240092 kb
Host smart-9eba2613-921b-4cd1-95a1-60bc9628738c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4151293306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.4151293306
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3280785924
Short name T830
Test name
Test status
Simulation time 10882670 ps
CPU time 1.5 seconds
Started Mar 05 01:22:35 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 235520 kb
Host smart-8ec2b1af-0027-4f2a-b519-aabe9720e0d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3280785924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3280785924
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2769404451
Short name T192
Test name
Test status
Simulation time 2839724278 ps
CPU time 48.29 seconds
Started Mar 05 01:22:38 PM PST 24
Finished Mar 05 01:23:27 PM PST 24
Peak memory 248576 kb
Host smart-35965552-da16-44a6-b7a3-a14a83924d99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2769404451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2769404451
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.4218856180
Short name T141
Test name
Test status
Simulation time 13187977539 ps
CPU time 479.06 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:30:42 PM PST 24
Peak memory 264960 kb
Host smart-be2a42ff-5b5f-45eb-ae34-c133add5aa11
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218856180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.4218856180
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2654949424
Short name T751
Test name
Test status
Simulation time 343907350 ps
CPU time 25.05 seconds
Started Mar 05 01:22:39 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 248520 kb
Host smart-1f1b2e18-6e9f-40a1-9ecb-41d9fbfb44d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2654949424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2654949424
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.299679009
Short name T351
Test name
Test status
Simulation time 89348551 ps
CPU time 5.63 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:22:48 PM PST 24
Peak memory 238652 kb
Host smart-f96088db-9cde-4186-af6a-4c1095a11521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299679009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.299679009
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3868591283
Short name T765
Test name
Test status
Simulation time 151528136 ps
CPU time 4.68 seconds
Started Mar 05 01:22:32 PM PST 24
Finished Mar 05 01:22:37 PM PST 24
Peak memory 235404 kb
Host smart-af066bcb-4b37-436c-8eb7-7a9ba7c2caf9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3868591283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3868591283
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2165719018
Short name T762
Test name
Test status
Simulation time 174392076 ps
CPU time 14.77 seconds
Started Mar 05 01:22:41 PM PST 24
Finished Mar 05 01:22:56 PM PST 24
Peak memory 244600 kb
Host smart-a6a3689b-6f93-4dda-82d0-e41b15af6795
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2165719018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2165719018
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.951430482
Short name T140
Test name
Test status
Simulation time 27021622993 ps
CPU time 148.27 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:25:11 PM PST 24
Peak memory 257048 kb
Host smart-f2665f48-ac1d-435a-83a7-0087c604d9c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=951430482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.951430482
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1690866733
Short name T784
Test name
Test status
Simulation time 539816190 ps
CPU time 4.57 seconds
Started Mar 05 01:22:33 PM PST 24
Finished Mar 05 01:22:38 PM PST 24
Peak memory 248476 kb
Host smart-952644a1-0835-4d91-a4cc-19b755239c49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1690866733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1690866733
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1224126971
Short name T791
Test name
Test status
Simulation time 77260148 ps
CPU time 6.22 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:22:49 PM PST 24
Peak memory 240368 kb
Host smart-8518dbee-aa21-4b3d-aaa7-0585fe50f7c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224126971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1224126971
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1704341763
Short name T755
Test name
Test status
Simulation time 484810227 ps
CPU time 8.29 seconds
Started Mar 05 01:22:51 PM PST 24
Finished Mar 05 01:23:00 PM PST 24
Peak memory 236332 kb
Host smart-cf0dd629-e125-4296-9213-18f78bd6bf0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1704341763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1704341763
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.650344302
Short name T346
Test name
Test status
Simulation time 7961520 ps
CPU time 1.31 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:22:44 PM PST 24
Peak memory 235452 kb
Host smart-bf3d7de0-e2a3-49f9-936a-2a268313c9ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=650344302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.650344302
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3167955023
Short name T193
Test name
Test status
Simulation time 85523870 ps
CPU time 12.47 seconds
Started Mar 05 01:22:51 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 244632 kb
Host smart-016249ac-a4e0-4649-a9a2-1385a9daf11e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3167955023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3167955023
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3062556764
Short name T142
Test name
Test status
Simulation time 2199966486 ps
CPU time 174.65 seconds
Started Mar 05 01:22:49 PM PST 24
Finished Mar 05 01:25:44 PM PST 24
Peak memory 265236 kb
Host smart-e7dbcbc0-ccfb-44a5-9d68-63aad269005f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3062556764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3062556764
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1484581091
Short name T148
Test name
Test status
Simulation time 2173999503 ps
CPU time 360.94 seconds
Started Mar 05 01:22:44 PM PST 24
Finished Mar 05 01:28:45 PM PST 24
Peak memory 269540 kb
Host smart-ec630f2f-4258-405c-8b17-3042612e3f55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484581091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1484581091
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.763064397
Short name T788
Test name
Test status
Simulation time 147738862 ps
CPU time 11.36 seconds
Started Mar 05 01:22:46 PM PST 24
Finished Mar 05 01:22:58 PM PST 24
Peak memory 248364 kb
Host smart-d009beaa-2d45-47de-9fb5-f82e7c9130d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=763064397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.763064397
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2847003619
Short name T152
Test name
Test status
Simulation time 117154292 ps
CPU time 4.1 seconds
Started Mar 05 01:22:51 PM PST 24
Finished Mar 05 01:22:55 PM PST 24
Peak memory 237420 kb
Host smart-23269ddd-f983-4fc8-b109-31b79cd40c7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2847003619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2847003619
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2001688104
Short name T782
Test name
Test status
Simulation time 294922441 ps
CPU time 12.76 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:22:55 PM PST 24
Peak memory 242448 kb
Host smart-2e3f5932-33a5-4a03-b599-4e28d57cf834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001688104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2001688104
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.4168242862
Short name T728
Test name
Test status
Simulation time 842987230 ps
CPU time 8.86 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:22:52 PM PST 24
Peak memory 240260 kb
Host smart-c35a0c97-90f5-48f9-a6c4-008b28e82b5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4168242862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.4168242862
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.244523943
Short name T790
Test name
Test status
Simulation time 19652582 ps
CPU time 1.53 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:22:44 PM PST 24
Peak memory 236424 kb
Host smart-bc9fcfa6-7878-4637-b0fd-3463eaab3741
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=244523943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.244523943
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1255334298
Short name T772
Test name
Test status
Simulation time 247078470 ps
CPU time 21.29 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:23:05 PM PST 24
Peak memory 240320 kb
Host smart-d56e0570-9f36-4b35-80bc-94a93b709afe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1255334298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1255334298
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.571404384
Short name T714
Test name
Test status
Simulation time 25246545 ps
CPU time 4.3 seconds
Started Mar 05 01:22:43 PM PST 24
Finished Mar 05 01:22:47 PM PST 24
Peak memory 240336 kb
Host smart-4f9db149-1e90-424d-b98f-7f7e8ddd3d85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=571404384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.571404384
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1969666036
Short name T724
Test name
Test status
Simulation time 96021295 ps
CPU time 6.99 seconds
Started Mar 05 01:22:45 PM PST 24
Finished Mar 05 01:22:53 PM PST 24
Peak memory 238400 kb
Host smart-5d7b2acf-3e7b-4993-89e2-20d5ae72d141
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969666036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1969666036
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1079085862
Short name T174
Test name
Test status
Simulation time 191252360 ps
CPU time 4.66 seconds
Started Mar 05 01:22:45 PM PST 24
Finished Mar 05 01:22:50 PM PST 24
Peak memory 236088 kb
Host smart-eb76161b-0e54-4002-976f-43253d9bfcf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1079085862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1079085862
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2215684160
Short name T719
Test name
Test status
Simulation time 7556353 ps
CPU time 1.4 seconds
Started Mar 05 01:22:44 PM PST 24
Finished Mar 05 01:22:46 PM PST 24
Peak memory 236316 kb
Host smart-55f245bd-1c42-41aa-9798-dafc1ab0e75a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2215684160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2215684160
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.862995895
Short name T171
Test name
Test status
Simulation time 1674730978 ps
CPU time 21.89 seconds
Started Mar 05 01:22:44 PM PST 24
Finished Mar 05 01:23:07 PM PST 24
Peak memory 240316 kb
Host smart-e654f5a8-5073-47aa-85a8-53588ec14531
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=862995895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.862995895
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.262520494
Short name T146
Test name
Test status
Simulation time 11684797161 ps
CPU time 488.09 seconds
Started Mar 05 01:22:46 PM PST 24
Finished Mar 05 01:30:54 PM PST 24
Peak memory 268652 kb
Host smart-b894070e-fa86-442a-b797-bc127de8426e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262520494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.262520494
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.601715348
Short name T754
Test name
Test status
Simulation time 549884185 ps
CPU time 11.07 seconds
Started Mar 05 01:22:44 PM PST 24
Finished Mar 05 01:22:56 PM PST 24
Peak memory 248636 kb
Host smart-a8806a82-f833-4302-b625-ea01c208ef1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=601715348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.601715348
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1468507915
Short name T349
Test name
Test status
Simulation time 322507090 ps
CPU time 7.68 seconds
Started Mar 05 01:22:53 PM PST 24
Finished Mar 05 01:23:01 PM PST 24
Peak memory 239924 kb
Host smart-c63c9fba-d3a3-497c-aab7-7415690e5841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468507915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1468507915
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1087822132
Short name T822
Test name
Test status
Simulation time 22040068 ps
CPU time 3.89 seconds
Started Mar 05 01:22:53 PM PST 24
Finished Mar 05 01:22:57 PM PST 24
Peak memory 236200 kb
Host smart-879f5882-693e-415c-a1a0-b5c337133d57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1087822132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1087822132
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1606606453
Short name T796
Test name
Test status
Simulation time 13464887 ps
CPU time 1.49 seconds
Started Mar 05 01:22:56 PM PST 24
Finished Mar 05 01:22:58 PM PST 24
Peak memory 235652 kb
Host smart-2ddec919-3af0-4c81-a813-fd94d82ae254
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606606453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1606606453
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3742726891
Short name T770
Test name
Test status
Simulation time 359956450 ps
CPU time 11.75 seconds
Started Mar 05 01:22:55 PM PST 24
Finished Mar 05 01:23:07 PM PST 24
Peak memory 240320 kb
Host smart-823d6ab0-7c49-4e22-92c9-ffc55416ead0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3742726891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3742726891
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3581903231
Short name T144
Test name
Test status
Simulation time 9761732601 ps
CPU time 179.93 seconds
Started Mar 05 01:22:42 PM PST 24
Finished Mar 05 01:25:42 PM PST 24
Peak memory 256916 kb
Host smart-4f7447bd-d42d-444b-a54d-367e3859325c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3581903231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3581903231
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1468553287
Short name T808
Test name
Test status
Simulation time 185344133 ps
CPU time 10.98 seconds
Started Mar 05 01:22:53 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 248524 kb
Host smart-31f503d2-4c26-4a79-9a3c-45c7814262ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1468553287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1468553287
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.443682312
Short name T773
Test name
Test status
Simulation time 108140689 ps
CPU time 8.29 seconds
Started Mar 05 01:22:50 PM PST 24
Finished Mar 05 01:22:58 PM PST 24
Peak memory 252396 kb
Host smart-e9bb87f9-c416-43f4-b79d-e7061f87fceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443682312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.443682312
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.2149120843
Short name T756
Test name
Test status
Simulation time 29731877 ps
CPU time 3.53 seconds
Started Mar 05 01:22:50 PM PST 24
Finished Mar 05 01:22:54 PM PST 24
Peak memory 236328 kb
Host smart-639ef950-3eb2-445f-ad2b-0a5f908e563d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2149120843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.2149120843
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2166402590
Short name T738
Test name
Test status
Simulation time 14371647 ps
CPU time 1.42 seconds
Started Mar 05 01:22:52 PM PST 24
Finished Mar 05 01:22:54 PM PST 24
Peak memory 236412 kb
Host smart-e9d1533c-7c2e-4378-9a50-184f19065c5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2166402590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2166402590
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3722671359
Short name T749
Test name
Test status
Simulation time 498947341 ps
CPU time 35.32 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:23:29 PM PST 24
Peak memory 244596 kb
Host smart-32457799-ca1e-4775-99a6-4c25e47678a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3722671359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3722671359
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3941914084
Short name T114
Test name
Test status
Simulation time 2334530384 ps
CPU time 367.24 seconds
Started Mar 05 01:22:53 PM PST 24
Finished Mar 05 01:29:00 PM PST 24
Peak memory 268264 kb
Host smart-ca5f16a1-0e5c-4d65-ba51-4031cff0c1f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941914084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3941914084
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4116223446
Short name T730
Test name
Test status
Simulation time 133611447 ps
CPU time 5.6 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:22:59 PM PST 24
Peak memory 248468 kb
Host smart-a47febad-9d54-4ad0-81b1-bf576e93b9b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4116223446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4116223446
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2076051429
Short name T265
Test name
Test status
Simulation time 974512827 ps
CPU time 41.85 seconds
Started Mar 05 01:22:49 PM PST 24
Finished Mar 05 01:23:31 PM PST 24
Peak memory 239164 kb
Host smart-133546be-2c72-4dc1-97ea-7d65115b57e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2076051429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2076051429
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2260302651
Short name T736
Test name
Test status
Simulation time 130603662 ps
CPU time 10.82 seconds
Started Mar 05 01:23:04 PM PST 24
Finished Mar 05 01:23:15 PM PST 24
Peak memory 252312 kb
Host smart-d38c040f-6f74-40b1-92ba-c3a268aa71fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260302651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2260302651
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.648604607
Short name T748
Test name
Test status
Simulation time 34945812 ps
CPU time 5.41 seconds
Started Mar 05 01:22:57 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 240272 kb
Host smart-f5da7395-9827-4c07-b775-f4ad2dc1ac95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=648604607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.648604607
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1063693497
Short name T824
Test name
Test status
Simulation time 18641356 ps
CPU time 1.49 seconds
Started Mar 05 01:22:52 PM PST 24
Finished Mar 05 01:22:53 PM PST 24
Peak memory 236452 kb
Host smart-ba8be9bd-00dc-4e48-893e-a4bde76b7b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1063693497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1063693497
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.3610408374
Short name T744
Test name
Test status
Simulation time 1114794250 ps
CPU time 25.73 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:23:20 PM PST 24
Peak memory 244556 kb
Host smart-7bd7439f-41f5-4616-826a-b8f79fa2bc0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3610408374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.3610408374
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1647087575
Short name T129
Test name
Test status
Simulation time 3982997502 ps
CPU time 241.59 seconds
Started Mar 05 01:22:52 PM PST 24
Finished Mar 05 01:26:54 PM PST 24
Peak memory 265212 kb
Host smart-e2496cf2-2aed-41ae-bf6f-2ef6a95f4419
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1647087575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1647087575
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3875153707
Short name T768
Test name
Test status
Simulation time 2956518123 ps
CPU time 17.04 seconds
Started Mar 05 01:22:54 PM PST 24
Finished Mar 05 01:23:11 PM PST 24
Peak memory 252028 kb
Host smart-4a8abfff-3127-4146-a554-02f5b98e2252
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3875153707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3875153707
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3444887116
Short name T767
Test name
Test status
Simulation time 183001927 ps
CPU time 10.99 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:12 PM PST 24
Peak memory 238468 kb
Host smart-907372a5-dead-4694-8dad-66cf960e0f38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444887116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3444887116
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2005161768
Short name T799
Test name
Test status
Simulation time 65866695 ps
CPU time 3.29 seconds
Started Mar 05 01:23:03 PM PST 24
Finished Mar 05 01:23:06 PM PST 24
Peak memory 236308 kb
Host smart-cadd061e-38b4-4cb2-85de-3a58bf0fbf40
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2005161768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2005161768
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1062282167
Short name T794
Test name
Test status
Simulation time 9210911 ps
CPU time 1.59 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 236492 kb
Host smart-79b1c9aa-8335-40b8-8ff3-701f362cc4c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1062282167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1062282167
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4258748555
Short name T774
Test name
Test status
Simulation time 846075281 ps
CPU time 20.88 seconds
Started Mar 05 01:22:58 PM PST 24
Finished Mar 05 01:23:19 PM PST 24
Peak memory 248528 kb
Host smart-cbe36e54-e0a7-41a7-a1f1-58b27d07d371
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4258748555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4258748555
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.861820489
Short name T713
Test name
Test status
Simulation time 119013109 ps
CPU time 5.65 seconds
Started Mar 05 01:23:00 PM PST 24
Finished Mar 05 01:23:06 PM PST 24
Peak memory 248364 kb
Host smart-0e4daecb-76c6-48ed-99e5-60afcc19e105
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861820489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.861820489
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3833341429
Short name T800
Test name
Test status
Simulation time 3753669885 ps
CPU time 68.03 seconds
Started Mar 05 01:22:10 PM PST 24
Finished Mar 05 01:23:19 PM PST 24
Peak memory 236340 kb
Host smart-2fcced12-560d-46f4-ac95-aca6038ca416
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3833341429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3833341429
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.393194513
Short name T740
Test name
Test status
Simulation time 855383973 ps
CPU time 105.37 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:24:04 PM PST 24
Peak memory 240164 kb
Host smart-9c25e3e9-f9f4-4def-8005-343d37c5b021
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=393194513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.393194513
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.993240045
Short name T831
Test name
Test status
Simulation time 46963242 ps
CPU time 6.34 seconds
Started Mar 05 01:22:12 PM PST 24
Finished Mar 05 01:22:19 PM PST 24
Peak memory 240244 kb
Host smart-16f3247e-f838-4b6b-9e20-cceb5459c92c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993240045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.993240045
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.997370063
Short name T718
Test name
Test status
Simulation time 71757347 ps
CPU time 6.62 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:22:25 PM PST 24
Peak memory 240380 kb
Host smart-d55746b4-3953-4855-95a1-16289ce014ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997370063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.997370063
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2574983883
Short name T766
Test name
Test status
Simulation time 369702521 ps
CPU time 8.08 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:22:35 PM PST 24
Peak memory 236332 kb
Host smart-38c49494-0530-4276-8839-c37447537d8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2574983883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2574983883
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4085965274
Short name T348
Test name
Test status
Simulation time 9902584 ps
CPU time 1.3 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:22:20 PM PST 24
Peak memory 235532 kb
Host smart-ca565cdb-0492-4623-bc13-c5940ad52d37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4085965274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4085965274
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.532544578
Short name T191
Test name
Test status
Simulation time 627266221 ps
CPU time 39.1 seconds
Started Mar 05 01:22:17 PM PST 24
Finished Mar 05 01:22:57 PM PST 24
Peak memory 243716 kb
Host smart-d7730d9c-591c-4282-a1f7-a47900db1223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=532544578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.532544578
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.490212471
Short name T149
Test name
Test status
Simulation time 109910845027 ps
CPU time 538 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:31:25 PM PST 24
Peak memory 265216 kb
Host smart-5d4d09fc-d50a-4b3b-a9ee-c60ecfbf6bc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490212471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.490212471
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3948018977
Short name T809
Test name
Test status
Simulation time 1931933139 ps
CPU time 27.68 seconds
Started Mar 05 01:22:17 PM PST 24
Finished Mar 05 01:22:46 PM PST 24
Peak memory 247632 kb
Host smart-82a2045a-1c1f-4f91-ae68-9fe88906448d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3948018977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3948018977
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3193286153
Short name T739
Test name
Test status
Simulation time 6474293 ps
CPU time 1.4 seconds
Started Mar 05 01:23:00 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 235524 kb
Host smart-4e3050bd-1338-4b27-be76-417f5abbad07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3193286153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3193286153
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1334198086
Short name T804
Test name
Test status
Simulation time 6861104 ps
CPU time 1.44 seconds
Started Mar 05 01:22:59 PM PST 24
Finished Mar 05 01:23:01 PM PST 24
Peak memory 236432 kb
Host smart-6be49027-19f1-4f7f-825a-2eefaad9c6a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334198086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1334198086
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1353966854
Short name T743
Test name
Test status
Simulation time 10602506 ps
CPU time 1.35 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 236424 kb
Host smart-08e3924a-92a1-4cbb-93da-cd0a32dadc9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1353966854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1353966854
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.680483427
Short name T725
Test name
Test status
Simulation time 9972800 ps
CPU time 1.37 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 235544 kb
Host smart-82297c79-1086-47b1-90f0-0e47a91975fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=680483427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.680483427
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2082741216
Short name T731
Test name
Test status
Simulation time 11529735 ps
CPU time 1.58 seconds
Started Mar 05 01:22:59 PM PST 24
Finished Mar 05 01:23:00 PM PST 24
Peak memory 236328 kb
Host smart-7e689656-db4f-4d34-938e-25175a93b8ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2082741216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2082741216
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.301069173
Short name T737
Test name
Test status
Simulation time 14262356 ps
CPU time 1.59 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 236420 kb
Host smart-d475e12d-c9c5-490e-a68f-4b02016414f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301069173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.301069173
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3456036646
Short name T795
Test name
Test status
Simulation time 15670139 ps
CPU time 1.32 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 235552 kb
Host smart-b3e74d93-00bd-43d4-ab02-f8c5dcb4c06d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3456036646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3456036646
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.4282976683
Short name T815
Test name
Test status
Simulation time 10101384 ps
CPU time 1.43 seconds
Started Mar 05 01:23:03 PM PST 24
Finished Mar 05 01:23:05 PM PST 24
Peak memory 236332 kb
Host smart-a9903dc5-7166-4478-8fb1-3c01dc138355
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4282976683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.4282976683
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.4128019210
Short name T813
Test name
Test status
Simulation time 3416549830 ps
CPU time 235.57 seconds
Started Mar 05 01:22:26 PM PST 24
Finished Mar 05 01:26:22 PM PST 24
Peak memory 238408 kb
Host smart-e3614d46-e8ef-4e81-b4c7-7174ff31ad38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4128019210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.4128019210
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1781972456
Short name T757
Test name
Test status
Simulation time 26740291234 ps
CPU time 256.1 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:26:41 PM PST 24
Peak memory 236392 kb
Host smart-14d8e3f3-da98-4782-886e-7afa527ec1ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1781972456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1781972456
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3648400382
Short name T786
Test name
Test status
Simulation time 109574946 ps
CPU time 8.92 seconds
Started Mar 05 01:22:11 PM PST 24
Finished Mar 05 01:22:20 PM PST 24
Peak memory 240316 kb
Host smart-6962f5ec-2b2a-44f0-b1c3-66aa7f836a05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3648400382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3648400382
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2081715609
Short name T798
Test name
Test status
Simulation time 526024450 ps
CPU time 9.87 seconds
Started Mar 05 01:22:21 PM PST 24
Finished Mar 05 01:22:31 PM PST 24
Peak memory 250604 kb
Host smart-c7c679d9-3307-46f3-8f06-b40bbfc9a1f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081715609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2081715609
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.4282186847
Short name T187
Test name
Test status
Simulation time 646052176 ps
CPU time 7.79 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:22:37 PM PST 24
Peak memory 236272 kb
Host smart-478d4a82-8755-4f8e-860c-95e82afff231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4282186847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4282186847
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.3114478830
Short name T781
Test name
Test status
Simulation time 25230605 ps
CPU time 1.47 seconds
Started Mar 05 01:22:25 PM PST 24
Finished Mar 05 01:22:26 PM PST 24
Peak memory 236420 kb
Host smart-459594a5-595d-462c-b214-5d9f3374d3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3114478830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.3114478830
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2029600605
Short name T779
Test name
Test status
Simulation time 1235443867 ps
CPU time 41.8 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:23:06 PM PST 24
Peak memory 243716 kb
Host smart-74326cd0-b413-4f1c-9043-40952c9eb33d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2029600605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2029600605
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2763780028
Short name T121
Test name
Test status
Simulation time 1971491721 ps
CPU time 121.75 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:24:32 PM PST 24
Peak memory 257104 kb
Host smart-a902947f-24ca-4595-b110-e6a4301a2015
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2763780028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2763780028
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3566391926
Short name T353
Test name
Test status
Simulation time 2517219719 ps
CPU time 283.26 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:27:10 PM PST 24
Peak memory 267856 kb
Host smart-e398d4fa-3bfb-43b4-aec7-d888138b3bcc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566391926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3566391926
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3290952415
Short name T817
Test name
Test status
Simulation time 1375334027 ps
CPU time 22.94 seconds
Started Mar 05 01:22:33 PM PST 24
Finished Mar 05 01:22:56 PM PST 24
Peak memory 248712 kb
Host smart-a0d67b94-f801-4f26-b49c-6034e9946739
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3290952415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3290952415
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.645961258
Short name T760
Test name
Test status
Simulation time 14947135 ps
CPU time 1.43 seconds
Started Mar 05 01:23:00 PM PST 24
Finished Mar 05 01:23:01 PM PST 24
Peak memory 235536 kb
Host smart-86637c2d-d48c-44da-a002-37620ed78de5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=645961258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.645961258
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2269252224
Short name T717
Test name
Test status
Simulation time 10076078 ps
CPU time 1.5 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 234624 kb
Host smart-e490a9e4-8f8c-4efc-840c-65f3014a490f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2269252224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2269252224
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.4135849454
Short name T814
Test name
Test status
Simulation time 8742572 ps
CPU time 1.51 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 235612 kb
Host smart-316e4de1-923e-4f23-8516-f905a36f9212
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4135849454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.4135849454
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3339555942
Short name T832
Test name
Test status
Simulation time 15306652 ps
CPU time 1.5 seconds
Started Mar 05 01:23:03 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 234544 kb
Host smart-a5b5095a-8504-4266-b31f-222bf6e7beb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3339555942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3339555942
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1893610913
Short name T746
Test name
Test status
Simulation time 32429643 ps
CPU time 1.39 seconds
Started Mar 05 01:22:59 PM PST 24
Finished Mar 05 01:23:01 PM PST 24
Peak memory 235552 kb
Host smart-de88a24a-3c87-48c9-9a42-84762e559dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1893610913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1893610913
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2820219478
Short name T792
Test name
Test status
Simulation time 6465517 ps
CPU time 1.43 seconds
Started Mar 05 01:22:59 PM PST 24
Finished Mar 05 01:23:00 PM PST 24
Peak memory 235436 kb
Host smart-95c98c94-fe68-41fb-9dcb-e898333362af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2820219478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2820219478
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3050444106
Short name T753
Test name
Test status
Simulation time 14593452 ps
CPU time 1.73 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 235548 kb
Host smart-5cc3dd40-06f1-400f-b981-035cdd7a2bb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3050444106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3050444106
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.681347050
Short name T344
Test name
Test status
Simulation time 18112165 ps
CPU time 1.27 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 235620 kb
Host smart-415df063-305a-4db2-ac92-66c3c0488fc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=681347050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.681347050
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2014261236
Short name T726
Test name
Test status
Simulation time 12605204 ps
CPU time 1.35 seconds
Started Mar 05 01:23:04 PM PST 24
Finished Mar 05 01:23:05 PM PST 24
Peak memory 236432 kb
Host smart-fb6ed2c4-9919-452c-845d-f595e18ec187
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2014261236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2014261236
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3317920927
Short name T722
Test name
Test status
Simulation time 9223125 ps
CPU time 1.55 seconds
Started Mar 05 01:23:01 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 236420 kb
Host smart-d4aed980-a309-4535-a532-5178702d39e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3317920927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3317920927
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2732516388
Short name T188
Test name
Test status
Simulation time 8491716746 ps
CPU time 145.75 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:24:50 PM PST 24
Peak memory 240200 kb
Host smart-cf607e2f-d4ad-4731-8a05-010ee1eee06e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2732516388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2732516388
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4141123000
Short name T801
Test name
Test status
Simulation time 28466393060 ps
CPU time 558.68 seconds
Started Mar 05 01:22:19 PM PST 24
Finished Mar 05 01:31:38 PM PST 24
Peak memory 236392 kb
Host smart-2ecd87af-b40e-4ed6-a9dc-783f095d65a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4141123000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4141123000
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.854912153
Short name T818
Test name
Test status
Simulation time 39479908 ps
CPU time 3.87 seconds
Started Mar 05 01:22:26 PM PST 24
Finished Mar 05 01:22:31 PM PST 24
Peak memory 240256 kb
Host smart-9dfc3e59-c2e2-452f-ad0e-25cd74e25743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=854912153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.854912153
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.89007260
Short name T352
Test name
Test status
Simulation time 133246413 ps
CPU time 10.08 seconds
Started Mar 05 01:22:26 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 239568 kb
Host smart-14b70218-dcac-4500-b07c-f274c6fa757e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89007260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 4.alert_handler_csr_mem_rw_with_rand_reset.89007260
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2881711711
Short name T759
Test name
Test status
Simulation time 128558277 ps
CPU time 5.44 seconds
Started Mar 05 01:22:32 PM PST 24
Finished Mar 05 01:22:38 PM PST 24
Peak memory 236340 kb
Host smart-3690a42b-055c-4173-894a-252aadf3120d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2881711711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2881711711
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2070935734
Short name T827
Test name
Test status
Simulation time 13453335 ps
CPU time 1.27 seconds
Started Mar 05 01:22:28 PM PST 24
Finished Mar 05 01:22:30 PM PST 24
Peak memory 234512 kb
Host smart-e273e5ad-375b-4950-8496-0b9a4693d9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2070935734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2070935734
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.593836163
Short name T723
Test name
Test status
Simulation time 122084276 ps
CPU time 12.01 seconds
Started Mar 05 01:22:17 PM PST 24
Finished Mar 05 01:22:29 PM PST 24
Peak memory 240320 kb
Host smart-d3e87609-e976-4c3d-a95a-0ea4a172d855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=593836163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.593836163
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4161648073
Short name T826
Test name
Test status
Simulation time 4636212816 ps
CPU time 331.84 seconds
Started Mar 05 01:22:28 PM PST 24
Finished Mar 05 01:28:00 PM PST 24
Peak memory 265312 kb
Host smart-470df1b2-3770-4386-9fd0-062dde4accaf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161648073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4161648073
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1516934119
Short name T742
Test name
Test status
Simulation time 503760400 ps
CPU time 16.17 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:22:35 PM PST 24
Peak memory 254304 kb
Host smart-582f2f4d-a739-4e08-9b7a-60c224749a6f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1516934119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1516934119
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2840041765
Short name T716
Test name
Test status
Simulation time 24451602 ps
CPU time 1.28 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:03 PM PST 24
Peak memory 236432 kb
Host smart-8e3ff1c9-3c8c-46cd-a906-dbf7173c9f48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2840041765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2840041765
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1810777629
Short name T720
Test name
Test status
Simulation time 11450345 ps
CPU time 1.48 seconds
Started Mar 05 01:23:04 PM PST 24
Finished Mar 05 01:23:05 PM PST 24
Peak memory 234536 kb
Host smart-b579d72b-3082-4927-8965-5f06a8468527
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1810777629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1810777629
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2638849829
Short name T802
Test name
Test status
Simulation time 27697196 ps
CPU time 1.52 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 236420 kb
Host smart-7dabb931-99ca-4d2b-8d53-166d03c75648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638849829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2638849829
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1893363735
Short name T821
Test name
Test status
Simulation time 8907448 ps
CPU time 1.56 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 236432 kb
Host smart-2cffbdf8-d256-4c86-99ea-4f79b3e6b79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1893363735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1893363735
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.4057596271
Short name T347
Test name
Test status
Simulation time 10250732 ps
CPU time 1.41 seconds
Started Mar 05 01:23:03 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 234536 kb
Host smart-b5ac5a48-0737-4576-8e5b-c948b2ad3ea1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4057596271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.4057596271
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3687545435
Short name T156
Test name
Test status
Simulation time 8497618 ps
CPU time 1.44 seconds
Started Mar 05 01:23:02 PM PST 24
Finished Mar 05 01:23:04 PM PST 24
Peak memory 234536 kb
Host smart-f4b2744f-d36b-4b6c-9cf7-b1f39a45d1c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3687545435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3687545435
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2887309263
Short name T732
Test name
Test status
Simulation time 7881137 ps
CPU time 1.54 seconds
Started Mar 05 01:23:04 PM PST 24
Finished Mar 05 01:23:06 PM PST 24
Peak memory 235564 kb
Host smart-7e3384e5-b1ef-4e1e-b90e-c260012177c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2887309263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2887309263
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3028824028
Short name T763
Test name
Test status
Simulation time 15227284 ps
CPU time 1.5 seconds
Started Mar 05 01:23:00 PM PST 24
Finished Mar 05 01:23:02 PM PST 24
Peak memory 236404 kb
Host smart-f10c627d-5b1b-4bbd-846e-32ece00a4c47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3028824028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3028824028
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1046358905
Short name T812
Test name
Test status
Simulation time 7539070 ps
CPU time 1.5 seconds
Started Mar 05 01:23:16 PM PST 24
Finished Mar 05 01:23:18 PM PST 24
Peak memory 235536 kb
Host smart-02e6177f-2741-4099-a1a1-cb1ddb4ba86a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1046358905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1046358905
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.43142159
Short name T810
Test name
Test status
Simulation time 11820374 ps
CPU time 1.37 seconds
Started Mar 05 01:23:12 PM PST 24
Finished Mar 05 01:23:13 PM PST 24
Peak memory 236328 kb
Host smart-77f191b7-ebc0-4460-a67a-8e69e3a7938f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=43142159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.43142159
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2200737791
Short name T778
Test name
Test status
Simulation time 161073602 ps
CPU time 6.95 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 240124 kb
Host smart-02332c5c-d2c5-4517-972e-9b2756e2178f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200737791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2200737791
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.459666758
Short name T727
Test name
Test status
Simulation time 1294002931 ps
CPU time 9 seconds
Started Mar 05 01:22:20 PM PST 24
Finished Mar 05 01:22:30 PM PST 24
Peak memory 236200 kb
Host smart-15ed1e78-5911-4c50-b126-bc81d6a1c9ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=459666758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.459666758
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.810635385
Short name T758
Test name
Test status
Simulation time 17388849 ps
CPU time 1.37 seconds
Started Mar 05 01:22:25 PM PST 24
Finished Mar 05 01:22:27 PM PST 24
Peak memory 235540 kb
Host smart-7d599f12-d7dd-4e83-a4ff-77a6126008a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=810635385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.810635385
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1525893751
Short name T729
Test name
Test status
Simulation time 993832956 ps
CPU time 18.53 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:22:41 PM PST 24
Peak memory 240264 kb
Host smart-0558a2b6-0b17-4c2e-aaa9-b901353f860d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1525893751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1525893751
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.476102661
Short name T138
Test name
Test status
Simulation time 3089147353 ps
CPU time 85.52 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:23:44 PM PST 24
Peak memory 256928 kb
Host smart-5b83bfed-d6e1-4441-9b18-2d747ae698d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=476102661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.476102661
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3792269362
Short name T125
Test name
Test status
Simulation time 36589443880 ps
CPU time 317.94 seconds
Started Mar 05 01:22:18 PM PST 24
Finished Mar 05 01:27:36 PM PST 24
Peak memory 265204 kb
Host smart-d0c3d531-e051-4401-806b-36809e391f62
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792269362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3792269362
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.945609205
Short name T715
Test name
Test status
Simulation time 44814452 ps
CPU time 6.05 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:22:33 PM PST 24
Peak memory 248540 kb
Host smart-6ffac91d-f202-4e11-a9ad-6b7d479ba863
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=945609205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.945609205
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2841484837
Short name T172
Test name
Test status
Simulation time 86321557 ps
CPU time 4.93 seconds
Started Mar 05 01:22:33 PM PST 24
Finished Mar 05 01:22:38 PM PST 24
Peak memory 236600 kb
Host smart-8bb48966-e443-499b-a9fb-b8101c863a98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841484837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2841484837
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1257096249
Short name T797
Test name
Test status
Simulation time 21555752 ps
CPU time 3.56 seconds
Started Mar 05 01:22:31 PM PST 24
Finished Mar 05 01:22:36 PM PST 24
Peak memory 239272 kb
Host smart-1a5a1c86-71de-4eaa-8aa5-1e732be651bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1257096249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1257096249
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3176885856
Short name T825
Test name
Test status
Simulation time 11496149 ps
CPU time 1.69 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:22:32 PM PST 24
Peak memory 236424 kb
Host smart-0cf022c5-98c3-4ca5-836d-30b2dc153759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3176885856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3176885856
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1625428911
Short name T735
Test name
Test status
Simulation time 2063023566 ps
CPU time 38.53 seconds
Started Mar 05 01:22:31 PM PST 24
Finished Mar 05 01:23:09 PM PST 24
Peak memory 244444 kb
Host smart-f84b0413-cdc9-4a0a-80c9-64e50b775913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1625428911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1625428911
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1119629940
Short name T113
Test name
Test status
Simulation time 2880408615 ps
CPU time 85.83 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:23:50 PM PST 24
Peak memory 257012 kb
Host smart-4b36a6f0-cb7e-4a91-83b7-07de2ea29628
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1119629940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1119629940
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3464556936
Short name T803
Test name
Test status
Simulation time 2891913200 ps
CPU time 30.73 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:22:53 PM PST 24
Peak memory 253528 kb
Host smart-f6e7a7d3-e734-4014-813e-1da589ddd6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3464556936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3464556936
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1394389865
Short name T785
Test name
Test status
Simulation time 35327426 ps
CPU time 4.73 seconds
Started Mar 05 01:22:37 PM PST 24
Finished Mar 05 01:22:42 PM PST 24
Peak memory 256736 kb
Host smart-d27e53ae-9ecc-4283-a699-c594edae60fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394389865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1394389865
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.405338858
Short name T741
Test name
Test status
Simulation time 391186192 ps
CPU time 9.04 seconds
Started Mar 05 01:22:20 PM PST 24
Finished Mar 05 01:22:29 PM PST 24
Peak memory 236332 kb
Host smart-8b9449a5-d848-4f4f-9e17-b3a02014303f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=405338858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.405338858
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1672048680
Short name T752
Test name
Test status
Simulation time 7132657 ps
CPU time 1.46 seconds
Started Mar 05 01:22:24 PM PST 24
Finished Mar 05 01:22:25 PM PST 24
Peak memory 235540 kb
Host smart-f2ac0393-1d78-4fa8-8897-1d5620573a4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1672048680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1672048680
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.222153107
Short name T721
Test name
Test status
Simulation time 1715965809 ps
CPU time 40.97 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:23:08 PM PST 24
Peak memory 248548 kb
Host smart-c48f6258-75b1-47b2-920a-65ceaf30452a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=222153107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.222153107
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4181258952
Short name T123
Test name
Test status
Simulation time 4997647714 ps
CPU time 332.78 seconds
Started Mar 05 01:22:32 PM PST 24
Finished Mar 05 01:28:05 PM PST 24
Peak memory 265184 kb
Host smart-4fd47142-c8bb-49d4-9085-b7d8d4e63840
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4181258952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4181258952
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.754282363
Short name T764
Test name
Test status
Simulation time 184963419 ps
CPU time 15.4 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:22:45 PM PST 24
Peak memory 251852 kb
Host smart-cdee7034-98fe-4eca-8254-d6c3d88ec816
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=754282363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.754282363
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3860254916
Short name T829
Test name
Test status
Simulation time 188602295 ps
CPU time 13.24 seconds
Started Mar 05 01:22:26 PM PST 24
Finished Mar 05 01:22:39 PM PST 24
Peak memory 249616 kb
Host smart-15c95afc-b21b-4acf-b5b3-0e1f1de64728
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860254916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3860254916
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1218902424
Short name T355
Test name
Test status
Simulation time 267276200 ps
CPU time 8.8 seconds
Started Mar 05 01:22:22 PM PST 24
Finished Mar 05 01:22:31 PM PST 24
Peak memory 236328 kb
Host smart-3191b17f-1f41-4277-86e6-aa4e81d3b6b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1218902424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1218902424
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1048344043
Short name T155
Test name
Test status
Simulation time 8772047 ps
CPU time 1.54 seconds
Started Mar 05 01:22:25 PM PST 24
Finished Mar 05 01:22:27 PM PST 24
Peak memory 236408 kb
Host smart-1ca4141f-e636-4581-b3e0-6167ca6bba5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1048344043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1048344043
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3035426187
Short name T189
Test name
Test status
Simulation time 1411253236 ps
CPU time 28.2 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:22:52 PM PST 24
Peak memory 240396 kb
Host smart-d540e70b-f06f-4e01-a6ce-a7a2bda953b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3035426187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3035426187
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1148670459
Short name T127
Test name
Test status
Simulation time 1102421847 ps
CPU time 108.85 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:24:18 PM PST 24
Peak memory 256772 kb
Host smart-810fb4ec-8560-4e77-a751-6b38ecd4531c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1148670459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1148670459
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1181006939
Short name T131
Test name
Test status
Simulation time 69536234829 ps
CPU time 1228.54 seconds
Started Mar 05 01:22:23 PM PST 24
Finished Mar 05 01:42:52 PM PST 24
Peak memory 265180 kb
Host smart-cb43c9e3-00c2-4d32-a896-d89c2df45919
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181006939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1181006939
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3485725333
Short name T776
Test name
Test status
Simulation time 311792317 ps
CPU time 6.79 seconds
Started Mar 05 01:22:25 PM PST 24
Finished Mar 05 01:22:33 PM PST 24
Peak memory 248524 kb
Host smart-fdb88d17-04d7-4ba5-9ce2-690db1900bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3485725333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3485725333
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3668515318
Short name T789
Test name
Test status
Simulation time 204796685 ps
CPU time 7.82 seconds
Started Mar 05 01:22:35 PM PST 24
Finished Mar 05 01:22:43 PM PST 24
Peak memory 240388 kb
Host smart-bdaf6084-7f9b-4be9-90a4-c8e587491bc6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668515318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3668515318
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.930604791
Short name T806
Test name
Test status
Simulation time 22971792 ps
CPU time 3.45 seconds
Started Mar 05 01:22:30 PM PST 24
Finished Mar 05 01:22:34 PM PST 24
Peak memory 240148 kb
Host smart-a5dfb738-8875-4ce9-8254-fe144043383c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=930604791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.930604791
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2847999418
Short name T811
Test name
Test status
Simulation time 46565914 ps
CPU time 1.34 seconds
Started Mar 05 01:22:28 PM PST 24
Finished Mar 05 01:22:30 PM PST 24
Peak memory 235612 kb
Host smart-b2cf492b-9fe3-444d-afa0-bf5fa936efb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2847999418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2847999418
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3320262293
Short name T783
Test name
Test status
Simulation time 13473135755 ps
CPU time 50.27 seconds
Started Mar 05 01:22:39 PM PST 24
Finished Mar 05 01:23:30 PM PST 24
Peak memory 244540 kb
Host smart-c7f40036-1e08-4dfd-95dd-79d175420ee6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3320262293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3320262293
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.185666902
Short name T118
Test name
Test status
Simulation time 2592416684 ps
CPU time 166.99 seconds
Started Mar 05 01:22:35 PM PST 24
Finished Mar 05 01:25:22 PM PST 24
Peak memory 256984 kb
Host smart-5efa910b-0c8a-4436-b2b0-1d3b6a457017
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=185666902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.185666902
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.521327063
Short name T130
Test name
Test status
Simulation time 57625969674 ps
CPU time 934.9 seconds
Started Mar 05 01:22:27 PM PST 24
Finished Mar 05 01:38:02 PM PST 24
Peak memory 272928 kb
Host smart-feb563fd-1d5a-4ea9-9234-7f9c0347a086
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521327063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.521327063
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2627722576
Short name T793
Test name
Test status
Simulation time 1499910639 ps
CPU time 25.3 seconds
Started Mar 05 01:22:29 PM PST 24
Finished Mar 05 01:22:54 PM PST 24
Peak memory 247484 kb
Host smart-c41bdbd5-4180-48ed-8556-b40749c699e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2627722576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2627722576
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3794913950
Short name T273
Test name
Test status
Simulation time 9217049317 ps
CPU time 654.46 seconds
Started Mar 05 01:57:33 PM PST 24
Finished Mar 05 02:08:27 PM PST 24
Peak memory 265436 kb
Host smart-9906e8aa-6606-49be-9d45-b438d1bad1d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794913950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3794913950
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2800519936
Short name T616
Test name
Test status
Simulation time 347494474 ps
CPU time 10.45 seconds
Started Mar 05 01:57:32 PM PST 24
Finished Mar 05 01:57:43 PM PST 24
Peak memory 240432 kb
Host smart-3a4dc6fa-3bc4-4266-9344-7f5a060b0a32
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2800519936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2800519936
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2303763042
Short name T652
Test name
Test status
Simulation time 696309870 ps
CPU time 18.65 seconds
Started Mar 05 01:57:35 PM PST 24
Finished Mar 05 01:57:53 PM PST 24
Peak memory 248568 kb
Host smart-3e6c9c20-1f5d-4757-8032-78cd768fb72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037
63042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2303763042
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.989340691
Short name T179
Test name
Test status
Simulation time 616571458 ps
CPU time 18.16 seconds
Started Mar 05 01:57:34 PM PST 24
Finished Mar 05 01:57:52 PM PST 24
Peak memory 248552 kb
Host smart-ab21ac44-a237-41fe-8b0b-46e8000ce40a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98934
0691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.989340691
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2918307452
Short name T336
Test name
Test status
Simulation time 47052744601 ps
CPU time 1318.94 seconds
Started Mar 05 01:57:32 PM PST 24
Finished Mar 05 02:19:32 PM PST 24
Peak memory 286796 kb
Host smart-4b62c8c9-7dcc-4fbd-bf82-db1bce78dd74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918307452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2918307452
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3307831782
Short name T100
Test name
Test status
Simulation time 172433212814 ps
CPU time 1291.09 seconds
Started Mar 05 01:57:32 PM PST 24
Finished Mar 05 02:19:04 PM PST 24
Peak memory 272304 kb
Host smart-41deaa18-8709-4526-a006-d918621f729b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307831782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3307831782
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3912430801
Short name T710
Test name
Test status
Simulation time 3941815293 ps
CPU time 102.25 seconds
Started Mar 05 01:57:34 PM PST 24
Finished Mar 05 01:59:16 PM PST 24
Peak memory 247848 kb
Host smart-7f559b5e-9b48-4a5d-8727-a20400909137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912430801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3912430801
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2276958151
Short name T400
Test name
Test status
Simulation time 4633493760 ps
CPU time 50.45 seconds
Started Mar 05 01:57:34 PM PST 24
Finished Mar 05 01:58:24 PM PST 24
Peak memory 249040 kb
Host smart-a4602377-8de9-44e7-81b1-9f4ff7591de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22769
58151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2276958151
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.584106484
Short name T278
Test name
Test status
Simulation time 399254819 ps
CPU time 34.41 seconds
Started Mar 05 01:57:35 PM PST 24
Finished Mar 05 01:58:09 PM PST 24
Peak memory 247672 kb
Host smart-f9fa5d7e-0b14-4b86-8723-bc169a990c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58410
6484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.584106484
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.1099275333
Short name T33
Test name
Test status
Simulation time 1361479221 ps
CPU time 21.26 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 01:58:00 PM PST 24
Peak memory 269160 kb
Host smart-9da98dcb-be8c-4426-97ad-f97b37eb6353
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1099275333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1099275333
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3471782430
Short name T561
Test name
Test status
Simulation time 595132861 ps
CPU time 13.72 seconds
Started Mar 05 01:57:33 PM PST 24
Finished Mar 05 01:57:47 PM PST 24
Peak memory 248992 kb
Host smart-5023a973-f3dc-4a98-bbf5-94b1d2d0e85f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34717
82430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3471782430
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2163091191
Short name T445
Test name
Test status
Simulation time 381450924 ps
CPU time 24.84 seconds
Started Mar 05 01:57:34 PM PST 24
Finished Mar 05 01:57:59 PM PST 24
Peak memory 248916 kb
Host smart-531308a0-ef2f-4273-a670-dce70da9d47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630
91191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2163091191
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.984543953
Short name T453
Test name
Test status
Simulation time 63143608480 ps
CPU time 841.89 seconds
Started Mar 05 01:57:31 PM PST 24
Finished Mar 05 02:11:33 PM PST 24
Peak memory 257240 kb
Host smart-0906779c-6a01-41da-bba0-b91e321614fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984543953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.984543953
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3728348159
Short name T706
Test name
Test status
Simulation time 17928687280 ps
CPU time 1340.51 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 02:20:00 PM PST 24
Peak memory 282388 kb
Host smart-449431d0-7212-4f00-9e45-f2be47addc69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728348159 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3728348159
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1008259512
Short name T611
Test name
Test status
Simulation time 186388797902 ps
CPU time 2640.17 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 02:41:39 PM PST 24
Peak memory 282652 kb
Host smart-f713c291-a24a-4bbb-9a05-2b1815a8db96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008259512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1008259512
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.411604108
Short name T519
Test name
Test status
Simulation time 825557766 ps
CPU time 11.52 seconds
Started Mar 05 01:57:47 PM PST 24
Finished Mar 05 01:57:59 PM PST 24
Peak memory 248980 kb
Host smart-8d4e73b2-aae4-4245-93f6-13dc6afdca20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=411604108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.411604108
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2656050396
Short name T685
Test name
Test status
Simulation time 1260696154 ps
CPU time 17.57 seconds
Started Mar 05 01:57:37 PM PST 24
Finished Mar 05 01:57:55 PM PST 24
Peak memory 253476 kb
Host smart-34b8e9f9-5d6e-41ea-8442-8c374521135b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26560
50396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2656050396
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1762363887
Short name T181
Test name
Test status
Simulation time 59515974 ps
CPU time 3.04 seconds
Started Mar 05 01:57:40 PM PST 24
Finished Mar 05 01:57:43 PM PST 24
Peak memory 239076 kb
Host smart-2d58484f-ed33-42b2-9c18-38405283ff2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
63887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1762363887
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.2994032651
Short name T4
Test name
Test status
Simulation time 131711182876 ps
CPU time 1939.01 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 02:29:58 PM PST 24
Peak memory 272980 kb
Host smart-528b09c4-73f3-4ca7-b7e9-daef3242c2fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994032651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.2994032651
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3340812914
Short name T646
Test name
Test status
Simulation time 54245045540 ps
CPU time 1537.48 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 02:23:16 PM PST 24
Peak memory 272104 kb
Host smart-c99d0300-71a3-41d3-9823-caef77c12de7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340812914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3340812914
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2636670720
Short name T63
Test name
Test status
Simulation time 516072432 ps
CPU time 32.86 seconds
Started Mar 05 01:57:39 PM PST 24
Finished Mar 05 01:58:12 PM PST 24
Peak memory 248980 kb
Host smart-ebb888f2-c2d5-41a2-96a1-1bd9e74480a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26366
70720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2636670720
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3466356173
Short name T566
Test name
Test status
Simulation time 9447893393 ps
CPU time 80.25 seconds
Started Mar 05 01:57:40 PM PST 24
Finished Mar 05 01:59:01 PM PST 24
Peak memory 248744 kb
Host smart-556313d3-cc40-44a8-8c9c-4f3cfc2a6c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34663
56173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3466356173
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.436013525
Short name T12
Test name
Test status
Simulation time 2666194017 ps
CPU time 57.33 seconds
Started Mar 05 01:57:45 PM PST 24
Finished Mar 05 01:58:43 PM PST 24
Peak memory 277828 kb
Host smart-9188244b-541a-45f6-9ed6-e67ac627bed7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=436013525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.436013525
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2441383558
Short name T101
Test name
Test status
Simulation time 373637746 ps
CPU time 23.64 seconds
Started Mar 05 01:57:40 PM PST 24
Finished Mar 05 01:58:04 PM PST 24
Peak memory 247360 kb
Host smart-b318205c-220b-4cd0-80c7-0f8a576eb1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24413
83558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2441383558
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3818906470
Short name T356
Test name
Test status
Simulation time 144889873 ps
CPU time 15.21 seconds
Started Mar 05 01:57:37 PM PST 24
Finished Mar 05 01:57:53 PM PST 24
Peak memory 248976 kb
Host smart-d5c5c924-79c0-44c7-9217-faf9c5bb1abc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38189
06470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3818906470
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3164436594
Short name T21
Test name
Test status
Simulation time 16007051704 ps
CPU time 1402.51 seconds
Started Mar 05 01:57:49 PM PST 24
Finished Mar 05 02:21:12 PM PST 24
Peak memory 289292 kb
Host smart-199fd36d-70e1-41db-ba44-6813eecb320e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164436594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3164436594
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2257421386
Short name T291
Test name
Test status
Simulation time 463588453168 ps
CPU time 2339.85 seconds
Started Mar 05 01:58:25 PM PST 24
Finished Mar 05 02:37:25 PM PST 24
Peak memory 273480 kb
Host smart-3240bf78-eb1e-441f-ad96-c2c8bf6fa945
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257421386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2257421386
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.859021467
Short name T451
Test name
Test status
Simulation time 5339090554 ps
CPU time 25.31 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 01:58:58 PM PST 24
Peak memory 240848 kb
Host smart-c79e4678-a4b2-4f4a-ab97-5d11ca6bf80c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=859021467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.859021467
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1508920103
Short name T681
Test name
Test status
Simulation time 339682498 ps
CPU time 31.13 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 01:58:57 PM PST 24
Peak memory 256696 kb
Host smart-dc23f09b-7a04-40fd-8fb4-855e9f5bbbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15089
20103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1508920103
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.1617364077
Short name T679
Test name
Test status
Simulation time 702879453 ps
CPU time 18.18 seconds
Started Mar 05 01:58:28 PM PST 24
Finished Mar 05 01:58:46 PM PST 24
Peak memory 255440 kb
Host smart-c0ea1816-04d6-4611-ad71-11edfbd06612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
64077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.1617364077
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.458348429
Short name T343
Test name
Test status
Simulation time 64312124338 ps
CPU time 1273.22 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 02:19:48 PM PST 24
Peak memory 288904 kb
Host smart-3ca6c696-d67d-4f7c-97dc-d60aa00a8de5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458348429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.458348429
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2710274603
Short name T683
Test name
Test status
Simulation time 12358716908 ps
CPU time 1244.11 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 02:19:19 PM PST 24
Peak memory 273428 kb
Host smart-34e8d41a-4161-43f8-977f-aa539e290e19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710274603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2710274603
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3317281263
Short name T302
Test name
Test status
Simulation time 3919725854 ps
CPU time 159.16 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 02:01:05 PM PST 24
Peak memory 247956 kb
Host smart-7b9cf9e0-e577-48dd-baa8-ea3858a3c42d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317281263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3317281263
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1591197527
Short name T516
Test name
Test status
Simulation time 250522601 ps
CPU time 28.59 seconds
Started Mar 05 01:58:25 PM PST 24
Finished Mar 05 01:58:54 PM PST 24
Peak memory 255536 kb
Host smart-4d81874c-a88d-46ed-ab9b-7bfa3f015595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15911
97527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1591197527
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3034963607
Short name T492
Test name
Test status
Simulation time 53817127 ps
CPU time 4.83 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 01:58:38 PM PST 24
Peak memory 239064 kb
Host smart-3bddb9c9-a75c-4524-9f76-9c3fb0753f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30349
63607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3034963607
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.231279944
Short name T377
Test name
Test status
Simulation time 1164468068 ps
CPU time 75.1 seconds
Started Mar 05 01:58:27 PM PST 24
Finished Mar 05 01:59:42 PM PST 24
Peak memory 255316 kb
Host smart-fc7c992f-a57e-4ba0-87c4-b1ac4fee3e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23127
9944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.231279944
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1909708457
Short name T700
Test name
Test status
Simulation time 5934518498 ps
CPU time 34.26 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 01:59:01 PM PST 24
Peak memory 255544 kb
Host smart-bd6b4278-e7c5-4d74-b71b-7588a13fc7f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19097
08457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1909708457
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4087676428
Short name T205
Test name
Test status
Simulation time 9846761683 ps
CPU time 53.32 seconds
Started Mar 05 01:58:27 PM PST 24
Finished Mar 05 01:59:20 PM PST 24
Peak memory 250064 kb
Host smart-b273a9ca-990e-48bf-9e4a-0f51e25d317c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087676428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4087676428
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1876833307
Short name T178
Test name
Test status
Simulation time 14233216 ps
CPU time 2.66 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 01:58:37 PM PST 24
Peak memory 249148 kb
Host smart-f7b5a8b7-9f44-45c9-b780-9b18623b5b07
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1876833307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1876833307
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3954202038
Short name T631
Test name
Test status
Simulation time 22928217105 ps
CPU time 1367.45 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 02:21:21 PM PST 24
Peak memory 273608 kb
Host smart-d75018c0-6ba3-4afe-9389-164548fba28a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954202038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3954202038
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.390258415
Short name T548
Test name
Test status
Simulation time 1438140730 ps
CPU time 9.23 seconds
Started Mar 05 01:58:36 PM PST 24
Finished Mar 05 01:58:45 PM PST 24
Peak memory 240728 kb
Host smart-29707f83-4645-4fba-bb08-edfd85fa98b8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=390258415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.390258415
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3548282989
Short name T592
Test name
Test status
Simulation time 4162581501 ps
CPU time 229.55 seconds
Started Mar 05 01:58:31 PM PST 24
Finished Mar 05 02:02:21 PM PST 24
Peak memory 257188 kb
Host smart-12579381-e0b3-49e1-9c22-b240bf03195d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35482
82989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3548282989
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.663585161
Short name T627
Test name
Test status
Simulation time 886117917 ps
CPU time 37.71 seconds
Started Mar 05 01:58:36 PM PST 24
Finished Mar 05 01:59:14 PM PST 24
Peak memory 254764 kb
Host smart-2fc3521a-ffbe-4c8e-8bbc-07c19aeec86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66358
5161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.663585161
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1184465527
Short name T581
Test name
Test status
Simulation time 22038445209 ps
CPU time 1372.2 seconds
Started Mar 05 01:58:32 PM PST 24
Finished Mar 05 02:21:24 PM PST 24
Peak memory 273576 kb
Host smart-12dc224f-d96a-402b-9cf3-93923f2bfbd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184465527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1184465527
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.703023593
Short name T629
Test name
Test status
Simulation time 28208005344 ps
CPU time 275.02 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 02:03:08 PM PST 24
Peak memory 247992 kb
Host smart-6cd61f45-58e7-4407-ab3e-2482bcbd64e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703023593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.703023593
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2932060745
Short name T668
Test name
Test status
Simulation time 4542036502 ps
CPU time 75.01 seconds
Started Mar 05 01:58:30 PM PST 24
Finished Mar 05 01:59:45 PM PST 24
Peak memory 255496 kb
Host smart-8600b7b6-afd3-43cd-9476-88595eab4aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29320
60745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2932060745
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2024261552
Short name T250
Test name
Test status
Simulation time 2427174711 ps
CPU time 18.05 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 01:58:52 PM PST 24
Peak memory 253692 kb
Host smart-8e2a970b-a07f-4c11-8e47-227e392f5178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20242
61552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2024261552
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1834186259
Short name T85
Test name
Test status
Simulation time 608546311 ps
CPU time 39.08 seconds
Started Mar 05 01:58:30 PM PST 24
Finished Mar 05 01:59:10 PM PST 24
Peak memory 248848 kb
Host smart-5e0c1599-2448-4f2c-a9d6-d808896ba68e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
86259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1834186259
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1851520040
Short name T198
Test name
Test status
Simulation time 6993343407 ps
CPU time 292.59 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 02:03:26 PM PST 24
Peak memory 254596 kb
Host smart-d425fdb3-247a-4ab2-a95c-ef6e77658023
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851520040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1851520040
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.199026492
Short name T243
Test name
Test status
Simulation time 30231146676 ps
CPU time 2136.2 seconds
Started Mar 05 01:58:32 PM PST 24
Finished Mar 05 02:34:08 PM PST 24
Peak memory 281712 kb
Host smart-920bf972-0259-43a7-be42-d602088acfc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199026492 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.199026492
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1509114658
Short name T225
Test name
Test status
Simulation time 108965847 ps
CPU time 3.1 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 01:58:45 PM PST 24
Peak memory 249148 kb
Host smart-36ca1220-9cb2-4938-9beb-9e27872a40fb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1509114658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1509114658
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2286923637
Short name T435
Test name
Test status
Simulation time 34892110174 ps
CPU time 1185.53 seconds
Started Mar 05 01:58:36 PM PST 24
Finished Mar 05 02:18:22 PM PST 24
Peak memory 265432 kb
Host smart-37bffd82-f7a5-472a-9222-b06d6ca01c3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286923637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2286923637
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2050641391
Short name T472
Test name
Test status
Simulation time 653214577 ps
CPU time 10.83 seconds
Started Mar 05 01:58:35 PM PST 24
Finished Mar 05 01:58:46 PM PST 24
Peak memory 240724 kb
Host smart-acced8b4-e9db-47a8-97ff-6528b38f9a3a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2050641391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2050641391
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3263684633
Short name T447
Test name
Test status
Simulation time 5304165059 ps
CPU time 291.99 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 02:03:26 PM PST 24
Peak memory 256688 kb
Host smart-4fcbaf68-35f2-4cba-a750-29b17c9ea2b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32636
84633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3263684633
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3987160473
Short name T541
Test name
Test status
Simulation time 874118352 ps
CPU time 49.08 seconds
Started Mar 05 01:58:32 PM PST 24
Finished Mar 05 01:59:21 PM PST 24
Peak memory 255144 kb
Host smart-bd387b9c-fd72-473a-9ada-a9e6ec85326a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39871
60473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3987160473
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2451148329
Short name T661
Test name
Test status
Simulation time 12799294137 ps
CPU time 1093.11 seconds
Started Mar 05 01:58:32 PM PST 24
Finished Mar 05 02:16:45 PM PST 24
Peak memory 283956 kb
Host smart-9fd17766-eaf1-45aa-b6b3-11994ac7d543
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451148329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2451148329
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.1479688830
Short name T595
Test name
Test status
Simulation time 10202553028 ps
CPU time 407.62 seconds
Started Mar 05 01:58:31 PM PST 24
Finished Mar 05 02:05:18 PM PST 24
Peak memory 247300 kb
Host smart-f719e8dc-7049-4813-b9d1-c7dcb5e1488e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479688830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.1479688830
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.286033790
Short name T238
Test name
Test status
Simulation time 364080561 ps
CPU time 23.19 seconds
Started Mar 05 01:58:31 PM PST 24
Finished Mar 05 01:58:54 PM PST 24
Peak memory 248892 kb
Host smart-cc6c012f-b800-4d83-a8b4-988d984fa4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
3790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.286033790
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2991939716
Short name T507
Test name
Test status
Simulation time 1896842448 ps
CPU time 29.31 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 01:59:03 PM PST 24
Peak memory 256596 kb
Host smart-eb3e8c89-b9be-4bf9-9f36-541ea13755fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29919
39716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2991939716
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2445904495
Short name T656
Test name
Test status
Simulation time 281935739 ps
CPU time 5.98 seconds
Started Mar 05 01:58:34 PM PST 24
Finished Mar 05 01:58:40 PM PST 24
Peak memory 248980 kb
Host smart-7ec79d7a-d25c-4fc0-90aa-3c17329862a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24459
04495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2445904495
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.1683542031
Short name T682
Test name
Test status
Simulation time 5688351425 ps
CPU time 607.11 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:08:49 PM PST 24
Peak memory 272220 kb
Host smart-2be58648-0554-4c11-8c01-915bab7805d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683542031 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.1683542031
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2945697198
Short name T91
Test name
Test status
Simulation time 44311283160 ps
CPU time 1387.31 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:21:48 PM PST 24
Peak memory 289840 kb
Host smart-51c01edb-7714-4592-aa5c-c60f6febfdd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945697198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2945697198
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.107499180
Short name T207
Test name
Test status
Simulation time 148514496 ps
CPU time 8.1 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 01:58:50 PM PST 24
Peak memory 240744 kb
Host smart-d9c70147-1d8e-4475-b614-5fc25084d54a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=107499180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.107499180
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1030739940
Short name T431
Test name
Test status
Simulation time 1572126705 ps
CPU time 146.49 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 02:01:09 PM PST 24
Peak memory 249136 kb
Host smart-13e4bf92-1ec7-4954-9438-92ab4905cb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10307
39940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1030739940
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2464949199
Short name T75
Test name
Test status
Simulation time 738836290 ps
CPU time 45.02 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:59:26 PM PST 24
Peak memory 254540 kb
Host smart-bd1ef9c1-2ef6-4c4d-8593-58fb794ba0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24649
49199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2464949199
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2768325978
Short name T660
Test name
Test status
Simulation time 37915215488 ps
CPU time 2177.96 seconds
Started Mar 05 01:58:44 PM PST 24
Finished Mar 05 02:35:02 PM PST 24
Peak memory 273288 kb
Host smart-da64c9ca-4006-4f18-8dc5-524077e11e83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768325978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2768325978
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2548244449
Short name T232
Test name
Test status
Simulation time 8226895665 ps
CPU time 811.23 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:12:12 PM PST 24
Peak memory 269536 kb
Host smart-eb5e3a79-15f1-4882-af0a-770529c444e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548244449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2548244449
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.3303484562
Short name T9
Test name
Test status
Simulation time 31146172245 ps
CPU time 342.85 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:04:24 PM PST 24
Peak memory 247924 kb
Host smart-4c2706ce-49d9-4ec7-8c61-e28f2f2eae72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303484562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.3303484562
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1465043888
Short name T94
Test name
Test status
Simulation time 1860139242 ps
CPU time 40 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 01:59:22 PM PST 24
Peak memory 248980 kb
Host smart-79f28c91-9c6b-44a3-a12d-e39f4ec95225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14650
43888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1465043888
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1180327572
Short name T490
Test name
Test status
Simulation time 920888158 ps
CPU time 51.6 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:59:33 PM PST 24
Peak memory 255288 kb
Host smart-05ebeef1-7376-4287-977c-642dfe20d7d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11803
27572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1180327572
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3191438234
Short name T680
Test name
Test status
Simulation time 2439579761 ps
CPU time 47.5 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:59:29 PM PST 24
Peak memory 255480 kb
Host smart-3307bfa3-c091-4017-b011-a8e6fde96d95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31914
38234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3191438234
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.2488578577
Short name T371
Test name
Test status
Simulation time 632449077 ps
CPU time 37.77 seconds
Started Mar 05 01:58:39 PM PST 24
Finished Mar 05 01:59:17 PM PST 24
Peak memory 248992 kb
Host smart-ba567c26-34d2-46b0-9502-26355bd51eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24885
78577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.2488578577
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1509986816
Short name T218
Test name
Test status
Simulation time 65725559 ps
CPU time 3.37 seconds
Started Mar 05 01:58:39 PM PST 24
Finished Mar 05 01:58:43 PM PST 24
Peak memory 249128 kb
Host smart-b18ed676-68c4-4ea1-96c2-3f78e135a0e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1509986816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1509986816
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3119031076
Short name T446
Test name
Test status
Simulation time 153885621876 ps
CPU time 2951.85 seconds
Started Mar 05 01:58:44 PM PST 24
Finished Mar 05 02:47:56 PM PST 24
Peak memory 283168 kb
Host smart-3ac022a6-a124-4ff8-be1b-c991e8929134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119031076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3119031076
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1138920138
Short name T637
Test name
Test status
Simulation time 285283635 ps
CPU time 10.18 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:58:51 PM PST 24
Peak memory 240796 kb
Host smart-ced1f5b0-db75-4f78-8849-3a098381609a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1138920138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1138920138
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3811402542
Short name T696
Test name
Test status
Simulation time 1476040964 ps
CPU time 116.9 seconds
Started Mar 05 01:58:47 PM PST 24
Finished Mar 05 02:00:44 PM PST 24
Peak memory 256172 kb
Host smart-c79fb484-2c7c-42ac-9612-9f3244bb68ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38114
02542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3811402542
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2436479852
Short name T79
Test name
Test status
Simulation time 1317020487 ps
CPU time 36.34 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 01:59:19 PM PST 24
Peak memory 255460 kb
Host smart-7f8b16d3-0720-4ee8-b102-3f0057a133c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24364
79852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2436479852
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1789508597
Short name T337
Test name
Test status
Simulation time 5784685264 ps
CPU time 521.32 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:07:23 PM PST 24
Peak memory 270652 kb
Host smart-06d1232a-695e-4ded-aa23-b2394df5d06c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789508597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1789508597
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.973467539
Short name T71
Test name
Test status
Simulation time 108471402820 ps
CPU time 1739.22 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:27:41 PM PST 24
Peak memory 272968 kb
Host smart-4f0cfd10-ab86-4686-9a3a-34a08e99e87f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973467539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.973467539
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.156134698
Short name T691
Test name
Test status
Simulation time 14406230385 ps
CPU time 576.78 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:08:18 PM PST 24
Peak memory 247728 kb
Host smart-533a935d-460c-4986-9c57-e706d4fac98e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156134698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.156134698
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1647022012
Short name T476
Test name
Test status
Simulation time 288099186 ps
CPU time 9.03 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:58:50 PM PST 24
Peak memory 253804 kb
Host smart-8894e7e7-1dac-4614-9b86-a815f4b987bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16470
22012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1647022012
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.989919654
Short name T543
Test name
Test status
Simulation time 846231718 ps
CPU time 54.98 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:59:36 PM PST 24
Peak memory 248384 kb
Host smart-0e017f4b-c040-4242-946f-551ce65e77a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98991
9654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.989919654
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1922001629
Short name T466
Test name
Test status
Simulation time 292484037 ps
CPU time 19.32 seconds
Started Mar 05 01:58:42 PM PST 24
Finished Mar 05 01:59:01 PM PST 24
Peak memory 255000 kb
Host smart-d03c9c6a-1dae-4332-a59c-7f28efa4a564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19220
01629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1922001629
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.805518050
Short name T83
Test name
Test status
Simulation time 476864052 ps
CPU time 27.06 seconds
Started Mar 05 01:58:40 PM PST 24
Finished Mar 05 01:59:08 PM PST 24
Peak memory 255940 kb
Host smart-995feb67-cedd-4715-b414-5580c2b4c74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80551
8050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.805518050
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.4248009914
Short name T449
Test name
Test status
Simulation time 206760296924 ps
CPU time 1166.6 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 02:18:08 PM PST 24
Peak memory 284724 kb
Host smart-069fd6e5-31b4-42fc-9ff2-1e5d6acdc7b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248009914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.4248009914
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1563354656
Short name T219
Test name
Test status
Simulation time 57292584 ps
CPU time 2.28 seconds
Started Mar 05 01:58:47 PM PST 24
Finished Mar 05 01:58:50 PM PST 24
Peak memory 249208 kb
Host smart-04ced4a9-042a-4c17-8d81-6cc187c56765
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1563354656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1563354656
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.693904864
Short name T104
Test name
Test status
Simulation time 43189245941 ps
CPU time 2443.86 seconds
Started Mar 05 01:58:45 PM PST 24
Finished Mar 05 02:39:30 PM PST 24
Peak memory 282824 kb
Host smart-3243eec7-5168-4014-a5b3-274d62a9478d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693904864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.693904864
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4123371397
Short name T502
Test name
Test status
Simulation time 1119572691 ps
CPU time 12.01 seconds
Started Mar 05 01:58:48 PM PST 24
Finished Mar 05 01:59:00 PM PST 24
Peak memory 240724 kb
Host smart-8a4bcfa5-ee48-415a-984f-c70856f4fa26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4123371397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4123371397
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3453524076
Short name T382
Test name
Test status
Simulation time 16178437135 ps
CPU time 190.84 seconds
Started Mar 05 01:58:48 PM PST 24
Finished Mar 05 02:01:58 PM PST 24
Peak memory 256128 kb
Host smart-78730469-fd20-4615-8006-5ad0b69fb7c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
24076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3453524076
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1553717097
Short name T444
Test name
Test status
Simulation time 343866585 ps
CPU time 33.49 seconds
Started Mar 05 01:58:40 PM PST 24
Finished Mar 05 01:59:14 PM PST 24
Peak memory 254716 kb
Host smart-53a273cf-45ab-42f0-aca3-17fcd1896b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15537
17097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1553717097
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3784369667
Short name T338
Test name
Test status
Simulation time 80257513285 ps
CPU time 1292.37 seconds
Started Mar 05 01:58:50 PM PST 24
Finished Mar 05 02:20:23 PM PST 24
Peak memory 273052 kb
Host smart-532e4afc-7a8f-4c58-be17-fe885f6a8731
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784369667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3784369667
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.208226528
Short name T384
Test name
Test status
Simulation time 43007868440 ps
CPU time 1177.5 seconds
Started Mar 05 01:58:50 PM PST 24
Finished Mar 05 02:18:28 PM PST 24
Peak memory 289816 kb
Host smart-18a8ae9b-9507-4083-911b-1b623d53abea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208226528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.208226528
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3342624523
Short name T323
Test name
Test status
Simulation time 9343340672 ps
CPU time 382.62 seconds
Started Mar 05 01:58:49 PM PST 24
Finished Mar 05 02:05:12 PM PST 24
Peak memory 246700 kb
Host smart-3183f7f2-8543-4aee-848a-228453ff1391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342624523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3342624523
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1613379747
Short name T69
Test name
Test status
Simulation time 16045700130 ps
CPU time 46.18 seconds
Started Mar 05 01:58:39 PM PST 24
Finished Mar 05 01:59:26 PM PST 24
Peak memory 249036 kb
Host smart-d7816225-45f3-44d2-9308-71c49492a0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16133
79747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1613379747
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1709380419
Short name T95
Test name
Test status
Simulation time 611780374 ps
CPU time 19.02 seconds
Started Mar 05 01:58:39 PM PST 24
Finished Mar 05 01:58:58 PM PST 24
Peak memory 255460 kb
Host smart-4952692f-375c-4a26-a87d-a7891c49e28c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
80419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1709380419
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.3621160042
Short name T528
Test name
Test status
Simulation time 324714863 ps
CPU time 10.65 seconds
Started Mar 05 01:58:49 PM PST 24
Finished Mar 05 01:59:00 PM PST 24
Peak memory 253796 kb
Host smart-6ba3e588-b4b1-4ebf-9192-f3bd50c2404f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36211
60042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.3621160042
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3415707716
Short name T5
Test name
Test status
Simulation time 306179659 ps
CPU time 17.86 seconds
Started Mar 05 01:58:41 PM PST 24
Finished Mar 05 01:58:59 PM PST 24
Peak memory 248988 kb
Host smart-9920873c-6b46-4585-a1b6-489e1534198b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34157
07716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3415707716
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.473013127
Short name T621
Test name
Test status
Simulation time 1576878958 ps
CPU time 164.49 seconds
Started Mar 05 01:58:50 PM PST 24
Finished Mar 05 02:01:35 PM PST 24
Peak memory 251728 kb
Host smart-ee4856b2-de87-4a2d-9da8-f41fce815a5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473013127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.473013127
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1843849886
Short name T221
Test name
Test status
Simulation time 127791503 ps
CPU time 2.96 seconds
Started Mar 05 01:58:58 PM PST 24
Finished Mar 05 01:59:02 PM PST 24
Peak memory 249152 kb
Host smart-f413a242-790d-4f78-8f5f-edb063ef17a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1843849886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1843849886
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1795412837
Short name T408
Test name
Test status
Simulation time 6765205877 ps
CPU time 646.95 seconds
Started Mar 05 01:58:47 PM PST 24
Finished Mar 05 02:09:34 PM PST 24
Peak memory 273544 kb
Host smart-4e6b2bae-3da5-40a7-b6b4-eb08d90d44ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795412837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1795412837
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2993128005
Short name T462
Test name
Test status
Simulation time 1091995454 ps
CPU time 44.19 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 01:59:42 PM PST 24
Peak memory 240768 kb
Host smart-82f7aba6-5e15-4a67-a46f-6e3fea50e804
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2993128005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2993128005
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3790536123
Short name T44
Test name
Test status
Simulation time 7937768200 ps
CPU time 290.51 seconds
Started Mar 05 01:58:48 PM PST 24
Finished Mar 05 02:03:38 PM PST 24
Peak memory 256664 kb
Host smart-1a9b595d-41e7-47fb-97bd-d2aefbcf9657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
36123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3790536123
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4090561224
Short name T704
Test name
Test status
Simulation time 924463761 ps
CPU time 20.19 seconds
Started Mar 05 01:58:47 PM PST 24
Finished Mar 05 01:59:07 PM PST 24
Peak memory 255272 kb
Host smart-1512689b-d088-4c8d-bc1e-f07ee27f76d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40905
61224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4090561224
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3300254822
Short name T332
Test name
Test status
Simulation time 18083439007 ps
CPU time 1448.51 seconds
Started Mar 05 01:58:49 PM PST 24
Finished Mar 05 02:22:58 PM PST 24
Peak memory 289692 kb
Host smart-66108f27-0be3-4ed2-8846-055d9252769d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300254822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3300254822
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2218328211
Short name T413
Test name
Test status
Simulation time 32162639252 ps
CPU time 1323.27 seconds
Started Mar 05 01:58:57 PM PST 24
Finished Mar 05 02:21:01 PM PST 24
Peak memory 289788 kb
Host smart-1b8dc11c-7440-4e30-afce-3f34e448d750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218328211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2218328211
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.752980023
Short name T670
Test name
Test status
Simulation time 2029875435 ps
CPU time 91.44 seconds
Started Mar 05 01:58:51 PM PST 24
Finished Mar 05 02:00:23 PM PST 24
Peak memory 246844 kb
Host smart-bf07683a-dfa8-4a72-80a9-f73a60755cd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752980023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.752980023
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.707333379
Short name T491
Test name
Test status
Simulation time 1492686497 ps
CPU time 27.74 seconds
Started Mar 05 01:58:49 PM PST 24
Finished Mar 05 01:59:17 PM PST 24
Peak memory 257160 kb
Host smart-935e6863-0c7f-45fb-a7fb-c938b9b62244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70733
3379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.707333379
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.4127235714
Short name T505
Test name
Test status
Simulation time 1023996313 ps
CPU time 21.84 seconds
Started Mar 05 01:58:50 PM PST 24
Finished Mar 05 01:59:12 PM PST 24
Peak memory 247520 kb
Host smart-9db080db-8a88-4bd9-937e-e287d34ea57c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41272
35714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.4127235714
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1748193158
Short name T603
Test name
Test status
Simulation time 245010933 ps
CPU time 4.8 seconds
Started Mar 05 01:58:51 PM PST 24
Finished Mar 05 01:58:56 PM PST 24
Peak memory 239052 kb
Host smart-bfb09b35-8af0-413a-939b-6fd9d3339f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17481
93158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1748193158
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1569953780
Short name T426
Test name
Test status
Simulation time 334417069 ps
CPU time 6.75 seconds
Started Mar 05 01:58:46 PM PST 24
Finished Mar 05 01:58:53 PM PST 24
Peak memory 250264 kb
Host smart-1725a0ec-f462-4bd7-b986-0a5fbd7af318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15699
53780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1569953780
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3297153698
Short name T97
Test name
Test status
Simulation time 102777244532 ps
CPU time 5014.29 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 03:22:32 PM PST 24
Peak memory 332504 kb
Host smart-72a4ea26-d1f9-437b-866e-9e032225e199
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297153698 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3297153698
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1843654969
Short name T224
Test name
Test status
Simulation time 141694468 ps
CPU time 3.79 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 01:59:01 PM PST 24
Peak memory 249156 kb
Host smart-a3d03b36-a532-4cc0-829f-a4ce677e28b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1843654969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1843654969
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2144160120
Short name T662
Test name
Test status
Simulation time 20490678760 ps
CPU time 746.63 seconds
Started Mar 05 01:58:58 PM PST 24
Finished Mar 05 02:11:25 PM PST 24
Peak memory 273416 kb
Host smart-946c993e-9f0c-483a-a131-6e215792085f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144160120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2144160120
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3777477651
Short name T372
Test name
Test status
Simulation time 1650927390 ps
CPU time 68.38 seconds
Started Mar 05 01:59:00 PM PST 24
Finished Mar 05 02:00:08 PM PST 24
Peak memory 248936 kb
Host smart-15beb847-55d5-42b8-b022-c425b5aa091f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3777477651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3777477651
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2422783449
Short name T602
Test name
Test status
Simulation time 6997800133 ps
CPU time 215.92 seconds
Started Mar 05 01:59:00 PM PST 24
Finished Mar 05 02:02:36 PM PST 24
Peak memory 257192 kb
Host smart-e2900a38-9d3d-4fd3-8d7f-95c457be9410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24227
83449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2422783449
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2087868522
Short name T588
Test name
Test status
Simulation time 84035618 ps
CPU time 9.6 seconds
Started Mar 05 01:58:54 PM PST 24
Finished Mar 05 01:59:05 PM PST 24
Peak memory 256156 kb
Host smart-36451d6b-a521-423c-8b4f-ec0fa51f903e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20878
68522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2087868522
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2281449498
Short name T340
Test name
Test status
Simulation time 32007445466 ps
CPU time 852.56 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 02:13:10 PM PST 24
Peak memory 272916 kb
Host smart-99ff07a3-7a12-4303-8bb6-458904afafea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281449498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2281449498
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3130530351
Short name T659
Test name
Test status
Simulation time 133581673844 ps
CPU time 972.8 seconds
Started Mar 05 01:58:59 PM PST 24
Finished Mar 05 02:15:12 PM PST 24
Peak memory 282940 kb
Host smart-20d39531-7cc5-4167-ba58-e7994bfd7a22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130530351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3130530351
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1952031353
Short name T441
Test name
Test status
Simulation time 131162026386 ps
CPU time 416.99 seconds
Started Mar 05 01:58:55 PM PST 24
Finished Mar 05 02:05:53 PM PST 24
Peak memory 247672 kb
Host smart-c93be655-5fd4-450d-afd9-1794e96fdd22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952031353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1952031353
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1800926522
Short name T42
Test name
Test status
Simulation time 438094083 ps
CPU time 31.67 seconds
Started Mar 05 01:58:55 PM PST 24
Finished Mar 05 01:59:27 PM PST 24
Peak memory 249056 kb
Host smart-60b748be-b9ee-4f3e-ad02-dc9b42ea33e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18009
26522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1800926522
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3737746642
Short name T48
Test name
Test status
Simulation time 77795653 ps
CPU time 9.51 seconds
Started Mar 05 01:58:54 PM PST 24
Finished Mar 05 01:59:05 PM PST 24
Peak memory 253268 kb
Host smart-8d4c9fa1-1b69-4519-9aea-c652fd46bc85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37377
46642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3737746642
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3508644812
Short name T540
Test name
Test status
Simulation time 551871546 ps
CPU time 34.17 seconds
Started Mar 05 01:58:54 PM PST 24
Finished Mar 05 01:59:29 PM PST 24
Peak memory 248952 kb
Host smart-3b2b8fbf-08bf-4f4a-a275-61c6e5dc309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35086
44812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3508644812
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3467805122
Short name T711
Test name
Test status
Simulation time 65589864 ps
CPU time 5.42 seconds
Started Mar 05 01:58:57 PM PST 24
Finished Mar 05 01:59:04 PM PST 24
Peak memory 240796 kb
Host smart-200820a7-6a63-4252-9a9f-7eb8e1e60a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34678
05122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3467805122
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.3690754534
Short name T457
Test name
Test status
Simulation time 67273888048 ps
CPU time 1686.06 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 02:27:04 PM PST 24
Peak memory 289572 kb
Host smart-f51c3ca3-26b4-48a3-bad0-3d6711351082
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690754534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.3690754534
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1504093936
Short name T227
Test name
Test status
Simulation time 44154750 ps
CPU time 4.19 seconds
Started Mar 05 01:59:07 PM PST 24
Finished Mar 05 01:59:11 PM PST 24
Peak memory 249140 kb
Host smart-29a11b87-08c9-47fa-a0de-89c61f3238aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1504093936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1504093936
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2909633017
Short name T495
Test name
Test status
Simulation time 42544869602 ps
CPU time 2574.21 seconds
Started Mar 05 01:59:08 PM PST 24
Finished Mar 05 02:42:03 PM PST 24
Peak memory 286252 kb
Host smart-edd3dcc7-54ee-4bc4-a291-927edfa1ff91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909633017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2909633017
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.889879878
Short name T208
Test name
Test status
Simulation time 137271873 ps
CPU time 7.94 seconds
Started Mar 05 01:59:06 PM PST 24
Finished Mar 05 01:59:14 PM PST 24
Peak memory 240772 kb
Host smart-0542abd2-3119-4a19-86da-7d18f9ec4b48
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=889879878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.889879878
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.206368180
Short name T365
Test name
Test status
Simulation time 30790018798 ps
CPU time 306.77 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:04:12 PM PST 24
Peak memory 256452 kb
Host smart-b7be2a78-ba31-4795-b9ea-10ad7fa109d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20636
8180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.206368180
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.773903456
Short name T606
Test name
Test status
Simulation time 1766017617 ps
CPU time 59.14 seconds
Started Mar 05 01:58:56 PM PST 24
Finished Mar 05 01:59:56 PM PST 24
Peak memory 256488 kb
Host smart-cef66717-6227-4f38-8f38-68b9e34753d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77390
3456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.773903456
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3859546099
Short name T329
Test name
Test status
Simulation time 18087388106 ps
CPU time 1743.97 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:28:09 PM PST 24
Peak memory 289680 kb
Host smart-bb6cae4b-ee76-4603-9f85-6e6d093cb2cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859546099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3859546099
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.878055966
Short name T440
Test name
Test status
Simulation time 84554163586 ps
CPU time 1427.08 seconds
Started Mar 05 01:59:07 PM PST 24
Finished Mar 05 02:22:54 PM PST 24
Peak memory 273040 kb
Host smart-b21fe0b7-4e61-4a6c-b69f-d524a9313d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878055966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.878055966
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2249534799
Short name T308
Test name
Test status
Simulation time 3783362029 ps
CPU time 165.67 seconds
Started Mar 05 01:59:06 PM PST 24
Finished Mar 05 02:01:51 PM PST 24
Peak memory 247876 kb
Host smart-87f4a3c0-70b2-4621-badb-778720f6bec5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249534799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2249534799
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3331123139
Short name T578
Test name
Test status
Simulation time 550292538 ps
CPU time 43.85 seconds
Started Mar 05 01:58:55 PM PST 24
Finished Mar 05 01:59:40 PM PST 24
Peak memory 255932 kb
Host smart-705daecd-e26f-46bc-b345-f5c794cb6b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
23139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3331123139
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2907212692
Short name T471
Test name
Test status
Simulation time 434100653 ps
CPU time 8.37 seconds
Started Mar 05 01:59:00 PM PST 24
Finished Mar 05 01:59:08 PM PST 24
Peak memory 247084 kb
Host smart-dda14b67-08a8-41ed-9faf-ecbc095e3b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29072
12692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2907212692
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1783811739
Short name T34
Test name
Test status
Simulation time 1181385266 ps
CPU time 39.77 seconds
Started Mar 05 01:59:07 PM PST 24
Finished Mar 05 01:59:46 PM PST 24
Peak memory 248980 kb
Host smart-c155bac9-355b-4e51-b4f8-acf7d5e98d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17838
11739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1783811739
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3542374840
Short name T455
Test name
Test status
Simulation time 2733099226 ps
CPU time 28.9 seconds
Started Mar 05 01:59:00 PM PST 24
Finished Mar 05 01:59:29 PM PST 24
Peak memory 249032 kb
Host smart-d5718179-f7f7-4ce9-89ff-ddb3d713adbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35423
74840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3542374840
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3374286548
Short name T220
Test name
Test status
Simulation time 46165421 ps
CPU time 3.59 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 01:59:18 PM PST 24
Peak memory 249160 kb
Host smart-e61353e5-930a-49e0-bd7f-237d0762f13f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3374286548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3374286548
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2493362870
Short name T474
Test name
Test status
Simulation time 30379575030 ps
CPU time 2034.13 seconds
Started Mar 05 01:59:07 PM PST 24
Finished Mar 05 02:33:02 PM PST 24
Peak memory 282692 kb
Host smart-e711a429-f31b-4fe9-9844-57faac315520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493362870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2493362870
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2481194303
Short name T438
Test name
Test status
Simulation time 307868771 ps
CPU time 9.53 seconds
Started Mar 05 01:59:13 PM PST 24
Finished Mar 05 01:59:23 PM PST 24
Peak memory 240744 kb
Host smart-f7166951-f1bc-4413-b420-1e6cc0e6acb0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2481194303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2481194303
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.310494347
Short name T532
Test name
Test status
Simulation time 7719059868 ps
CPU time 173.17 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:01:58 PM PST 24
Peak memory 256376 kb
Host smart-cbae41f3-6c99-4750-a99d-11b5192a1544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
4347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.310494347
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.4127755152
Short name T692
Test name
Test status
Simulation time 315004652 ps
CPU time 4.78 seconds
Started Mar 05 01:59:06 PM PST 24
Finished Mar 05 01:59:10 PM PST 24
Peak memory 238924 kb
Host smart-8ef18820-e507-4ec9-bc9c-e3ce78828730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41277
55152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.4127755152
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1424529933
Short name T653
Test name
Test status
Simulation time 17579016806 ps
CPU time 1210.2 seconds
Started Mar 05 01:59:06 PM PST 24
Finished Mar 05 02:19:16 PM PST 24
Peak memory 265448 kb
Host smart-df45626f-bf56-4c0c-bfa1-b58a5d197610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424529933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1424529933
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.4261792948
Short name T315
Test name
Test status
Simulation time 54015469280 ps
CPU time 555.12 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:08:20 PM PST 24
Peak memory 247836 kb
Host smart-d0057901-1d04-4ae9-a38a-0f61a8af1a8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261792948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.4261792948
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2458761663
Short name T358
Test name
Test status
Simulation time 2327240556 ps
CPU time 36.45 seconds
Started Mar 05 01:59:08 PM PST 24
Finished Mar 05 01:59:45 PM PST 24
Peak memory 249020 kb
Host smart-5cca897d-f5cb-4bff-8730-effdc92fde2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
61663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2458761663
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2468223432
Short name T410
Test name
Test status
Simulation time 764120704 ps
CPU time 13.23 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 01:59:19 PM PST 24
Peak memory 251592 kb
Host smart-6619345b-bf32-41f1-bcb9-bb5cb7372087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24682
23432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2468223432
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1310976812
Short name T701
Test name
Test status
Simulation time 603386163 ps
CPU time 40.22 seconds
Started Mar 05 01:59:07 PM PST 24
Finished Mar 05 01:59:47 PM PST 24
Peak memory 255044 kb
Host smart-5476c065-30fe-408a-90bb-f79ddb0db670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13109
76812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1310976812
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2408151677
Short name T43
Test name
Test status
Simulation time 1881279874 ps
CPU time 67.66 seconds
Started Mar 05 01:59:05 PM PST 24
Finished Mar 05 02:00:13 PM PST 24
Peak memory 248980 kb
Host smart-30eecee0-819d-4862-8f4b-e27190c00483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24081
51677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2408151677
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2789364745
Short name T373
Test name
Test status
Simulation time 5809127668 ps
CPU time 141.18 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 02:01:36 PM PST 24
Peak memory 257212 kb
Host smart-d417174e-bee4-48e9-915d-f17576082ff2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789364745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2789364745
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2947953324
Short name T228
Test name
Test status
Simulation time 35751033 ps
CPU time 3.48 seconds
Started Mar 05 01:57:45 PM PST 24
Finished Mar 05 01:57:49 PM PST 24
Peak memory 249148 kb
Host smart-2c133395-145c-4a55-96a9-b52749e537d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2947953324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2947953324
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3014117554
Short name T195
Test name
Test status
Simulation time 31826349165 ps
CPU time 1022.56 seconds
Started Mar 05 01:57:46 PM PST 24
Finished Mar 05 02:14:49 PM PST 24
Peak memory 273400 kb
Host smart-ea9a8e05-88dc-4a61-8f00-7c87b19815b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014117554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3014117554
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.31190303
Short name T436
Test name
Test status
Simulation time 262134243 ps
CPU time 14.68 seconds
Started Mar 05 01:57:47 PM PST 24
Finished Mar 05 01:58:02 PM PST 24
Peak memory 248960 kb
Host smart-f0a29ecf-48ba-45a3-be94-8b6b35624cc5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=31190303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.31190303
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.3501149388
Short name T553
Test name
Test status
Simulation time 4787006318 ps
CPU time 82.41 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:59:11 PM PST 24
Peak memory 256344 kb
Host smart-d347b7f6-d280-4982-aa92-f3032bab2a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35011
49388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.3501149388
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3812009863
Short name T236
Test name
Test status
Simulation time 944071939 ps
CPU time 17.33 seconds
Started Mar 05 01:57:46 PM PST 24
Finished Mar 05 01:58:04 PM PST 24
Peak memory 254736 kb
Host smart-059bb9ab-5683-4b9c-93ea-e7bd8ec570d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38120
09863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3812009863
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2420033379
Short name T442
Test name
Test status
Simulation time 48640708997 ps
CPU time 1011.79 seconds
Started Mar 05 01:57:45 PM PST 24
Finished Mar 05 02:14:37 PM PST 24
Peak memory 273172 kb
Host smart-fddb3342-5a6b-4841-918d-87952629c90b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420033379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2420033379
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.973552720
Short name T109
Test name
Test status
Simulation time 73665437994 ps
CPU time 2415.08 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 02:38:03 PM PST 24
Peak memory 281848 kb
Host smart-d571b9a4-e538-4052-9a5c-85c88c083a95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973552720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.973552720
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.4039096903
Short name T300
Test name
Test status
Simulation time 54795262182 ps
CPU time 580.69 seconds
Started Mar 05 01:57:45 PM PST 24
Finished Mar 05 02:07:26 PM PST 24
Peak memory 247860 kb
Host smart-245113b3-f0be-4d5a-9b83-3559db5d29f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039096903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.4039096903
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.4049564483
Short name T437
Test name
Test status
Simulation time 471369888 ps
CPU time 10.44 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:57:59 PM PST 24
Peak memory 248992 kb
Host smart-79e338bf-f450-4976-be52-98ac42be8dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40495
64483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.4049564483
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.313436597
Short name T404
Test name
Test status
Simulation time 85193268 ps
CPU time 7.18 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:57:56 PM PST 24
Peak memory 252788 kb
Host smart-d9fa6420-ebd5-4d8f-aabf-b3ab1a1ebcf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31343
6597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.313436597
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3448176408
Short name T32
Test name
Test status
Simulation time 797083265 ps
CPU time 12.48 seconds
Started Mar 05 01:57:47 PM PST 24
Finished Mar 05 01:58:00 PM PST 24
Peak memory 269632 kb
Host smart-68b67911-8ac5-43a0-917b-7519bffc91f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3448176408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3448176408
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3449846655
Short name T61
Test name
Test status
Simulation time 540170700 ps
CPU time 41.06 seconds
Started Mar 05 01:57:46 PM PST 24
Finished Mar 05 01:58:28 PM PST 24
Peak memory 255728 kb
Host smart-67e14b86-e1f7-4d4c-950c-3f512e8bd72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34498
46655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3449846655
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.4165766487
Short name T416
Test name
Test status
Simulation time 623852927 ps
CPU time 45.9 seconds
Started Mar 05 01:57:47 PM PST 24
Finished Mar 05 01:58:33 PM PST 24
Peak memory 255744 kb
Host smart-8e6cbf8b-fe3c-4914-89b6-844aa8660249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41657
66487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.4165766487
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3089155067
Short name T252
Test name
Test status
Simulation time 2930448293 ps
CPU time 159.05 seconds
Started Mar 05 01:57:52 PM PST 24
Finished Mar 05 02:00:32 PM PST 24
Peak memory 257236 kb
Host smart-fd356aaa-66e3-456b-8a64-abd59a2f08b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089155067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3089155067
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2359440792
Short name T15
Test name
Test status
Simulation time 32429762487 ps
CPU time 719.32 seconds
Started Mar 05 01:59:16 PM PST 24
Finished Mar 05 02:11:15 PM PST 24
Peak memory 265396 kb
Host smart-d35988c9-9c1a-42da-b37a-3cf9632879b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359440792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2359440792
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3110099249
Short name T686
Test name
Test status
Simulation time 4080936625 ps
CPU time 44.18 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 02:00:00 PM PST 24
Peak memory 249000 kb
Host smart-f9875efd-2024-4157-80a7-51630bf29dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31100
99249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3110099249
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2673150639
Short name T412
Test name
Test status
Simulation time 5220185914 ps
CPU time 35.03 seconds
Started Mar 05 01:59:14 PM PST 24
Finished Mar 05 01:59:49 PM PST 24
Peak memory 254956 kb
Host smart-3069afb5-7d5c-429e-90f7-d383099dc0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26731
50639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2673150639
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.638410299
Short name T573
Test name
Test status
Simulation time 27260979015 ps
CPU time 1544.03 seconds
Started Mar 05 01:59:12 PM PST 24
Finished Mar 05 02:24:56 PM PST 24
Peak memory 265464 kb
Host smart-da59aa1d-08cd-45d1-a97a-b2b4962665bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638410299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.638410299
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3483890828
Short name T90
Test name
Test status
Simulation time 22954548504 ps
CPU time 1457.45 seconds
Started Mar 05 01:59:12 PM PST 24
Finished Mar 05 02:23:29 PM PST 24
Peak memory 272540 kb
Host smart-ff02c0de-b086-4c12-bee8-daadd1502c44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483890828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3483890828
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3637538486
Short name T303
Test name
Test status
Simulation time 25473350194 ps
CPU time 268.7 seconds
Started Mar 05 01:59:13 PM PST 24
Finished Mar 05 02:03:42 PM PST 24
Peak memory 247644 kb
Host smart-5e4c68de-a661-4366-822a-1fe04f4c2bd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637538486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3637538486
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3948832116
Short name T388
Test name
Test status
Simulation time 866790430 ps
CPU time 11.12 seconds
Started Mar 05 01:59:13 PM PST 24
Finished Mar 05 01:59:24 PM PST 24
Peak memory 253972 kb
Host smart-dd6ecaae-40a0-4714-88bb-ccff5ce552cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39488
32116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3948832116
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.843719314
Short name T237
Test name
Test status
Simulation time 2115876793 ps
CPU time 26.45 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 01:59:42 PM PST 24
Peak memory 255636 kb
Host smart-b14962ba-1cfd-4ee8-95fa-b61ff7143d0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84371
9314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.843719314
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1433555379
Short name T399
Test name
Test status
Simulation time 1211722825 ps
CPU time 43 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 01:59:58 PM PST 24
Peak memory 247244 kb
Host smart-19b79865-25b8-4838-b4ef-ef663e766779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14335
55379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1433555379
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1005841554
Short name T74
Test name
Test status
Simulation time 1010281358 ps
CPU time 28.93 seconds
Started Mar 05 01:59:14 PM PST 24
Finished Mar 05 01:59:44 PM PST 24
Peak memory 249080 kb
Host smart-e4dfd02c-86c6-4434-ad22-415b3c6159b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
41554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1005841554
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3301788971
Short name T204
Test name
Test status
Simulation time 31947436333 ps
CPU time 1619.3 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 02:26:14 PM PST 24
Peak memory 305664 kb
Host smart-7ffe063a-cec8-42c5-b447-ef6d7d2d3b42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301788971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3301788971
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.807509760
Short name T45
Test name
Test status
Simulation time 40590696289 ps
CPU time 2296.63 seconds
Started Mar 05 01:59:14 PM PST 24
Finished Mar 05 02:37:31 PM PST 24
Peak memory 288128 kb
Host smart-607a6c17-cbee-4c83-865b-2fc48688a5f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807509760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.807509760
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4280979148
Short name T368
Test name
Test status
Simulation time 4787650848 ps
CPU time 157.16 seconds
Started Mar 05 01:59:13 PM PST 24
Finished Mar 05 02:01:50 PM PST 24
Peak memory 257236 kb
Host smart-8adb677c-d139-4107-b544-f177f0c47141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42809
79148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4280979148
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1409446264
Short name T473
Test name
Test status
Simulation time 1006714977 ps
CPU time 63.35 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 02:00:19 PM PST 24
Peak memory 255604 kb
Host smart-fc3caf06-5ad7-4a55-84c6-56f401dc3f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14094
46264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1409446264
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.648115475
Short name T68
Test name
Test status
Simulation time 104921976444 ps
CPU time 1632.72 seconds
Started Mar 05 01:59:19 PM PST 24
Finished Mar 05 02:26:32 PM PST 24
Peak memory 289492 kb
Host smart-1be71fca-9e93-46ed-929d-5452cb296afe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648115475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.648115475
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.36875411
Short name T185
Test name
Test status
Simulation time 347581656 ps
CPU time 34.91 seconds
Started Mar 05 01:59:11 PM PST 24
Finished Mar 05 01:59:46 PM PST 24
Peak memory 248976 kb
Host smart-85af6c38-1df0-4a1c-9ec7-4faba8dcd6de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36875
411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.36875411
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3859711938
Short name T288
Test name
Test status
Simulation time 386571570 ps
CPU time 34.69 seconds
Started Mar 05 01:59:13 PM PST 24
Finished Mar 05 01:59:48 PM PST 24
Peak memory 254624 kb
Host smart-5a953501-b515-475e-ac2d-11b142c68457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38597
11938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3859711938
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2235725028
Short name T50
Test name
Test status
Simulation time 358138780 ps
CPU time 25.11 seconds
Started Mar 05 01:59:15 PM PST 24
Finished Mar 05 01:59:41 PM PST 24
Peak memory 255536 kb
Host smart-2bd34b22-5f4f-47c1-8ac3-9b2af1b25eb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22357
25028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2235725028
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.164867632
Short name T673
Test name
Test status
Simulation time 600697875 ps
CPU time 9.86 seconds
Started Mar 05 01:59:14 PM PST 24
Finished Mar 05 01:59:24 PM PST 24
Peak memory 249016 kb
Host smart-89c3aefe-4666-45eb-a27f-1fb1edcf80f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16486
7632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.164867632
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.998508919
Short name T486
Test name
Test status
Simulation time 104510692399 ps
CPU time 2294.01 seconds
Started Mar 05 01:59:21 PM PST 24
Finished Mar 05 02:37:36 PM PST 24
Peak memory 287400 kb
Host smart-59d5ace9-7074-4573-9d26-48508593cad2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998508919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.998508919
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.2319802899
Short name T468
Test name
Test status
Simulation time 185172178014 ps
CPU time 1605.01 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 02:26:06 PM PST 24
Peak memory 289984 kb
Host smart-d4c42341-ad64-4a1d-9df8-7f093390644e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319802899 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.2319802899
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3396704480
Short name T488
Test name
Test status
Simulation time 75833804345 ps
CPU time 1142.26 seconds
Started Mar 05 01:59:19 PM PST 24
Finished Mar 05 02:18:22 PM PST 24
Peak memory 289676 kb
Host smart-167eab17-1a29-4eb4-80b3-13bf1194e075
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396704480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3396704480
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2023233772
Short name T370
Test name
Test status
Simulation time 2328709232 ps
CPU time 135.15 seconds
Started Mar 05 01:59:17 PM PST 24
Finished Mar 05 02:01:33 PM PST 24
Peak memory 256704 kb
Host smart-a58f6482-a038-4273-85dc-dd16f4dae731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20232
33772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2023233772
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4276928980
Short name T612
Test name
Test status
Simulation time 707028646 ps
CPU time 24.86 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 01:59:43 PM PST 24
Peak memory 255424 kb
Host smart-c247e838-3927-4ca9-87a4-3e866a2a83aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
28980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4276928980
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.4181146981
Short name T294
Test name
Test status
Simulation time 9226913032 ps
CPU time 928.14 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 02:14:47 PM PST 24
Peak memory 272768 kb
Host smart-f32d4bbd-c0af-4950-bbc1-7eaa3430cac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181146981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.4181146981
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1933219371
Short name T464
Test name
Test status
Simulation time 8297045397 ps
CPU time 750.43 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 02:11:49 PM PST 24
Peak memory 265444 kb
Host smart-37607b44-3d63-4d93-81b5-b5306f7f8572
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933219371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1933219371
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.157378697
Short name T470
Test name
Test status
Simulation time 351695793 ps
CPU time 27.26 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 01:59:48 PM PST 24
Peak memory 248972 kb
Host smart-2b22f651-8f47-4d05-8478-3eb34052cad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15737
8697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.157378697
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1952584033
Short name T17
Test name
Test status
Simulation time 502061948 ps
CPU time 31.39 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 01:59:50 PM PST 24
Peak memory 247344 kb
Host smart-ca945989-47e7-45ed-931c-0b817786cc8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19525
84033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1952584033
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3633567316
Short name T267
Test name
Test status
Simulation time 578223843 ps
CPU time 18.07 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 01:59:38 PM PST 24
Peak memory 248976 kb
Host smart-3f8deade-045b-4344-9289-f3c0585edbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36335
67316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3633567316
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3431630658
Short name T78
Test name
Test status
Simulation time 9579906508 ps
CPU time 146.95 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 02:01:45 PM PST 24
Peak memory 252480 kb
Host smart-c3e2a1e6-bca1-4dc0-b78b-b21775ffd231
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431630658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3431630658
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1101350083
Short name T197
Test name
Test status
Simulation time 18411342759 ps
CPU time 1993.19 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 02:32:33 PM PST 24
Peak memory 305276 kb
Host smart-5f5ad8cb-f9de-4c6e-be98-3184e60fbba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101350083 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1101350083
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2742862808
Short name T479
Test name
Test status
Simulation time 73751068020 ps
CPU time 1706.98 seconds
Started Mar 05 01:59:26 PM PST 24
Finished Mar 05 02:27:54 PM PST 24
Peak memory 289324 kb
Host smart-7f255b4c-5583-47df-88de-cfe180ebb729
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742862808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2742862808
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.935185880
Short name T589
Test name
Test status
Simulation time 12185363365 ps
CPU time 179.85 seconds
Started Mar 05 01:59:19 PM PST 24
Finished Mar 05 02:02:19 PM PST 24
Peak memory 256704 kb
Host smart-ef861d9d-17aa-453a-825c-0c58146f754d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93518
5880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.935185880
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2034653384
Short name T422
Test name
Test status
Simulation time 2521749876 ps
CPU time 18.94 seconds
Started Mar 05 01:59:18 PM PST 24
Finished Mar 05 01:59:38 PM PST 24
Peak memory 254840 kb
Host smart-c22dcc29-2ae6-42f8-868c-68658309bc39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20346
53384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2034653384
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1621879042
Short name T296
Test name
Test status
Simulation time 84932997815 ps
CPU time 1792.59 seconds
Started Mar 05 01:59:26 PM PST 24
Finished Mar 05 02:29:19 PM PST 24
Peak memory 272928 kb
Host smart-805f6143-3568-4163-ad7a-65683a2b9c91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621879042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1621879042
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3449110645
Short name T524
Test name
Test status
Simulation time 81982110584 ps
CPU time 1783.01 seconds
Started Mar 05 01:59:33 PM PST 24
Finished Mar 05 02:29:16 PM PST 24
Peak memory 289976 kb
Host smart-b72209de-3c58-4f58-8a3c-e18c17e2f766
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449110645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3449110645
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1163836993
Short name T529
Test name
Test status
Simulation time 3299498407 ps
CPU time 140.26 seconds
Started Mar 05 01:59:33 PM PST 24
Finished Mar 05 02:01:54 PM PST 24
Peak memory 247672 kb
Host smart-5c091a0b-b604-403b-9199-a4d4b6f10eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163836993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1163836993
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3013601785
Short name T544
Test name
Test status
Simulation time 75663297 ps
CPU time 3.62 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 01:59:24 PM PST 24
Peak memory 240772 kb
Host smart-11dbc56d-973e-4f82-ad95-14768c22b9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136
01785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3013601785
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1195974253
Short name T66
Test name
Test status
Simulation time 429305123 ps
CPU time 38.85 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 01:59:59 PM PST 24
Peak memory 247460 kb
Host smart-fb728fc9-3ace-40fa-8d3a-32c8a3405c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11959
74253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1195974253
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3340798809
Short name T651
Test name
Test status
Simulation time 125126759 ps
CPU time 6.99 seconds
Started Mar 05 01:59:33 PM PST 24
Finished Mar 05 01:59:40 PM PST 24
Peak memory 248944 kb
Host smart-c3c0b25d-791e-4592-8714-56b282ea650d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33407
98809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3340798809
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3880904676
Short name T494
Test name
Test status
Simulation time 108448051 ps
CPU time 13.74 seconds
Started Mar 05 01:59:20 PM PST 24
Finished Mar 05 01:59:34 PM PST 24
Peak memory 248976 kb
Host smart-8ee3d1cd-e21b-44e7-9f0b-48c3d4c1d112
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
04676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3880904676
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3541224316
Short name T86
Test name
Test status
Simulation time 29134458645 ps
CPU time 381.17 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:05:55 PM PST 24
Peak memory 257204 kb
Host smart-4a00047a-f1f0-4c18-aebd-1daa02826b58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541224316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3541224316
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1671130734
Short name T515
Test name
Test status
Simulation time 295429265703 ps
CPU time 2585.13 seconds
Started Mar 05 01:59:25 PM PST 24
Finished Mar 05 02:42:32 PM PST 24
Peak memory 289412 kb
Host smart-d76a92c5-6da9-4656-b168-13709a97dd4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671130734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1671130734
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2620845265
Short name T678
Test name
Test status
Simulation time 4147453689 ps
CPU time 99.48 seconds
Started Mar 05 01:59:26 PM PST 24
Finished Mar 05 02:01:06 PM PST 24
Peak memory 249036 kb
Host smart-73dbbaea-f24d-41f9-b3e9-2a54bbf7d2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26208
45265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2620845265
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2110909734
Short name T76
Test name
Test status
Simulation time 322403852 ps
CPU time 19.94 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 01:59:54 PM PST 24
Peak memory 255188 kb
Host smart-bf99439f-3988-40f6-97ae-f2496d8c9623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21109
09734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2110909734
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.834814851
Short name T583
Test name
Test status
Simulation time 161069523806 ps
CPU time 2087.63 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:34:22 PM PST 24
Peak memory 272648 kb
Host smart-1e69ad6b-25cd-4000-83e9-373aa858eb62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834814851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.834814851
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3038535773
Short name T321
Test name
Test status
Simulation time 71246251879 ps
CPU time 482.38 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:07:37 PM PST 24
Peak memory 247944 kb
Host smart-193454c8-f9c6-4c9a-b23f-600bdfced97e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038535773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3038535773
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.890313141
Short name T582
Test name
Test status
Simulation time 115012933 ps
CPU time 13.11 seconds
Started Mar 05 01:59:27 PM PST 24
Finished Mar 05 01:59:41 PM PST 24
Peak memory 255812 kb
Host smart-dcf6b194-160f-4602-a8f7-a318a8e69642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89031
3141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.890313141
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.13810087
Short name T411
Test name
Test status
Simulation time 471585985 ps
CPU time 24.34 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 01:59:58 PM PST 24
Peak memory 247528 kb
Host smart-9a9fa987-b9ce-4fc8-9977-83d5410685af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13810
087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.13810087
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3445085987
Short name T251
Test name
Test status
Simulation time 297891778 ps
CPU time 17.81 seconds
Started Mar 05 01:59:26 PM PST 24
Finished Mar 05 01:59:45 PM PST 24
Peak memory 252644 kb
Host smart-f39bf7d0-ffba-4655-a976-9afcfcd3c75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34450
85987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3445085987
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2659270770
Short name T268
Test name
Test status
Simulation time 302009185 ps
CPU time 19.07 seconds
Started Mar 05 01:59:27 PM PST 24
Finished Mar 05 01:59:47 PM PST 24
Peak memory 248984 kb
Host smart-a4446414-e35c-4b76-bd55-603fe3e83dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26592
70770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2659270770
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4236729122
Short name T687
Test name
Test status
Simulation time 55463630124 ps
CPU time 1546.68 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:25:21 PM PST 24
Peak memory 289932 kb
Host smart-78d40dab-0722-45dd-89a3-448cedd0c861
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236729122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4236729122
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1629932290
Short name T112
Test name
Test status
Simulation time 153127529039 ps
CPU time 2311 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:38:05 PM PST 24
Peak memory 282780 kb
Host smart-5d2d323f-22f6-4088-8f4a-57addafacedb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629932290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1629932290
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.24786685
Short name T292
Test name
Test status
Simulation time 3442877652 ps
CPU time 219.92 seconds
Started Mar 05 01:59:35 PM PST 24
Finished Mar 05 02:03:15 PM PST 24
Peak memory 256568 kb
Host smart-507546fd-6b81-45b4-83fc-6add6d3ecae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24786
685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.24786685
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1908406363
Short name T517
Test name
Test status
Simulation time 965610893 ps
CPU time 51.23 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:00:25 PM PST 24
Peak memory 255268 kb
Host smart-6f0bfe61-16bc-46c7-b6ed-5c89d3fb07c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19084
06363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1908406363
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.257805031
Short name T13
Test name
Test status
Simulation time 21553038364 ps
CPU time 968.28 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:15:43 PM PST 24
Peak memory 273600 kb
Host smart-39b29cf3-9c67-454e-baa7-80b4bc56e59c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257805031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.257805031
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2060616877
Short name T363
Test name
Test status
Simulation time 79424849195 ps
CPU time 2530.12 seconds
Started Mar 05 01:59:33 PM PST 24
Finished Mar 05 02:41:44 PM PST 24
Peak memory 289040 kb
Host smart-e3601bf6-3c04-4404-aefc-a9d11d9d128a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060616877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2060616877
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.945172350
Short name T508
Test name
Test status
Simulation time 4395645472 ps
CPU time 45.42 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 02:00:20 PM PST 24
Peak memory 249048 kb
Host smart-83deca03-6853-41c0-8083-bcf0eec2ac9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94517
2350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.945172350
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1912310444
Short name T428
Test name
Test status
Simulation time 1292321289 ps
CPU time 33.3 seconds
Started Mar 05 01:59:35 PM PST 24
Finished Mar 05 02:00:08 PM PST 24
Peak memory 255348 kb
Host smart-685aaf78-72c2-4937-aa6a-7ac6ef40419c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19123
10444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1912310444
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.959865069
Short name T419
Test name
Test status
Simulation time 132151949 ps
CPU time 16.38 seconds
Started Mar 05 01:59:35 PM PST 24
Finished Mar 05 01:59:52 PM PST 24
Peak memory 247304 kb
Host smart-56aa695d-40bc-4e60-b651-21c23f0a1a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95986
5069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.959865069
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3509590982
Short name T549
Test name
Test status
Simulation time 116626719 ps
CPU time 4.3 seconds
Started Mar 05 01:59:34 PM PST 24
Finished Mar 05 01:59:38 PM PST 24
Peak memory 240756 kb
Host smart-a72911fe-9630-46df-8bb5-4d644944dcea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35095
90982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3509590982
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.916617711
Short name T698
Test name
Test status
Simulation time 6669959613 ps
CPU time 806.17 seconds
Started Mar 05 01:59:42 PM PST 24
Finished Mar 05 02:13:08 PM PST 24
Peak memory 267468 kb
Host smart-c8964fd5-c1b7-4c0f-b9fc-e89a4926f0b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916617711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.916617711
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3702069696
Short name T392
Test name
Test status
Simulation time 293961781 ps
CPU time 5.47 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 01:59:50 PM PST 24
Peak memory 238896 kb
Host smart-5d4cdd9b-9a70-42c4-b728-6fecdc18d67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37020
69696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3702069696
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3797571894
Short name T77
Test name
Test status
Simulation time 1252980051 ps
CPU time 79.37 seconds
Started Mar 05 01:59:41 PM PST 24
Finished Mar 05 02:01:01 PM PST 24
Peak memory 255428 kb
Host smart-10528e9e-929a-43e9-a23b-05b8dbb116e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37975
71894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3797571894
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.40980453
Short name T342
Test name
Test status
Simulation time 37280203461 ps
CPU time 2369.89 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:39:13 PM PST 24
Peak memory 281824 kb
Host smart-7fd20004-860c-4400-bc65-d642695eee28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40980453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.40980453
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2047291607
Short name T480
Test name
Test status
Simulation time 136059834400 ps
CPU time 2473.07 seconds
Started Mar 05 01:59:42 PM PST 24
Finished Mar 05 02:40:55 PM PST 24
Peak memory 285332 kb
Host smart-db086b61-9202-499c-b2da-eabc9d63d930
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047291607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2047291607
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.513782597
Short name T211
Test name
Test status
Simulation time 11644330410 ps
CPU time 131.69 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:01:56 PM PST 24
Peak memory 247836 kb
Host smart-30ec7cc6-886f-4453-a785-7e583151eae0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513782597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.513782597
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3201442143
Short name T448
Test name
Test status
Simulation time 3066213363 ps
CPU time 43.4 seconds
Started Mar 05 01:59:42 PM PST 24
Finished Mar 05 02:00:26 PM PST 24
Peak memory 257228 kb
Host smart-6be6fe3b-cc9d-497e-b6d4-c0738e94279a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32014
42143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3201442143
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4265537844
Short name T671
Test name
Test status
Simulation time 2150534009 ps
CPU time 70.69 seconds
Started Mar 05 01:59:41 PM PST 24
Finished Mar 05 02:00:52 PM PST 24
Peak memory 255656 kb
Host smart-755ebbfa-9cfc-4540-a16b-1a545147efec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42655
37844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4265537844
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2082257275
Short name T254
Test name
Test status
Simulation time 4026507276 ps
CPU time 26.44 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:00:10 PM PST 24
Peak memory 247848 kb
Host smart-fe0ad4a6-ef02-40b9-b1e7-176c554d6a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20822
57275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2082257275
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1384673083
Short name T70
Test name
Test status
Simulation time 345793488 ps
CPU time 32.32 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:00:16 PM PST 24
Peak memory 248988 kb
Host smart-ee40ff4e-70ab-4f9b-bc79-a4d3b2a6cd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13846
73083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1384673083
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.423321637
Short name T89
Test name
Test status
Simulation time 39337257634 ps
CPU time 2595.63 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:43:00 PM PST 24
Peak memory 289836 kb
Host smart-d9417349-19fe-4926-a809-66c08d5bf167
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423321637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.423321637
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3890382204
Short name T246
Test name
Test status
Simulation time 39132954927 ps
CPU time 2532.91 seconds
Started Mar 05 01:59:46 PM PST 24
Finished Mar 05 02:41:59 PM PST 24
Peak memory 289372 kb
Host smart-f7cacc5e-9474-48b6-89e8-ddd8a82a6328
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890382204 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3890382204
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3615733487
Short name T380
Test name
Test status
Simulation time 36273948609 ps
CPU time 976.3 seconds
Started Mar 05 01:59:48 PM PST 24
Finished Mar 05 02:16:04 PM PST 24
Peak memory 273484 kb
Host smart-b8e867c2-7776-4d13-95b8-c5084eeea4df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615733487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3615733487
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3213823707
Short name T608
Test name
Test status
Simulation time 3506649325 ps
CPU time 80.07 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:01:04 PM PST 24
Peak memory 248588 kb
Host smart-675cdf57-a3d7-4907-b01b-82767337dd20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
23707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3213823707
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1165162190
Short name T537
Test name
Test status
Simulation time 1071738006 ps
CPU time 68.02 seconds
Started Mar 05 01:59:45 PM PST 24
Finished Mar 05 02:00:54 PM PST 24
Peak memory 255324 kb
Host smart-a789e37c-f790-49a4-9bd1-6ecf5c510fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11651
62190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1165162190
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3938594610
Short name T579
Test name
Test status
Simulation time 62746517185 ps
CPU time 675.11 seconds
Started Mar 05 01:59:41 PM PST 24
Finished Mar 05 02:10:56 PM PST 24
Peak memory 273064 kb
Host smart-3fc0b029-a627-4d79-ac76-9fc1f53e5f5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938594610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3938594610
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3161033839
Short name T14
Test name
Test status
Simulation time 288767026775 ps
CPU time 2924.64 seconds
Started Mar 05 01:59:42 PM PST 24
Finished Mar 05 02:48:27 PM PST 24
Peak memory 281428 kb
Host smart-705077ae-27c4-4483-a9cd-91026ce66d98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161033839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3161033839
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1500403157
Short name T310
Test name
Test status
Simulation time 38654571348 ps
CPU time 374.76 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:05:58 PM PST 24
Peak memory 247852 kb
Host smart-ebc78bde-25cf-4c11-a165-b4f1479bc2f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500403157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1500403157
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1560703318
Short name T503
Test name
Test status
Simulation time 2322328158 ps
CPU time 67.2 seconds
Started Mar 05 01:59:43 PM PST 24
Finished Mar 05 02:00:50 PM PST 24
Peak memory 255812 kb
Host smart-c6681563-b48c-43d4-81b4-093853975e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15607
03318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1560703318
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2360900866
Short name T283
Test name
Test status
Simulation time 621736452 ps
CPU time 23.15 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:00:07 PM PST 24
Peak memory 248516 kb
Host smart-0be0ac13-332e-4d8e-a6d6-cce6d4730570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23609
00866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2360900866
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2220354192
Short name T569
Test name
Test status
Simulation time 557664957 ps
CPU time 8.77 seconds
Started Mar 05 01:59:42 PM PST 24
Finished Mar 05 01:59:51 PM PST 24
Peak memory 251896 kb
Host smart-bf283c9a-4e3c-4773-8eab-031cbe48d575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22203
54192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2220354192
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.55603291
Short name T51
Test name
Test status
Simulation time 7569386317 ps
CPU time 640.56 seconds
Started Mar 05 01:59:57 PM PST 24
Finished Mar 05 02:10:38 PM PST 24
Peak memory 265432 kb
Host smart-ef072e18-039f-4531-b10e-f8e8b78eda03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55603291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.55603291
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2430276705
Short name T562
Test name
Test status
Simulation time 13310501325 ps
CPU time 197.04 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:03:11 PM PST 24
Peak memory 256456 kb
Host smart-410dfaca-cfa6-4f4f-b584-a5bacfcc4757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24302
76705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2430276705
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2669603160
Short name T469
Test name
Test status
Simulation time 2802411754 ps
CPU time 45.37 seconds
Started Mar 05 01:59:45 PM PST 24
Finished Mar 05 02:00:31 PM PST 24
Peak memory 256248 kb
Host smart-71f78a7a-16d3-4b3a-922c-08d94ad1a2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26696
03160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2669603160
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3634195465
Short name T341
Test name
Test status
Simulation time 8920172592 ps
CPU time 1050.91 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:17:24 PM PST 24
Peak memory 273152 kb
Host smart-cf30a887-d79a-4852-a08f-be111d88adbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634195465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3634195465
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.3288142255
Short name T487
Test name
Test status
Simulation time 112986687350 ps
CPU time 3205.39 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:53:24 PM PST 24
Peak memory 288128 kb
Host smart-a9ebd037-3d7b-4cf0-a439-1edbb4974e80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288142255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.3288142255
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.981701562
Short name T313
Test name
Test status
Simulation time 12743188220 ps
CPU time 94.23 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:01:29 PM PST 24
Peak memory 247620 kb
Host smart-c6dd45b0-a384-4a5b-a596-582d2b83123c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981701562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.981701562
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3711528250
Short name T538
Test name
Test status
Simulation time 268594318 ps
CPU time 17.49 seconds
Started Mar 05 01:59:48 PM PST 24
Finished Mar 05 02:00:06 PM PST 24
Peak memory 255680 kb
Host smart-5f41448a-c362-4fea-896b-dec93de52832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37115
28250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3711528250
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.4079298001
Short name T648
Test name
Test status
Simulation time 2418163422 ps
CPU time 57.34 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:00:41 PM PST 24
Peak memory 248668 kb
Host smart-30a89faa-44a0-465c-99a7-23971943b0ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40792
98001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.4079298001
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1768337782
Short name T262
Test name
Test status
Simulation time 918442945 ps
CPU time 29.95 seconds
Started Mar 05 01:59:56 PM PST 24
Finished Mar 05 02:00:26 PM PST 24
Peak memory 248976 kb
Host smart-de8dd7fc-4abd-46f6-b9ae-6a2e7451251a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
37782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1768337782
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3753239658
Short name T390
Test name
Test status
Simulation time 988611669 ps
CPU time 24.81 seconds
Started Mar 05 01:59:44 PM PST 24
Finished Mar 05 02:00:09 PM PST 24
Peak memory 248960 kb
Host smart-9a3d4825-598c-44a4-b218-97a0f52ffccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37532
39658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3753239658
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2717643844
Short name T47
Test name
Test status
Simulation time 128929493266 ps
CPU time 3376.06 seconds
Started Mar 05 01:59:57 PM PST 24
Finished Mar 05 02:56:14 PM PST 24
Peak memory 300424 kb
Host smart-7ba2abf1-a4ec-42ed-8043-223a3c8d117e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717643844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2717643844
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3856711609
Short name T580
Test name
Test status
Simulation time 27113388834 ps
CPU time 1822.58 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:30:17 PM PST 24
Peak memory 273692 kb
Host smart-2e0b6d94-94b4-40b8-ba07-24a7565ecc8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856711609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3856711609
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2856934374
Short name T677
Test name
Test status
Simulation time 548281311 ps
CPU time 40.15 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:33 PM PST 24
Peak memory 248520 kb
Host smart-fd13dff3-481b-4e4f-b833-5ea166e79e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28569
34374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2856934374
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1513784082
Short name T424
Test name
Test status
Simulation time 2903482659 ps
CPU time 36.86 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:30 PM PST 24
Peak memory 255520 kb
Host smart-d6096e62-dd94-4e81-b230-a1bd0dfbb04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
84082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1513784082
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1124753037
Short name T555
Test name
Test status
Simulation time 22307911814 ps
CPU time 822.93 seconds
Started Mar 05 01:59:55 PM PST 24
Finished Mar 05 02:13:39 PM PST 24
Peak memory 266464 kb
Host smart-477b1583-dd13-4f85-8ba6-7ea36b2e5e97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124753037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1124753037
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3142818485
Short name T305
Test name
Test status
Simulation time 31634766260 ps
CPU time 354.44 seconds
Started Mar 05 01:59:56 PM PST 24
Finished Mar 05 02:05:50 PM PST 24
Peak memory 247740 kb
Host smart-e18abc85-2e5b-4c01-80f7-8cd41baec371
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142818485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3142818485
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2603288384
Short name T675
Test name
Test status
Simulation time 2647882299 ps
CPU time 42.42 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:35 PM PST 24
Peak memory 257200 kb
Host smart-bcd0c0fc-3c1b-4979-8500-c107f73f51e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26032
88384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2603288384
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.96773187
Short name T62
Test name
Test status
Simulation time 200000443 ps
CPU time 15 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:00:10 PM PST 24
Peak memory 251784 kb
Host smart-1a066213-2c1d-4e4b-be2a-49f54eef8186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96773
187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.96773187
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.743597792
Short name T454
Test name
Test status
Simulation time 302243924 ps
CPU time 17.64 seconds
Started Mar 05 01:59:56 PM PST 24
Finished Mar 05 02:00:14 PM PST 24
Peak memory 255232 kb
Host smart-6c6ad991-d04c-434f-b242-9ad4c4150462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74359
7792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.743597792
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.711180593
Short name T663
Test name
Test status
Simulation time 58986712 ps
CPU time 3.85 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 01:59:58 PM PST 24
Peak memory 240772 kb
Host smart-5cccb958-6607-43e4-901d-99b5a96df21d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71118
0593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.711180593
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1577201348
Short name T630
Test name
Test status
Simulation time 32574902527 ps
CPU time 1537.79 seconds
Started Mar 05 01:59:57 PM PST 24
Finished Mar 05 02:25:35 PM PST 24
Peak memory 289868 kb
Host smart-7f446355-ef0d-41e2-bec7-4d0747d9248a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577201348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1577201348
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4177357135
Short name T177
Test name
Test status
Simulation time 653958043999 ps
CPU time 3781.74 seconds
Started Mar 05 01:59:55 PM PST 24
Finished Mar 05 03:02:58 PM PST 24
Peak memory 298272 kb
Host smart-0a47aa55-a4e0-4a0b-96f1-f74995456172
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177357135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4177357135
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.4127188362
Short name T226
Test name
Test status
Simulation time 15871976 ps
CPU time 2.6 seconds
Started Mar 05 01:57:55 PM PST 24
Finished Mar 05 01:57:58 PM PST 24
Peak memory 249144 kb
Host smart-d42e66e7-059c-4d85-9f88-1ca1ddf71b0d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4127188362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4127188362
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1210857917
Short name T619
Test name
Test status
Simulation time 44400068500 ps
CPU time 1417.38 seconds
Started Mar 05 01:57:54 PM PST 24
Finished Mar 05 02:21:32 PM PST 24
Peak memory 268516 kb
Host smart-8cf34219-4379-45cc-a398-05ba9acdef27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210857917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1210857917
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1330214078
Short name T658
Test name
Test status
Simulation time 136993733 ps
CPU time 8.32 seconds
Started Mar 05 01:57:52 PM PST 24
Finished Mar 05 01:58:01 PM PST 24
Peak memory 240744 kb
Host smart-48f6f6cc-e360-4bb9-b026-b9b514f3b312
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1330214078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1330214078
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1627246547
Short name T239
Test name
Test status
Simulation time 3174237479 ps
CPU time 87.88 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:59:16 PM PST 24
Peak memory 256672 kb
Host smart-7b2dac47-56b3-4aa3-92d8-7badcfffe5a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16272
46547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1627246547
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.937465857
Short name T425
Test name
Test status
Simulation time 402715794 ps
CPU time 8.18 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:57:57 PM PST 24
Peak memory 252672 kb
Host smart-7baf0f6b-69c8-457f-a0a2-40e5c1120706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93746
5857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.937465857
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2637888541
Short name T702
Test name
Test status
Simulation time 122469371595 ps
CPU time 1604.1 seconds
Started Mar 05 01:57:57 PM PST 24
Finished Mar 05 02:24:42 PM PST 24
Peak memory 273236 kb
Host smart-2e9af01e-0214-4b86-b05a-ff4da36b5b93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637888541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2637888541
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1706369412
Short name T536
Test name
Test status
Simulation time 78681113675 ps
CPU time 1505.16 seconds
Started Mar 05 01:57:53 PM PST 24
Finished Mar 05 02:22:58 PM PST 24
Peak memory 289236 kb
Host smart-9af5a21e-b543-4ddf-ac18-234b6ceb1cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706369412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1706369412
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.4098200279
Short name T391
Test name
Test status
Simulation time 1349664808 ps
CPU time 22.52 seconds
Started Mar 05 01:57:48 PM PST 24
Finished Mar 05 01:58:11 PM PST 24
Peak memory 248972 kb
Host smart-6ee407bd-1080-4240-9fa7-6eb710178b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40982
00279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.4098200279
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3458688172
Short name T617
Test name
Test status
Simulation time 6013113593 ps
CPU time 40.39 seconds
Started Mar 05 01:57:49 PM PST 24
Finished Mar 05 01:58:30 PM PST 24
Peak memory 256412 kb
Host smart-1adb5f65-ff10-4963-81fb-b6916e70f62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
88172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3458688172
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1832287436
Short name T564
Test name
Test status
Simulation time 314252708 ps
CPU time 19.71 seconds
Started Mar 05 01:57:54 PM PST 24
Finished Mar 05 01:58:14 PM PST 24
Peak memory 248988 kb
Host smart-8bedabe4-9a3c-4f0f-9ef9-ae8028ed0633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18322
87436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1832287436
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1306412797
Short name T233
Test name
Test status
Simulation time 283506720 ps
CPU time 12.59 seconds
Started Mar 05 01:57:49 PM PST 24
Finished Mar 05 01:58:02 PM PST 24
Peak memory 254312 kb
Host smart-8b795f35-16e2-4c21-8675-3860c27f1b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13064
12797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1306412797
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.344366513
Short name T607
Test name
Test status
Simulation time 167514954381 ps
CPU time 1458.75 seconds
Started Mar 05 01:57:55 PM PST 24
Finished Mar 05 02:22:14 PM PST 24
Peak memory 287396 kb
Host smart-b9069d99-96d5-47d0-8bbb-ac693c5b68ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344366513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.344366513
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.4073393729
Short name T467
Test name
Test status
Simulation time 66771997276 ps
CPU time 1924.79 seconds
Started Mar 05 01:59:57 PM PST 24
Finished Mar 05 02:32:02 PM PST 24
Peak memory 285660 kb
Host smart-e29cbf41-be8d-47d2-8e04-2cafb8b985aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073393729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.4073393729
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.31499814
Short name T641
Test name
Test status
Simulation time 1155012287 ps
CPU time 64.99 seconds
Started Mar 05 01:59:54 PM PST 24
Finished Mar 05 02:00:59 PM PST 24
Peak memory 256300 kb
Host smart-8b7a4f90-ebd9-400c-969e-529903e48718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.31499814
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3500235834
Short name T684
Test name
Test status
Simulation time 997020723 ps
CPU time 17.45 seconds
Started Mar 05 01:59:52 PM PST 24
Finished Mar 05 02:00:10 PM PST 24
Peak memory 252836 kb
Host smart-8180f400-5903-4d8c-a23c-890b2a28aa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35002
35834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3500235834
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2462185211
Short name T331
Test name
Test status
Simulation time 831457499506 ps
CPU time 3441.41 seconds
Started Mar 05 02:00:03 PM PST 24
Finished Mar 05 02:57:25 PM PST 24
Peak memory 289344 kb
Host smart-c9cb595f-9762-4dd6-9b2e-ba775d717329
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462185211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2462185211
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3761870650
Short name T626
Test name
Test status
Simulation time 67149438643 ps
CPU time 798.42 seconds
Started Mar 05 02:00:00 PM PST 24
Finished Mar 05 02:13:19 PM PST 24
Peak memory 272876 kb
Host smart-abc2bb4c-ee7c-4e5a-bd45-bc4f90bbed94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761870650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3761870650
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.499125085
Short name T307
Test name
Test status
Simulation time 4448969334 ps
CPU time 196.74 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:03:15 PM PST 24
Peak memory 247940 kb
Host smart-1dfcb9d9-118c-44fa-bc69-2b34933aba3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499125085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.499125085
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3579924176
Short name T385
Test name
Test status
Simulation time 472600697 ps
CPU time 30.31 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:24 PM PST 24
Peak memory 254676 kb
Host smart-8f4c818b-3752-4397-9b29-6f7f61f44c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35799
24176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3579924176
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.52367471
Short name T379
Test name
Test status
Simulation time 107162620 ps
CPU time 9.81 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:04 PM PST 24
Peak memory 253820 kb
Host smart-3f2e20b2-6013-418d-bba4-b28cc0568cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52367
471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.52367471
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.45353015
Short name T565
Test name
Test status
Simulation time 720726775 ps
CPU time 46.49 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:39 PM PST 24
Peak memory 255116 kb
Host smart-83cd880e-930d-4d92-99b2-61412386ebde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45353
015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.45353015
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2292016689
Short name T655
Test name
Test status
Simulation time 146957574 ps
CPU time 10.02 seconds
Started Mar 05 01:59:53 PM PST 24
Finished Mar 05 02:00:03 PM PST 24
Peak memory 248964 kb
Host smart-c2677e1c-6a39-4ae0-a1e2-9ddd94597528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22920
16689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2292016689
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1937428155
Short name T35
Test name
Test status
Simulation time 23954666442 ps
CPU time 1516.6 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:25:15 PM PST 24
Peak memory 287212 kb
Host smart-f50bff27-8d42-44f0-b29a-4570153d08a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937428155 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1937428155
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2826894533
Short name T59
Test name
Test status
Simulation time 44198363575 ps
CPU time 2182.63 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:36:21 PM PST 24
Peak memory 289340 kb
Host smart-853c89b7-9220-494c-9614-2aad00933884
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826894533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2826894533
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3864418443
Short name T456
Test name
Test status
Simulation time 1578696801 ps
CPU time 48.01 seconds
Started Mar 05 01:59:55 PM PST 24
Finished Mar 05 02:00:43 PM PST 24
Peak memory 256540 kb
Host smart-8a0a0d33-f61e-4f97-9882-e77f075b9b3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38644
18443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3864418443
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.2494306366
Short name T18
Test name
Test status
Simulation time 5013072939 ps
CPU time 38.19 seconds
Started Mar 05 01:59:59 PM PST 24
Finished Mar 05 02:00:37 PM PST 24
Peak memory 255528 kb
Host smart-ead479a8-3d47-42bc-abc4-41be549220a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24943
06366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.2494306366
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1364427106
Short name T231
Test name
Test status
Simulation time 39131870426 ps
CPU time 827.07 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:13:46 PM PST 24
Peak memory 273612 kb
Host smart-56e1243c-8325-4aab-b6d8-36aa46327773
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364427106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1364427106
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.2123338201
Short name T574
Test name
Test status
Simulation time 46631857977 ps
CPU time 1244.58 seconds
Started Mar 05 01:59:59 PM PST 24
Finished Mar 05 02:20:43 PM PST 24
Peak memory 266468 kb
Host smart-2fbb58ea-f12a-4083-9440-17efd32291f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123338201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.2123338201
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3543362790
Short name T597
Test name
Test status
Simulation time 2369524173 ps
CPU time 91.64 seconds
Started Mar 05 02:00:00 PM PST 24
Finished Mar 05 02:01:32 PM PST 24
Peak memory 249036 kb
Host smart-802d3005-b279-4595-8058-43dcf78796e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
62790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3543362790
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2578467441
Short name T234
Test name
Test status
Simulation time 1286403644 ps
CPU time 65.8 seconds
Started Mar 05 01:59:56 PM PST 24
Finished Mar 05 02:01:02 PM PST 24
Peak memory 255448 kb
Host smart-d724fa75-f5c3-4836-8b42-b208d0fe83eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25784
67441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2578467441
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2263682587
Short name T689
Test name
Test status
Simulation time 1949372563 ps
CPU time 29.16 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:00:28 PM PST 24
Peak memory 255100 kb
Host smart-60901700-ac0d-4eff-b5af-618db5a1d114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
82587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2263682587
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2653989415
Short name T96
Test name
Test status
Simulation time 246997722 ps
CPU time 23.88 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:00:22 PM PST 24
Peak memory 248976 kb
Host smart-b777936f-278e-4b3a-a039-dd162c8a42fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
89415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2653989415
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.54433996
Short name T260
Test name
Test status
Simulation time 205319125788 ps
CPU time 2889.19 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:48:14 PM PST 24
Peak memory 289228 kb
Host smart-eb2edee5-ded7-4850-874a-f65b3199c502
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54433996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_hand
ler_stress_all.54433996
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.234577772
Short name T199
Test name
Test status
Simulation time 46025442407 ps
CPU time 4875.82 seconds
Started Mar 05 01:59:59 PM PST 24
Finished Mar 05 03:21:16 PM PST 24
Peak memory 338692 kb
Host smart-35232510-ce70-460d-8619-2d9bc1bf7cfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234577772 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.234577772
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3674028688
Short name T6
Test name
Test status
Simulation time 4691090673 ps
CPU time 152.93 seconds
Started Mar 05 01:59:59 PM PST 24
Finished Mar 05 02:02:32 PM PST 24
Peak memory 248748 kb
Host smart-2be1feb9-bcff-42d8-9c22-52d83362d7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
28688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3674028688
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.436637652
Short name T429
Test name
Test status
Simulation time 107649202 ps
CPU time 5.4 seconds
Started Mar 05 01:59:58 PM PST 24
Finished Mar 05 02:00:04 PM PST 24
Peak memory 238904 kb
Host smart-873b31d0-a28d-4284-97c0-5b4c741c853f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43663
7652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.436637652
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1690625462
Short name T316
Test name
Test status
Simulation time 44463170350 ps
CPU time 2648.67 seconds
Started Mar 05 02:00:08 PM PST 24
Finished Mar 05 02:44:18 PM PST 24
Peak memory 289144 kb
Host smart-8426fb77-d196-45f8-8566-1cda125ec391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690625462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1690625462
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2990205304
Short name T620
Test name
Test status
Simulation time 39167591947 ps
CPU time 2319.38 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:38:44 PM PST 24
Peak memory 283812 kb
Host smart-0c4a014f-c6cc-4435-a1cc-c7dd6eeb421f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990205304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2990205304
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3134339500
Short name T590
Test name
Test status
Simulation time 17516119529 ps
CPU time 396 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:06:42 PM PST 24
Peak memory 255076 kb
Host smart-39e7a428-30fd-4b88-8225-a22cc2e25433
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134339500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3134339500
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3301863285
Short name T546
Test name
Test status
Simulation time 676628712 ps
CPU time 21.47 seconds
Started Mar 05 01:59:59 PM PST 24
Finished Mar 05 02:00:21 PM PST 24
Peak memory 248992 kb
Host smart-5b705f7f-7969-4a11-9d1e-26d7742b92a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33018
63285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3301863285
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.104553913
Short name T463
Test name
Test status
Simulation time 126987061 ps
CPU time 9.4 seconds
Started Mar 05 02:00:01 PM PST 24
Finished Mar 05 02:00:11 PM PST 24
Peak memory 249700 kb
Host smart-dc1a59bb-93b0-4c4e-a502-ad1cef60feaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
3913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.104553913
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.38051855
Short name T635
Test name
Test status
Simulation time 1439295272 ps
CPU time 15.32 seconds
Started Mar 05 02:00:01 PM PST 24
Finished Mar 05 02:00:17 PM PST 24
Peak memory 252920 kb
Host smart-6b66947e-589e-4139-9443-192291a917e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38051
855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.38051855
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.943822638
Short name T628
Test name
Test status
Simulation time 416232160 ps
CPU time 13.6 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:00:19 PM PST 24
Peak memory 249036 kb
Host smart-a5723e4b-284b-43e9-9cf3-9957265e52fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94382
2638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.943822638
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.412212294
Short name T110
Test name
Test status
Simulation time 54587283696 ps
CPU time 1583.72 seconds
Started Mar 05 02:00:07 PM PST 24
Finished Mar 05 02:26:31 PM PST 24
Peak memory 288912 kb
Host smart-66e2ead3-ddc6-474d-b7f8-2b0d5d7f05a7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412212294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.412212294
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.95864957
Short name T522
Test name
Test status
Simulation time 10544285671 ps
CPU time 912.13 seconds
Started Mar 05 02:00:11 PM PST 24
Finished Mar 05 02:15:24 PM PST 24
Peak memory 273612 kb
Host smart-7900b74b-42da-490c-a7cc-48abe82fe17d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95864957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.95864957
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1505016300
Short name T360
Test name
Test status
Simulation time 2413726409 ps
CPU time 126.75 seconds
Started Mar 05 02:00:03 PM PST 24
Finished Mar 05 02:02:09 PM PST 24
Peak memory 249156 kb
Host smart-2b4c25c5-f84d-4698-9318-1f1647d13a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15050
16300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1505016300
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2781247207
Short name T402
Test name
Test status
Simulation time 400503660 ps
CPU time 8.28 seconds
Started Mar 05 02:00:06 PM PST 24
Finished Mar 05 02:00:14 PM PST 24
Peak memory 249744 kb
Host smart-d3160ba0-2939-4bd9-969c-18e05e796873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27812
47207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2781247207
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.630822119
Short name T327
Test name
Test status
Simulation time 96410099401 ps
CPU time 1776.99 seconds
Started Mar 05 02:00:06 PM PST 24
Finished Mar 05 02:29:43 PM PST 24
Peak memory 289392 kb
Host smart-239752cd-cf37-4e05-8855-94bb038bba60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630822119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.630822119
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2514189313
Short name T533
Test name
Test status
Simulation time 47889407741 ps
CPU time 1448.45 seconds
Started Mar 05 02:00:07 PM PST 24
Finished Mar 05 02:24:15 PM PST 24
Peak memory 289612 kb
Host smart-8261b347-bc95-462e-9e06-71a63e8b8c28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514189313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2514189313
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3703350148
Short name T88
Test name
Test status
Simulation time 67785213508 ps
CPU time 474.7 seconds
Started Mar 05 02:00:08 PM PST 24
Finished Mar 05 02:08:02 PM PST 24
Peak memory 247104 kb
Host smart-cecb0d3b-225a-4c3a-8c98-0bfb33cbc8c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703350148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3703350148
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3871025319
Short name T712
Test name
Test status
Simulation time 8653596080 ps
CPU time 30.3 seconds
Started Mar 05 02:00:07 PM PST 24
Finished Mar 05 02:00:37 PM PST 24
Peak memory 248980 kb
Host smart-6b4ee777-cfe2-4c37-a85c-c95ea2cdbab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
25319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3871025319
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1793597946
Short name T381
Test name
Test status
Simulation time 363272352 ps
CPU time 33.91 seconds
Started Mar 05 02:00:06 PM PST 24
Finished Mar 05 02:00:40 PM PST 24
Peak memory 247348 kb
Host smart-d671a2e7-f341-485f-a2de-d356b67f8370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17935
97946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1793597946
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.529816440
Short name T633
Test name
Test status
Simulation time 769242740 ps
CPU time 28.05 seconds
Started Mar 05 02:00:07 PM PST 24
Finished Mar 05 02:00:35 PM PST 24
Peak memory 247300 kb
Host smart-c2b6bacb-1435-4ee4-ad02-c2c6e4fb93fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52981
6440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.529816440
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2000562819
Short name T705
Test name
Test status
Simulation time 339644558 ps
CPU time 37.1 seconds
Started Mar 05 02:00:07 PM PST 24
Finished Mar 05 02:00:44 PM PST 24
Peak memory 255720 kb
Host smart-bd078d6b-502e-4632-8841-d69aac6ca4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20005
62819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2000562819
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.794898187
Short name T28
Test name
Test status
Simulation time 108260449714 ps
CPU time 5758.56 seconds
Started Mar 05 02:00:11 PM PST 24
Finished Mar 05 03:36:10 PM PST 24
Peak memory 349112 kb
Host smart-efb12069-7ff7-4530-977c-da9c8c20a1e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794898187 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.794898187
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3827125244
Short name T194
Test name
Test status
Simulation time 22789958170 ps
CPU time 1084.52 seconds
Started Mar 05 02:00:11 PM PST 24
Finished Mar 05 02:18:16 PM PST 24
Peak memory 270564 kb
Host smart-d883f785-0cb5-4b25-a23d-260b9bfca6a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827125244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3827125244
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.633899219
Short name T604
Test name
Test status
Simulation time 2693475195 ps
CPU time 44 seconds
Started Mar 05 02:00:10 PM PST 24
Finished Mar 05 02:00:54 PM PST 24
Peak memory 254604 kb
Host smart-b2ef0c8b-745c-46d9-9ef0-4cd119f5ed7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63389
9219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.633899219
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3125979767
Short name T389
Test name
Test status
Simulation time 19713425750 ps
CPU time 84.07 seconds
Started Mar 05 02:00:09 PM PST 24
Finished Mar 05 02:01:33 PM PST 24
Peak memory 255228 kb
Host smart-09261030-c902-430b-8a00-8e959cee9377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31259
79767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3125979767
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.48728927
Short name T694
Test name
Test status
Simulation time 204652911836 ps
CPU time 2150.48 seconds
Started Mar 05 02:00:12 PM PST 24
Finished Mar 05 02:36:02 PM PST 24
Peak memory 273268 kb
Host smart-1d02423e-ef8c-4c90-8b26-351335e31b2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48728927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.48728927
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2199134133
Short name T241
Test name
Test status
Simulation time 63520678649 ps
CPU time 609.88 seconds
Started Mar 05 02:00:17 PM PST 24
Finished Mar 05 02:10:27 PM PST 24
Peak memory 247932 kb
Host smart-c434c0f8-3753-4cd0-99be-f7cf6e063918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199134133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2199134133
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.4137096542
Short name T406
Test name
Test status
Simulation time 94823932 ps
CPU time 4.66 seconds
Started Mar 05 02:00:12 PM PST 24
Finished Mar 05 02:00:17 PM PST 24
Peak memory 248968 kb
Host smart-27826c93-5a1b-45b3-b354-cb71da96f6fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370
96542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.4137096542
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3957867930
Short name T240
Test name
Test status
Simulation time 111954923 ps
CPU time 11.99 seconds
Started Mar 05 02:00:08 PM PST 24
Finished Mar 05 02:00:20 PM PST 24
Peak memory 255876 kb
Host smart-e666c643-d380-428b-8e10-d13db8401f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39578
67930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3957867930
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1211296945
Short name T498
Test name
Test status
Simulation time 1207679048 ps
CPU time 37.89 seconds
Started Mar 05 02:00:10 PM PST 24
Finished Mar 05 02:00:48 PM PST 24
Peak memory 255336 kb
Host smart-95248777-afaa-48a4-9b22-77459511482a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12112
96945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1211296945
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4274627395
Short name T585
Test name
Test status
Simulation time 151164950 ps
CPU time 8.4 seconds
Started Mar 05 02:00:05 PM PST 24
Finished Mar 05 02:00:14 PM PST 24
Peak memory 248976 kb
Host smart-d68c3724-8a10-49b3-a4af-ff62bdfa9355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42746
27395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4274627395
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2350331782
Short name T506
Test name
Test status
Simulation time 16432678656 ps
CPU time 1104.75 seconds
Started Mar 05 02:00:13 PM PST 24
Finished Mar 05 02:18:38 PM PST 24
Peak memory 272512 kb
Host smart-ee9752d8-8182-4158-83ae-21baa343cef9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350331782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2350331782
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3187374367
Short name T493
Test name
Test status
Simulation time 3056140742 ps
CPU time 199.11 seconds
Started Mar 05 02:00:13 PM PST 24
Finished Mar 05 02:03:32 PM PST 24
Peak memory 249268 kb
Host smart-2f77ae1b-eee4-4d2a-9107-f3b2851f2c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873
74367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3187374367
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2271338779
Short name T563
Test name
Test status
Simulation time 203009356 ps
CPU time 12.72 seconds
Started Mar 05 02:00:11 PM PST 24
Finished Mar 05 02:00:24 PM PST 24
Peak memory 252472 kb
Host smart-e54892a7-29dd-47b2-92a8-0ca68365c4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22713
38779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2271338779
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3112593275
Short name T497
Test name
Test status
Simulation time 133794245747 ps
CPU time 3273.96 seconds
Started Mar 05 02:00:15 PM PST 24
Finished Mar 05 02:54:49 PM PST 24
Peak memory 289516 kb
Host smart-43d0b98e-fee1-47f2-8aa4-55b710187c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112593275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3112593275
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3667030578
Short name T312
Test name
Test status
Simulation time 41412712565 ps
CPU time 423.32 seconds
Started Mar 05 02:00:13 PM PST 24
Finished Mar 05 02:07:16 PM PST 24
Peak memory 247928 kb
Host smart-8e0d6967-9a99-4f03-8a26-f88d99e70009
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667030578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3667030578
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2205252543
Short name T443
Test name
Test status
Simulation time 273904192 ps
CPU time 5.28 seconds
Started Mar 05 02:00:11 PM PST 24
Finished Mar 05 02:00:17 PM PST 24
Peak memory 240780 kb
Host smart-20fbcfc8-0181-43cd-a5d4-e06339f9693f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
52543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2205252543
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3952104729
Short name T674
Test name
Test status
Simulation time 593867009 ps
CPU time 31.31 seconds
Started Mar 05 02:00:14 PM PST 24
Finished Mar 05 02:00:45 PM PST 24
Peak memory 247444 kb
Host smart-578d1d0e-0a34-4fdb-aa5a-143c6d8b6df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39521
04729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3952104729
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3615595687
Short name T201
Test name
Test status
Simulation time 265659719 ps
CPU time 19.02 seconds
Started Mar 05 02:00:16 PM PST 24
Finished Mar 05 02:00:35 PM PST 24
Peak memory 247104 kb
Host smart-f64c4c0e-0ccf-4fe5-9c4e-21811702c7f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36155
95687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3615595687
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1097088712
Short name T550
Test name
Test status
Simulation time 1615306671 ps
CPU time 22.54 seconds
Started Mar 05 02:00:13 PM PST 24
Finished Mar 05 02:00:36 PM PST 24
Peak memory 248960 kb
Host smart-e338d1e6-d5d0-4200-95c0-75e4ab84dbc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970
88712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1097088712
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.4113456877
Short name T709
Test name
Test status
Simulation time 257565411830 ps
CPU time 4940.05 seconds
Started Mar 05 02:00:14 PM PST 24
Finished Mar 05 03:22:34 PM PST 24
Peak memory 300432 kb
Host smart-3c2e59d9-baaa-4737-ab4b-72e6a8a25b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113456877 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.4113456877
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3119373635
Short name T587
Test name
Test status
Simulation time 55075805446 ps
CPU time 2443.87 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:41:05 PM PST 24
Peak memory 282504 kb
Host smart-7b2992d9-c767-4d5b-8af3-763299961a33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119373635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3119373635
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2666568491
Short name T634
Test name
Test status
Simulation time 124004910 ps
CPU time 14.82 seconds
Started Mar 05 02:00:23 PM PST 24
Finished Mar 05 02:00:38 PM PST 24
Peak memory 255584 kb
Host smart-80a69030-4a62-4ae1-a66d-8ca366e333e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26665
68491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2666568491
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.4092438482
Short name T591
Test name
Test status
Simulation time 1134623002 ps
CPU time 63.82 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:01:24 PM PST 24
Peak memory 248300 kb
Host smart-6971c8bb-d5fa-4f22-a052-21753a6f51d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40924
38482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.4092438482
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1863664141
Short name T560
Test name
Test status
Simulation time 55427795898 ps
CPU time 2042.89 seconds
Started Mar 05 02:00:19 PM PST 24
Finished Mar 05 02:34:22 PM PST 24
Peak memory 283412 kb
Host smart-ecf2e128-4ea7-4256-b0fe-90004fddc610
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863664141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1863664141
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1402963688
Short name T518
Test name
Test status
Simulation time 24070115970 ps
CPU time 1129.44 seconds
Started Mar 05 02:00:19 PM PST 24
Finished Mar 05 02:19:09 PM PST 24
Peak memory 271580 kb
Host smart-25e3bfbc-c98c-4cfc-bc0f-9b22df197fc0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402963688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1402963688
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.419077027
Short name T309
Test name
Test status
Simulation time 12758370995 ps
CPU time 516.8 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:08:57 PM PST 24
Peak memory 247716 kb
Host smart-4a7d723c-5aec-4710-8b38-2501f029a513
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419077027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.419077027
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.756349034
Short name T559
Test name
Test status
Simulation time 2229515631 ps
CPU time 31.13 seconds
Started Mar 05 02:00:16 PM PST 24
Finished Mar 05 02:00:48 PM PST 24
Peak memory 249016 kb
Host smart-7405cd64-7f47-4b46-80aa-52ae0c51345e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75634
9034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.756349034
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3997159485
Short name T570
Test name
Test status
Simulation time 1411560036 ps
CPU time 23.47 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:00:50 PM PST 24
Peak memory 247280 kb
Host smart-01328be0-3942-4b5a-8d86-d974f36d3c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39971
59485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3997159485
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.4109693844
Short name T636
Test name
Test status
Simulation time 176822714 ps
CPU time 4.36 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:00:31 PM PST 24
Peak memory 240792 kb
Host smart-24414566-6325-4fdf-a83b-75a3746a214a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
93844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4109693844
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.704625153
Short name T269
Test name
Test status
Simulation time 349408123 ps
CPU time 18.8 seconds
Started Mar 05 02:00:12 PM PST 24
Finished Mar 05 02:00:31 PM PST 24
Peak memory 248888 kb
Host smart-6a7a7186-5f73-4ee5-a9c5-8a5c169145aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70462
5153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.704625153
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1729972913
Short name T514
Test name
Test status
Simulation time 183000574547 ps
CPU time 3205.82 seconds
Started Mar 05 02:00:18 PM PST 24
Finished Mar 05 02:53:44 PM PST 24
Peak memory 301668 kb
Host smart-a3f07f3d-3c7a-4a89-ac04-0f5373d46b0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729972913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1729972913
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3003571244
Short name T276
Test name
Test status
Simulation time 36721736421 ps
CPU time 2063.38 seconds
Started Mar 05 02:00:17 PM PST 24
Finished Mar 05 02:34:41 PM PST 24
Peak memory 289656 kb
Host smart-30e7439e-63e9-4a51-804c-45ee6a8e3241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003571244 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3003571244
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1584718402
Short name T432
Test name
Test status
Simulation time 60727229934 ps
CPU time 2148.74 seconds
Started Mar 05 02:00:19 PM PST 24
Finished Mar 05 02:36:08 PM PST 24
Peak memory 289440 kb
Host smart-46756f1b-11d8-42fb-bcd6-32ec155c83e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584718402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1584718402
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3618961803
Short name T414
Test name
Test status
Simulation time 25186097740 ps
CPU time 104.63 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:02:05 PM PST 24
Peak memory 256392 kb
Host smart-d4967c5c-e566-4937-b6d7-d4a8285c8458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36189
61803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3618961803
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3382466104
Short name T643
Test name
Test status
Simulation time 1276843505 ps
CPU time 22 seconds
Started Mar 05 02:00:19 PM PST 24
Finished Mar 05 02:00:41 PM PST 24
Peak memory 254076 kb
Host smart-b9e55a09-60de-40b4-9437-dcfdd25f6ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33824
66104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3382466104
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3024187015
Short name T625
Test name
Test status
Simulation time 115169745364 ps
CPU time 1591.74 seconds
Started Mar 05 02:00:21 PM PST 24
Finished Mar 05 02:26:53 PM PST 24
Peak memory 273584 kb
Host smart-76502552-a423-4b3e-9aab-3bce19fb5357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024187015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3024187015
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.1391797590
Short name T274
Test name
Test status
Simulation time 8448164010 ps
CPU time 745.03 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:12:45 PM PST 24
Peak memory 266436 kb
Host smart-410e8c55-dde6-4ae1-94ac-97a73baa4c8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391797590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.1391797590
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1683722531
Short name T638
Test name
Test status
Simulation time 31120761001 ps
CPU time 304.11 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:05:24 PM PST 24
Peak memory 246900 kb
Host smart-dd071723-6e7b-461f-97b0-d3e36dfe3fa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683722531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1683722531
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3955800391
Short name T623
Test name
Test status
Simulation time 1487129756 ps
CPU time 24.5 seconds
Started Mar 05 02:00:18 PM PST 24
Finished Mar 05 02:00:43 PM PST 24
Peak memory 248984 kb
Host smart-f52fa0dd-cbca-441e-8654-b90342333919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
00391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3955800391
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3365776327
Short name T527
Test name
Test status
Simulation time 1750204150 ps
CPU time 41.71 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:01:07 PM PST 24
Peak memory 254600 kb
Host smart-d251446e-e509-452e-b127-a24545e18a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33657
76327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3365776327
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.172470891
Short name T366
Test name
Test status
Simulation time 261164212 ps
CPU time 24.11 seconds
Started Mar 05 02:00:23 PM PST 24
Finished Mar 05 02:00:47 PM PST 24
Peak memory 248912 kb
Host smart-c16fc084-130b-4e14-9c0f-bde2af8deac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17247
0891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.172470891
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.102964431
Short name T632
Test name
Test status
Simulation time 68175010634 ps
CPU time 1895.97 seconds
Started Mar 05 02:00:22 PM PST 24
Finished Mar 05 02:31:58 PM PST 24
Peak memory 301516 kb
Host smart-0376f2ac-93a5-4822-ace5-d16e256217d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102964431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.102964431
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2844519021
Short name T58
Test name
Test status
Simulation time 9564657192 ps
CPU time 916.59 seconds
Started Mar 05 02:00:28 PM PST 24
Finished Mar 05 02:15:45 PM PST 24
Peak memory 284376 kb
Host smart-c19e868f-7d38-4482-9149-05a66e8f961c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844519021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2844519021
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3858719441
Short name T364
Test name
Test status
Simulation time 9822292264 ps
CPU time 162.49 seconds
Started Mar 05 02:00:28 PM PST 24
Finished Mar 05 02:03:11 PM PST 24
Peak memory 256536 kb
Host smart-1e8667d0-9692-43cc-a0de-625e1114ea9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38587
19441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3858719441
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3965337835
Short name T622
Test name
Test status
Simulation time 56711267 ps
CPU time 4.09 seconds
Started Mar 05 02:00:20 PM PST 24
Finished Mar 05 02:00:24 PM PST 24
Peak memory 249704 kb
Host smart-a0a247ed-0bcc-4e95-b70d-0f1c995f195a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39653
37835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3965337835
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.825740934
Short name T695
Test name
Test status
Simulation time 16874698196 ps
CPU time 1716.46 seconds
Started Mar 05 02:00:27 PM PST 24
Finished Mar 05 02:29:04 PM PST 24
Peak memory 289100 kb
Host smart-36029d69-e415-4aa6-965c-de9301a4e0cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825740934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.825740934
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3163659313
Short name T374
Test name
Test status
Simulation time 41599427411 ps
CPU time 2737.7 seconds
Started Mar 05 02:00:27 PM PST 24
Finished Mar 05 02:46:05 PM PST 24
Peak memory 290008 kb
Host smart-7cfdb3f1-4395-4c69-9951-e83939aa8d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163659313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3163659313
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.594309559
Short name T210
Test name
Test status
Simulation time 9672556892 ps
CPU time 410.82 seconds
Started Mar 05 02:00:31 PM PST 24
Finished Mar 05 02:07:22 PM PST 24
Peak memory 247860 kb
Host smart-f4e7e934-7afb-47a1-9098-6b39727bbee8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594309559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.594309559
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2272103380
Short name T669
Test name
Test status
Simulation time 685776011 ps
CPU time 41.95 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:01:08 PM PST 24
Peak memory 255932 kb
Host smart-0f12e998-d4ad-4d04-8a48-9630b1ebe874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
03380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2272103380
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4006660133
Short name T645
Test name
Test status
Simulation time 1540776238 ps
CPU time 27.79 seconds
Started Mar 05 02:00:21 PM PST 24
Finished Mar 05 02:00:49 PM PST 24
Peak memory 255488 kb
Host smart-e4f79113-0ce5-43f4-868d-41096fdf4ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40066
60133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4006660133
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3076833036
Short name T420
Test name
Test status
Simulation time 148956623 ps
CPU time 9.33 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:00:36 PM PST 24
Peak memory 254440 kb
Host smart-f74c7ce0-bdff-4ca9-b9b1-661dfb92e687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30768
33036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3076833036
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3715075919
Short name T369
Test name
Test status
Simulation time 172409914 ps
CPU time 15.47 seconds
Started Mar 05 02:00:21 PM PST 24
Finished Mar 05 02:00:37 PM PST 24
Peak memory 248956 kb
Host smart-0a430bf2-9812-4d75-902e-b4b2e325201b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37150
75919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3715075919
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2134666240
Short name T601
Test name
Test status
Simulation time 226174802718 ps
CPU time 3555.32 seconds
Started Mar 05 02:00:28 PM PST 24
Finished Mar 05 02:59:43 PM PST 24
Peak memory 289508 kb
Host smart-78de85a8-afde-4b4e-bd82-9e959ca6360b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134666240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2134666240
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3151112000
Short name T575
Test name
Test status
Simulation time 58006548094 ps
CPU time 1411.35 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:23:58 PM PST 24
Peak memory 281632 kb
Host smart-dbffa32e-a971-4deb-a4cd-5ecd73197f2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151112000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3151112000
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2458561152
Short name T403
Test name
Test status
Simulation time 1503231319 ps
CPU time 126.3 seconds
Started Mar 05 02:00:29 PM PST 24
Finished Mar 05 02:02:35 PM PST 24
Peak memory 250008 kb
Host smart-e5580ebe-d18b-4740-bf07-3b235d8e7eaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24585
61152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2458561152
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1379381741
Short name T397
Test name
Test status
Simulation time 841134741 ps
CPU time 48.2 seconds
Started Mar 05 02:00:27 PM PST 24
Finished Mar 05 02:01:16 PM PST 24
Peak memory 255316 kb
Host smart-db4b856f-2a4f-4a46-b933-6e3039630a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13793
81741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1379381741
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2061876422
Short name T605
Test name
Test status
Simulation time 134090237939 ps
CPU time 1944.67 seconds
Started Mar 05 02:00:29 PM PST 24
Finished Mar 05 02:32:54 PM PST 24
Peak memory 273628 kb
Host smart-3f2feb36-37b3-4cb6-9cf1-16cefb3533cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061876422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2061876422
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.180288914
Short name T361
Test name
Test status
Simulation time 55023179242 ps
CPU time 1745.12 seconds
Started Mar 05 02:00:26 PM PST 24
Finished Mar 05 02:29:32 PM PST 24
Peak memory 272992 kb
Host smart-50f0de97-d025-4ecf-ae4b-9ff41603d3df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180288914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.180288914
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2831875260
Short name T568
Test name
Test status
Simulation time 32460732815 ps
CPU time 346.06 seconds
Started Mar 05 02:00:29 PM PST 24
Finished Mar 05 02:06:15 PM PST 24
Peak memory 246940 kb
Host smart-1f9378f6-396f-49e0-87cf-b15aa80a3e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831875260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2831875260
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.635666608
Short name T542
Test name
Test status
Simulation time 8147642492 ps
CPU time 31.66 seconds
Started Mar 05 02:00:28 PM PST 24
Finished Mar 05 02:01:00 PM PST 24
Peak memory 249040 kb
Host smart-cef6ef21-e9e2-433f-bce0-f1a338c71f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63566
6608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.635666608
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1250515874
Short name T459
Test name
Test status
Simulation time 558794975 ps
CPU time 37.85 seconds
Started Mar 05 02:00:28 PM PST 24
Finished Mar 05 02:01:06 PM PST 24
Peak memory 247444 kb
Host smart-8aa1ca9c-2b4f-4a21-aaa8-a8a360494e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12505
15874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1250515874
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.4173973195
Short name T708
Test name
Test status
Simulation time 760253285 ps
CPU time 43.91 seconds
Started Mar 05 02:00:29 PM PST 24
Finished Mar 05 02:01:13 PM PST 24
Peak memory 248964 kb
Host smart-0272c9da-45b6-4ded-9c69-1cad7469de69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41739
73195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.4173973195
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2376855419
Short name T525
Test name
Test status
Simulation time 555407463 ps
CPU time 46.14 seconds
Started Mar 05 02:00:38 PM PST 24
Finished Mar 05 02:01:24 PM PST 24
Peak memory 257164 kb
Host smart-7c2e74b9-670b-4364-8aa0-097747a96b21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376855419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2376855419
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1149183026
Short name T286
Test name
Test status
Simulation time 777173451598 ps
CPU time 5425.79 seconds
Started Mar 05 02:00:39 PM PST 24
Finished Mar 05 03:31:05 PM PST 24
Peak memory 314676 kb
Host smart-c55ee135-8ba3-4590-b661-54ff65868af1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149183026 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1149183026
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.974928798
Short name T223
Test name
Test status
Simulation time 151677669 ps
CPU time 3.49 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:58:05 PM PST 24
Peak memory 249152 kb
Host smart-e4ad8fd9-b52b-4ab4-a50d-1b2fc648745e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=974928798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.974928798
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2216232337
Short name T405
Test name
Test status
Simulation time 56971237270 ps
CPU time 1807.04 seconds
Started Mar 05 01:57:58 PM PST 24
Finished Mar 05 02:28:06 PM PST 24
Peak memory 281840 kb
Host smart-71231098-ece8-49ed-bed1-4155d1883158
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216232337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2216232337
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1201592930
Short name T433
Test name
Test status
Simulation time 506791226 ps
CPU time 9.53 seconds
Started Mar 05 01:57:56 PM PST 24
Finished Mar 05 01:58:06 PM PST 24
Peak memory 240788 kb
Host smart-f9217723-6830-4694-8517-77fe983d1599
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1201592930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1201592930
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2156458736
Short name T699
Test name
Test status
Simulation time 15141030732 ps
CPU time 210.63 seconds
Started Mar 05 01:57:54 PM PST 24
Finished Mar 05 02:01:26 PM PST 24
Peak memory 256184 kb
Host smart-26b326bf-ea72-4060-b1e9-6120e67fb17d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21564
58736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2156458736
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1319921143
Short name T554
Test name
Test status
Simulation time 779711295 ps
CPU time 33.86 seconds
Started Mar 05 01:57:57 PM PST 24
Finished Mar 05 01:58:31 PM PST 24
Peak memory 255304 kb
Host smart-fc480295-673a-4a37-b9e1-8a9c8f3131b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13199
21143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1319921143
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.127811864
Short name T41
Test name
Test status
Simulation time 59112624617 ps
CPU time 1771.29 seconds
Started Mar 05 01:57:58 PM PST 24
Finished Mar 05 02:27:29 PM PST 24
Peak memory 289456 kb
Host smart-2c131715-ea1c-4523-9c01-a8cc5ce036ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127811864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.127811864
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2079057449
Short name T31
Test name
Test status
Simulation time 1581789018 ps
CPU time 27.14 seconds
Started Mar 05 01:57:55 PM PST 24
Finished Mar 05 01:58:23 PM PST 24
Peak memory 249196 kb
Host smart-478132d1-65c0-4e61-ac46-5e1a4185858e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20790
57449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2079057449
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.3709285879
Short name T650
Test name
Test status
Simulation time 229419745 ps
CPU time 4.8 seconds
Started Mar 05 01:57:52 PM PST 24
Finished Mar 05 01:57:58 PM PST 24
Peak memory 238924 kb
Host smart-f20570b5-02de-48ec-9ee9-e5854a39a138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37092
85879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.3709285879
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1531056596
Short name T11
Test name
Test status
Simulation time 474547670 ps
CPU time 24.41 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:58:25 PM PST 24
Peak memory 272420 kb
Host smart-6641229a-a049-4a74-8b52-204883028e0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1531056596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1531056596
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.1342631189
Short name T450
Test name
Test status
Simulation time 133234911 ps
CPU time 8.26 seconds
Started Mar 05 01:57:54 PM PST 24
Finished Mar 05 01:58:02 PM PST 24
Peak memory 253372 kb
Host smart-1275fd39-831a-4b72-b801-0aa25f8f1563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13426
31189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.1342631189
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.470506380
Short name T375
Test name
Test status
Simulation time 3921573424 ps
CPU time 23.6 seconds
Started Mar 05 01:57:58 PM PST 24
Finished Mar 05 01:58:22 PM PST 24
Peak memory 255800 kb
Host smart-f0201457-d7c0-4ccb-aa02-360ad63229b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47050
6380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.470506380
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.352910575
Short name T206
Test name
Test status
Simulation time 244198483294 ps
CPU time 3824.47 seconds
Started Mar 05 01:57:52 PM PST 24
Finished Mar 05 03:01:37 PM PST 24
Peak memory 297880 kb
Host smart-307ac7a2-07c0-47df-a142-cfdca77f66fc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352910575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.352910575
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4259580041
Short name T285
Test name
Test status
Simulation time 455887575823 ps
CPU time 1742.16 seconds
Started Mar 05 02:00:34 PM PST 24
Finished Mar 05 02:29:36 PM PST 24
Peak memory 265432 kb
Host smart-7819579a-5008-49a7-9936-220a0e5c4edf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259580041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4259580041
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.4213546290
Short name T654
Test name
Test status
Simulation time 16678412218 ps
CPU time 156.46 seconds
Started Mar 05 02:00:36 PM PST 24
Finished Mar 05 02:03:14 PM PST 24
Peak memory 256492 kb
Host smart-b182085c-dd32-44c1-9a09-4d9693e3c032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42135
46290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.4213546290
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2280370156
Short name T647
Test name
Test status
Simulation time 354021788 ps
CPU time 22.97 seconds
Started Mar 05 02:00:36 PM PST 24
Finished Mar 05 02:01:00 PM PST 24
Peak memory 248508 kb
Host smart-a63d700f-7ff6-4513-90dd-3e9869a52cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22803
70156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2280370156
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.972393407
Short name T293
Test name
Test status
Simulation time 9020548987 ps
CPU time 881.7 seconds
Started Mar 05 02:00:42 PM PST 24
Finished Mar 05 02:15:24 PM PST 24
Peak memory 273604 kb
Host smart-1f7ee788-a047-4670-9568-0d3cdb645741
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972393407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.972393407
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3469951257
Short name T545
Test name
Test status
Simulation time 45747627782 ps
CPU time 1538.4 seconds
Started Mar 05 02:00:40 PM PST 24
Finished Mar 05 02:26:19 PM PST 24
Peak memory 272644 kb
Host smart-76ebb80c-4762-47ce-b965-316a2887319f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469951257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3469951257
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.780313437
Short name T301
Test name
Test status
Simulation time 11836159363 ps
CPU time 499.88 seconds
Started Mar 05 02:00:36 PM PST 24
Finished Mar 05 02:08:56 PM PST 24
Peak memory 247816 kb
Host smart-dd80d068-7ccf-4912-93c4-4936322da9c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780313437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.780313437
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3652507505
Short name T465
Test name
Test status
Simulation time 565628687 ps
CPU time 33.43 seconds
Started Mar 05 02:00:35 PM PST 24
Finished Mar 05 02:01:09 PM PST 24
Peak memory 256116 kb
Host smart-ead71334-b692-4233-9d57-dba131ee3027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36525
07505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3652507505
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1566730429
Short name T53
Test name
Test status
Simulation time 3227486076 ps
CPU time 54.72 seconds
Started Mar 05 02:00:34 PM PST 24
Finished Mar 05 02:01:29 PM PST 24
Peak memory 255660 kb
Host smart-b47dfaaf-9ffa-42c7-bcd5-d1b872f0d644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15667
30429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1566730429
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3017906557
Short name T202
Test name
Test status
Simulation time 1521341021 ps
CPU time 29.83 seconds
Started Mar 05 02:00:36 PM PST 24
Finished Mar 05 02:01:06 PM PST 24
Peak memory 255120 kb
Host smart-25e5e7e5-351d-45ec-a37b-b4b0ed02ae35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30179
06557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3017906557
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2950563101
Short name T82
Test name
Test status
Simulation time 789399607 ps
CPU time 51.93 seconds
Started Mar 05 02:00:33 PM PST 24
Finished Mar 05 02:01:26 PM PST 24
Peak memory 248980 kb
Host smart-ad6bd531-b320-4c5c-bfc7-113bc0bbdce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29505
63101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2950563101
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.540876871
Short name T183
Test name
Test status
Simulation time 156041221880 ps
CPU time 3019.08 seconds
Started Mar 05 02:00:41 PM PST 24
Finished Mar 05 02:51:00 PM PST 24
Peak memory 289444 kb
Host smart-0f27b932-cbab-4d58-9f17-b5f99926fbdd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540876871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.540876871
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.116713302
Short name T531
Test name
Test status
Simulation time 286273571593 ps
CPU time 7398.88 seconds
Started Mar 05 02:00:43 PM PST 24
Finished Mar 05 04:04:02 PM PST 24
Peak memory 395552 kb
Host smart-ca39b387-ebe6-4601-a2fa-b8d5502c87bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116713302 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.116713302
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2736501208
Short name T108
Test name
Test status
Simulation time 25529273460 ps
CPU time 1645.48 seconds
Started Mar 05 02:00:43 PM PST 24
Finished Mar 05 02:28:09 PM PST 24
Peak memory 273556 kb
Host smart-c529fc97-148a-4abf-b175-c34282620738
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736501208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2736501208
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3988134789
Short name T284
Test name
Test status
Simulation time 2242330951 ps
CPU time 88.46 seconds
Started Mar 05 02:00:42 PM PST 24
Finished Mar 05 02:02:10 PM PST 24
Peak memory 256756 kb
Host smart-5c9b904e-bda5-4ab5-af13-c33fdf7a200a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39881
34789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3988134789
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2497111379
Short name T615
Test name
Test status
Simulation time 213897275 ps
CPU time 21.23 seconds
Started Mar 05 02:00:41 PM PST 24
Finished Mar 05 02:01:03 PM PST 24
Peak memory 248480 kb
Host smart-470ab73a-0c52-481a-9b4d-2b40163502e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24971
11379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2497111379
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.2440947193
Short name T280
Test name
Test status
Simulation time 118395075539 ps
CPU time 2051.01 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:35:04 PM PST 24
Peak memory 273076 kb
Host smart-a678192c-ae28-4da4-ac82-f5eb1db4ad5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440947193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.2440947193
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.687300102
Short name T535
Test name
Test status
Simulation time 267233030812 ps
CPU time 2917.66 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:49:31 PM PST 24
Peak memory 289348 kb
Host smart-ca483b6d-1c17-4abb-855f-3aa427cc34f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687300102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.687300102
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.180902780
Short name T299
Test name
Test status
Simulation time 8425457170 ps
CPU time 362.98 seconds
Started Mar 05 02:00:54 PM PST 24
Finished Mar 05 02:06:57 PM PST 24
Peak memory 246700 kb
Host smart-9d064409-e9df-478a-bb27-f9b23b24a37e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180902780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.180902780
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.803308987
Short name T481
Test name
Test status
Simulation time 546126603 ps
CPU time 13.57 seconds
Started Mar 05 02:00:45 PM PST 24
Finished Mar 05 02:00:58 PM PST 24
Peak memory 248980 kb
Host smart-d7d90fab-4ae3-40b5-9c9a-85b1228b2062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80330
8987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.803308987
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1427279144
Short name T477
Test name
Test status
Simulation time 310973816 ps
CPU time 22.84 seconds
Started Mar 05 02:00:42 PM PST 24
Finished Mar 05 02:01:05 PM PST 24
Peak memory 254084 kb
Host smart-77326cfc-3a10-4fed-9ed9-af6d970eaf90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
79144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1427279144
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4249193073
Short name T556
Test name
Test status
Simulation time 745137078 ps
CPU time 55.22 seconds
Started Mar 05 02:00:44 PM PST 24
Finished Mar 05 02:01:40 PM PST 24
Peak memory 255224 kb
Host smart-4441ee16-5948-480f-821d-cfdf31f8135f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42491
93073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4249193073
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2467448579
Short name T593
Test name
Test status
Simulation time 615223385 ps
CPU time 16.89 seconds
Started Mar 05 02:00:40 PM PST 24
Finished Mar 05 02:00:57 PM PST 24
Peak memory 248984 kb
Host smart-b742d35f-ec99-4600-bf6d-a785816364be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24674
48579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2467448579
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1334915952
Short name T407
Test name
Test status
Simulation time 8794439203 ps
CPU time 46.24 seconds
Started Mar 05 02:00:53 PM PST 24
Finished Mar 05 02:01:39 PM PST 24
Peak memory 255328 kb
Host smart-55ad0270-11ac-4ee7-b7d4-3847fc018244
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334915952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1334915952
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1998494112
Short name T40
Test name
Test status
Simulation time 16509461039 ps
CPU time 1086.31 seconds
Started Mar 05 02:00:53 PM PST 24
Finished Mar 05 02:18:59 PM PST 24
Peak memory 271204 kb
Host smart-2bd112e8-6669-49fe-8567-aee8511aba15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998494112 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1998494112
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3072094458
Short name T460
Test name
Test status
Simulation time 248283747108 ps
CPU time 2779.78 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:47:12 PM PST 24
Peak memory 289084 kb
Host smart-b2c87bdc-9e72-49ec-bae3-1adc3b5313cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072094458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3072094458
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1265091434
Short name T584
Test name
Test status
Simulation time 6553213435 ps
CPU time 131.33 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:03:04 PM PST 24
Peak memory 256524 kb
Host smart-5cd2259e-e874-40ec-a551-03bfd09323f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12650
91434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1265091434
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.610648449
Short name T73
Test name
Test status
Simulation time 953874191 ps
CPU time 65.1 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:01:58 PM PST 24
Peak memory 254668 kb
Host smart-da7c64ab-4c59-4d0a-bd89-6f29b6a19219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61064
8449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.610648449
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.916608973
Short name T664
Test name
Test status
Simulation time 57267893827 ps
CPU time 3400.5 seconds
Started Mar 05 02:00:54 PM PST 24
Finished Mar 05 02:57:35 PM PST 24
Peak memory 288948 kb
Host smart-22aef4ab-14a3-4ee8-b52d-01754a9718d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916608973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.916608973
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2807037580
Short name T624
Test name
Test status
Simulation time 100737079517 ps
CPU time 3110.08 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:52:43 PM PST 24
Peak memory 289280 kb
Host smart-a6f3f7b3-a19c-46cf-9c3f-c8ced377fae4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807037580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2807037580
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.4197425028
Short name T458
Test name
Test status
Simulation time 4769832248 ps
CPU time 60.38 seconds
Started Mar 05 02:00:51 PM PST 24
Finished Mar 05 02:01:51 PM PST 24
Peak memory 247852 kb
Host smart-97502393-4a46-4a08-92a9-b4e0244e042d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197425028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.4197425028
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2328388664
Short name T383
Test name
Test status
Simulation time 1832183829 ps
CPU time 74.77 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:02:07 PM PST 24
Peak memory 248956 kb
Host smart-cbe3f0d2-bfe2-4a91-94e4-89ce2e695737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23283
88664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2328388664
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2398145918
Short name T398
Test name
Test status
Simulation time 365520428 ps
CPU time 27.75 seconds
Started Mar 05 02:00:52 PM PST 24
Finished Mar 05 02:01:21 PM PST 24
Peak memory 255016 kb
Host smart-92c2e299-b6e2-4474-a232-cdd7a93b094b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23981
45918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2398145918
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3861614124
Short name T501
Test name
Test status
Simulation time 1258463927 ps
CPU time 38.34 seconds
Started Mar 05 02:00:53 PM PST 24
Finished Mar 05 02:01:31 PM PST 24
Peak memory 254372 kb
Host smart-ef7dbe1a-3048-45e5-9a6b-7c9036258aef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38616
14124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3861614124
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.372919818
Short name T362
Test name
Test status
Simulation time 2038062433 ps
CPU time 32.02 seconds
Started Mar 05 02:00:55 PM PST 24
Finished Mar 05 02:01:27 PM PST 24
Peak memory 248980 kb
Host smart-043a029b-45c0-4b45-9813-91259250c854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37291
9818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.372919818
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1642434053
Short name T102
Test name
Test status
Simulation time 6608849185 ps
CPU time 311.07 seconds
Started Mar 05 02:00:54 PM PST 24
Finished Mar 05 02:06:06 PM PST 24
Peak memory 255220 kb
Host smart-459243f8-eed2-44fa-97e2-0893d6e95322
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642434053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1642434053
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.815030815
Short name T186
Test name
Test status
Simulation time 57301448588 ps
CPU time 2869.12 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:48:55 PM PST 24
Peak memory 305484 kb
Host smart-60d42bad-79e7-4fdf-abcb-e5c15e3b9c37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815030815 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.815030815
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.474195899
Short name T586
Test name
Test status
Simulation time 271640001 ps
CPU time 18 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:22 PM PST 24
Peak memory 248672 kb
Host smart-dadc2b52-227d-455c-98bf-ce3de267a3df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47419
5899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.474195899
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1922250014
Short name T261
Test name
Test status
Simulation time 797691907 ps
CPU time 44.5 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:01:52 PM PST 24
Peak memory 255696 kb
Host smart-cd066366-53f5-430d-8ba2-c62d88ecafe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19222
50014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1922250014
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2009670725
Short name T598
Test name
Test status
Simulation time 59381837712 ps
CPU time 2197.35 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:37:44 PM PST 24
Peak memory 281552 kb
Host smart-b7d9d220-42f8-45ca-aa7d-c9cf16829b4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009670725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2009670725
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2162581471
Short name T84
Test name
Test status
Simulation time 164094393979 ps
CPU time 2959.92 seconds
Started Mar 05 02:01:06 PM PST 24
Finished Mar 05 02:50:28 PM PST 24
Peak memory 289944 kb
Host smart-e3378281-d313-4c4b-b87a-ec36fd2d5a41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162581471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2162581471
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.473323457
Short name T314
Test name
Test status
Simulation time 6519123132 ps
CPU time 284.71 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:05:52 PM PST 24
Peak memory 247848 kb
Host smart-1344adb3-ac25-4bbb-8d67-4b9394594fd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473323457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.473323457
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2012986145
Short name T270
Test name
Test status
Simulation time 3079292894 ps
CPU time 50.73 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:55 PM PST 24
Peak memory 249044 kb
Host smart-70b99af7-4df0-4ab3-9943-8726a51d2621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
86145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2012986145
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1556676917
Short name T478
Test name
Test status
Simulation time 375128746 ps
CPU time 8.46 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:13 PM PST 24
Peak memory 247304 kb
Host smart-ca06ea9d-6ea9-4f9c-85b8-d05e8341568d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15566
76917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1556676917
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2207319243
Short name T20
Test name
Test status
Simulation time 431299355 ps
CPU time 34.2 seconds
Started Mar 05 02:01:06 PM PST 24
Finished Mar 05 02:01:42 PM PST 24
Peak memory 255212 kb
Host smart-f86a361b-73f4-462b-a6da-5b9df379a55f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22073
19243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2207319243
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3138899562
Short name T676
Test name
Test status
Simulation time 416252009 ps
CPU time 31.18 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:01:38 PM PST 24
Peak memory 248688 kb
Host smart-3c913cd9-b8e3-4f37-8e0a-1ef9d0ff4b57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31388
99562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3138899562
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2860158980
Short name T263
Test name
Test status
Simulation time 163570764757 ps
CPU time 3109.85 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:52:57 PM PST 24
Peak memory 306160 kb
Host smart-e60e7e2f-5686-437f-b777-881f34dd5021
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860158980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2860158980
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.826841820
Short name T235
Test name
Test status
Simulation time 32902131501 ps
CPU time 985.24 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:17:32 PM PST 24
Peak memory 272672 kb
Host smart-3346ebad-c749-4642-ac41-d5615d2c6f78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826841820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.826841820
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2633391395
Short name T357
Test name
Test status
Simulation time 2452082043 ps
CPU time 161.61 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:03:49 PM PST 24
Peak memory 256788 kb
Host smart-733f56e6-8e8c-4091-966b-036ec33132fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26333
91395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2633391395
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4204627564
Short name T547
Test name
Test status
Simulation time 936418066 ps
CPU time 37.04 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:01:45 PM PST 24
Peak memory 254588 kb
Host smart-df12d657-5ce1-4a43-bc10-9b4aac2defcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42046
27564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4204627564
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2715980216
Short name T333
Test name
Test status
Simulation time 97390747240 ps
CPU time 2672.25 seconds
Started Mar 05 02:01:03 PM PST 24
Finished Mar 05 02:45:36 PM PST 24
Peak memory 289552 kb
Host smart-7b9736c2-4912-4d25-a9c9-4ef2e40f2747
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715980216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2715980216
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1368061713
Short name T520
Test name
Test status
Simulation time 184392758736 ps
CPU time 3043.36 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:51:59 PM PST 24
Peak memory 289352 kb
Host smart-9ee55254-bf23-4959-b824-4f23ef13ca70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368061713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1368061713
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2649094827
Short name T1
Test name
Test status
Simulation time 20397862984 ps
CPU time 243.99 seconds
Started Mar 05 02:01:05 PM PST 24
Finished Mar 05 02:05:10 PM PST 24
Peak memory 247936 kb
Host smart-e4534b2b-2c74-4fc1-b198-7deda3a54848
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649094827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2649094827
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3445492246
Short name T672
Test name
Test status
Simulation time 1275159397 ps
CPU time 21.3 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:28 PM PST 24
Peak memory 257156 kb
Host smart-ebc14509-ed12-4d5d-900f-90c45fcc1377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
92246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3445492246
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1848152322
Short name T182
Test name
Test status
Simulation time 921485526 ps
CPU time 30.59 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:36 PM PST 24
Peak memory 254800 kb
Host smart-a7614f10-819e-40ac-9986-73760729cc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18481
52322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1848152322
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2785881505
Short name T248
Test name
Test status
Simulation time 198587590 ps
CPU time 23.66 seconds
Started Mar 05 02:01:04 PM PST 24
Finished Mar 05 02:01:29 PM PST 24
Peak memory 247088 kb
Host smart-27093f16-9b73-4bdd-928f-4751d5633d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27858
81505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2785881505
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.650407111
Short name T504
Test name
Test status
Simulation time 7028674839 ps
CPU time 73.19 seconds
Started Mar 05 02:01:06 PM PST 24
Finished Mar 05 02:02:21 PM PST 24
Peak memory 256164 kb
Host smart-3ff6f8eb-b6f0-4427-a03f-4893cc573fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65040
7111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.650407111
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3269409342
Short name T253
Test name
Test status
Simulation time 47662711894 ps
CPU time 2833.43 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:48:30 PM PST 24
Peak memory 281820 kb
Host smart-6282237a-0953-4508-ab9f-72a8d806d0e9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269409342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3269409342
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2933114780
Short name T111
Test name
Test status
Simulation time 10605910451 ps
CPU time 1227.33 seconds
Started Mar 05 02:01:22 PM PST 24
Finished Mar 05 02:21:50 PM PST 24
Peak memory 289564 kb
Host smart-f0efe3a4-efce-4591-a871-7221863de907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933114780 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2933114780
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2129780917
Short name T523
Test name
Test status
Simulation time 29421616196 ps
CPU time 1900.29 seconds
Started Mar 05 02:01:18 PM PST 24
Finished Mar 05 02:32:59 PM PST 24
Peak memory 286548 kb
Host smart-a360e8f1-413e-4c78-aba8-d67cb53f9861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129780917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2129780917
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1689628879
Short name T418
Test name
Test status
Simulation time 1502170927 ps
CPU time 128.67 seconds
Started Mar 05 02:01:22 PM PST 24
Finished Mar 05 02:03:30 PM PST 24
Peak memory 256824 kb
Host smart-7a4d42a1-1679-4795-a7ed-77c053e06de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
28879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1689628879
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2816331999
Short name T386
Test name
Test status
Simulation time 213820140 ps
CPU time 15.36 seconds
Started Mar 05 02:01:15 PM PST 24
Finished Mar 05 02:01:31 PM PST 24
Peak memory 254432 kb
Host smart-b736ca3c-42df-459f-bc24-e19d709e5c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28163
31999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2816331999
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.157924068
Short name T335
Test name
Test status
Simulation time 48854077486 ps
CPU time 1051.92 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:18:48 PM PST 24
Peak memory 289196 kb
Host smart-d64c0b08-56d8-481c-a09f-23da686ee7a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157924068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.157924068
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.859163947
Short name T613
Test name
Test status
Simulation time 26894821666 ps
CPU time 1260.66 seconds
Started Mar 05 02:01:18 PM PST 24
Finished Mar 05 02:22:18 PM PST 24
Peak memory 273480 kb
Host smart-b8c59dc7-75a0-4608-9cec-23f1cf38507a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859163947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.859163947
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1492687040
Short name T324
Test name
Test status
Simulation time 40527045806 ps
CPU time 422.96 seconds
Started Mar 05 02:01:19 PM PST 24
Finished Mar 05 02:08:22 PM PST 24
Peak memory 247944 kb
Host smart-ea02b20f-f502-425c-ba2c-a61c3b561fd4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492687040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1492687040
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1113884514
Short name T367
Test name
Test status
Simulation time 1328583663 ps
CPU time 69.61 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:02:26 PM PST 24
Peak memory 248976 kb
Host smart-dd208ced-25de-4290-8633-3eb0b0b05964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
84514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1113884514
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1629483228
Short name T483
Test name
Test status
Simulation time 520235291 ps
CPU time 27.49 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:01:43 PM PST 24
Peak memory 247428 kb
Host smart-a83756d2-5fc3-412d-bc4f-669e81a48d8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
83228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1629483228
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1440869564
Short name T107
Test name
Test status
Simulation time 467047759 ps
CPU time 14.5 seconds
Started Mar 05 02:01:19 PM PST 24
Finished Mar 05 02:01:33 PM PST 24
Peak memory 255028 kb
Host smart-257fc6f5-cd6a-43ec-930b-1a89f57905c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
69564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1440869564
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1199917661
Short name T415
Test name
Test status
Simulation time 479036292 ps
CPU time 33.46 seconds
Started Mar 05 02:01:17 PM PST 24
Finished Mar 05 02:01:51 PM PST 24
Peak memory 256020 kb
Host smart-ecfab2bf-e209-4466-9ad1-912bdfa285d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11999
17661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1199917661
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.210102840
Short name T55
Test name
Test status
Simulation time 38102488108 ps
CPU time 1365.49 seconds
Started Mar 05 02:01:17 PM PST 24
Finished Mar 05 02:24:03 PM PST 24
Peak memory 289988 kb
Host smart-8377f837-d90a-4ddf-a62f-c15853ce010b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210102840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.210102840
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1411761603
Short name T393
Test name
Test status
Simulation time 52341640195 ps
CPU time 3090.52 seconds
Started Mar 05 02:01:17 PM PST 24
Finished Mar 05 02:52:48 PM PST 24
Peak memory 289944 kb
Host smart-b49f57d8-4690-41bd-9e61-05b5505ed0b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411761603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1411761603
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1114034405
Short name T65
Test name
Test status
Simulation time 5113873294 ps
CPU time 79.33 seconds
Started Mar 05 02:01:22 PM PST 24
Finished Mar 05 02:02:41 PM PST 24
Peak memory 256312 kb
Host smart-454811ae-f73f-4a32-95de-a8f6bb189b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11140
34405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1114034405
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3786756252
Short name T649
Test name
Test status
Simulation time 2252317738 ps
CPU time 68.08 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:02:25 PM PST 24
Peak memory 254744 kb
Host smart-dfba8465-8246-4876-8c1a-b1c851c5725e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
56252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3786756252
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3912500902
Short name T334
Test name
Test status
Simulation time 86335184792 ps
CPU time 2496.38 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:43:01 PM PST 24
Peak memory 289236 kb
Host smart-202f4a24-d97f-4da9-82c0-9296e7ce9772
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912500902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3912500902
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2836042841
Short name T279
Test name
Test status
Simulation time 176964208807 ps
CPU time 2723.34 seconds
Started Mar 05 02:01:35 PM PST 24
Finished Mar 05 02:46:59 PM PST 24
Peak memory 287852 kb
Host smart-0c64d18b-584a-40f3-8807-ab02c3c94810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836042841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2836042841
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3252816769
Short name T297
Test name
Test status
Simulation time 56733454528 ps
CPU time 653.59 seconds
Started Mar 05 02:01:22 PM PST 24
Finished Mar 05 02:12:16 PM PST 24
Peak memory 247948 kb
Host smart-5986a4a9-4628-4011-aaa4-aff9204668e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252816769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3252816769
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.201669506
Short name T697
Test name
Test status
Simulation time 587494732 ps
CPU time 25.9 seconds
Started Mar 05 02:01:15 PM PST 24
Finished Mar 05 02:01:41 PM PST 24
Peak memory 249140 kb
Host smart-8b814bf2-21be-4cac-a162-fe51d70eeba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20166
9506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.201669506
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2388389219
Short name T609
Test name
Test status
Simulation time 3771221692 ps
CPU time 35.78 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:01:52 PM PST 24
Peak memory 247652 kb
Host smart-87a12da7-7db9-4320-8378-e0cd1b9f8ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
89219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2388389219
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3236557766
Short name T430
Test name
Test status
Simulation time 632826843 ps
CPU time 39.77 seconds
Started Mar 05 02:01:15 PM PST 24
Finished Mar 05 02:01:55 PM PST 24
Peak memory 255432 kb
Host smart-b7780328-7c65-4aac-9544-5294968a7799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32365
57766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3236557766
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2788652890
Short name T499
Test name
Test status
Simulation time 17753189 ps
CPU time 3.69 seconds
Started Mar 05 02:01:16 PM PST 24
Finished Mar 05 02:01:19 PM PST 24
Peak memory 240780 kb
Host smart-6894dda4-f283-4e20-8914-44b42ff1ae89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27886
52890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2788652890
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.664369109
Short name T657
Test name
Test status
Simulation time 196101616110 ps
CPU time 2947.7 seconds
Started Mar 05 02:01:25 PM PST 24
Finished Mar 05 02:50:33 PM PST 24
Peak memory 286676 kb
Host smart-91df379d-a36c-455b-bec9-dfbbddae1c5f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664369109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.664369109
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.403925788
Short name T421
Test name
Test status
Simulation time 87707938476 ps
CPU time 2643.88 seconds
Started Mar 05 02:01:25 PM PST 24
Finished Mar 05 02:45:30 PM PST 24
Peak memory 286336 kb
Host smart-9724a57a-444c-4882-9688-185acf37cb7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403925788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.403925788
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1452265033
Short name T618
Test name
Test status
Simulation time 1384409930 ps
CPU time 117.6 seconds
Started Mar 05 02:01:26 PM PST 24
Finished Mar 05 02:03:24 PM PST 24
Peak memory 256536 kb
Host smart-b1d86b70-1a53-464f-9499-707e78f52239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14522
65033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1452265033
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.707162100
Short name T64
Test name
Test status
Simulation time 49498649 ps
CPU time 3.39 seconds
Started Mar 05 02:01:25 PM PST 24
Finished Mar 05 02:01:28 PM PST 24
Peak memory 239068 kb
Host smart-fc9c169f-b200-4563-a757-0f15341bb503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70716
2100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.707162100
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.302001490
Short name T318
Test name
Test status
Simulation time 46689860969 ps
CPU time 3063.56 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:52:28 PM PST 24
Peak memory 289220 kb
Host smart-54573e9a-d96a-4f1e-86ad-609df0783fb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302001490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.302001490
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3150110922
Short name T417
Test name
Test status
Simulation time 24285017403 ps
CPU time 1403.24 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:24:48 PM PST 24
Peak memory 265420 kb
Host smart-49045299-a052-4a76-820c-839e9d47eb2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150110922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3150110922
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2404829645
Short name T644
Test name
Test status
Simulation time 217596136 ps
CPU time 5.96 seconds
Started Mar 05 02:01:27 PM PST 24
Finished Mar 05 02:01:34 PM PST 24
Peak memory 248996 kb
Host smart-a6b3fc6b-7943-4963-b1a6-371f97f50cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
29645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2404829645
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.250690877
Short name T427
Test name
Test status
Simulation time 1702538053 ps
CPU time 26.28 seconds
Started Mar 05 02:01:26 PM PST 24
Finished Mar 05 02:01:52 PM PST 24
Peak memory 255264 kb
Host smart-81c528d0-1ce3-4366-b7ff-01c8e6b674e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25069
0877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.250690877
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.854989317
Short name T500
Test name
Test status
Simulation time 211350180 ps
CPU time 18.77 seconds
Started Mar 05 02:01:23 PM PST 24
Finished Mar 05 02:01:42 PM PST 24
Peak memory 248996 kb
Host smart-1d5f10be-2d27-44c1-a76a-7594a76dd4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85498
9317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.854989317
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3225334915
Short name T359
Test name
Test status
Simulation time 454912940 ps
CPU time 22.61 seconds
Started Mar 05 02:01:26 PM PST 24
Finished Mar 05 02:01:49 PM PST 24
Peak memory 249104 kb
Host smart-c26a3591-939f-40d9-a4f2-84a809e7577f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253
34915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3225334915
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1124891448
Short name T184
Test name
Test status
Simulation time 168254292252 ps
CPU time 2330.47 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:40:15 PM PST 24
Peak memory 283740 kb
Host smart-496a9d88-d205-4d34-afb9-1731c3eb9b89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124891448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1124891448
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2177016145
Short name T2
Test name
Test status
Simulation time 322403906 ps
CPU time 20.29 seconds
Started Mar 05 02:01:26 PM PST 24
Finished Mar 05 02:01:46 PM PST 24
Peak memory 255912 kb
Host smart-eb546705-4207-45df-bd30-d28034d30596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21770
16145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2177016145
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3666158727
Short name T534
Test name
Test status
Simulation time 1049486273 ps
CPU time 14.73 seconds
Started Mar 05 02:01:25 PM PST 24
Finished Mar 05 02:01:40 PM PST 24
Peak memory 252312 kb
Host smart-9f17e091-19f5-445b-a9e3-ad59caa7722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36661
58727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3666158727
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.919621950
Short name T539
Test name
Test status
Simulation time 138206778841 ps
CPU time 2037.79 seconds
Started Mar 05 02:01:23 PM PST 24
Finished Mar 05 02:35:21 PM PST 24
Peak memory 273160 kb
Host smart-3e904490-802b-4608-90cb-06daf75cc620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919621950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.919621950
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1696203508
Short name T39
Test name
Test status
Simulation time 12963895042 ps
CPU time 1421.69 seconds
Started Mar 05 02:01:36 PM PST 24
Finished Mar 05 02:25:18 PM PST 24
Peak memory 289536 kb
Host smart-ddfb6a34-9705-4e44-b3a1-dea5e13dc469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696203508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1696203508
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2217304646
Short name T325
Test name
Test status
Simulation time 50690488407 ps
CPU time 586.55 seconds
Started Mar 05 02:01:23 PM PST 24
Finished Mar 05 02:11:10 PM PST 24
Peak memory 247644 kb
Host smart-2511d3f7-3579-4382-b9eb-a8cade92e62e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217304646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2217304646
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3301982708
Short name T511
Test name
Test status
Simulation time 3304768916 ps
CPU time 40.55 seconds
Started Mar 05 02:01:23 PM PST 24
Finished Mar 05 02:02:04 PM PST 24
Peak memory 249040 kb
Host smart-ab79471f-ca20-4105-8d59-ccc8f0f17630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33019
82708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3301982708
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3019979611
Short name T552
Test name
Test status
Simulation time 333878365 ps
CPU time 4.87 seconds
Started Mar 05 02:01:25 PM PST 24
Finished Mar 05 02:01:30 PM PST 24
Peak memory 238864 kb
Host smart-3a3af7bd-edcd-4682-a066-5d7f81d1629a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30199
79611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3019979611
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1126461544
Short name T423
Test name
Test status
Simulation time 571237016 ps
CPU time 29.29 seconds
Started Mar 05 02:01:27 PM PST 24
Finished Mar 05 02:01:57 PM PST 24
Peak memory 254692 kb
Host smart-a8a897f5-299b-47fd-86e0-33b9c40f1d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11264
61544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1126461544
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1299713831
Short name T180
Test name
Test status
Simulation time 15517177312 ps
CPU time 56.35 seconds
Started Mar 05 02:01:24 PM PST 24
Finished Mar 05 02:02:21 PM PST 24
Peak memory 248956 kb
Host smart-58aa4156-a25d-44ab-92af-9bd8380d5b3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12997
13831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1299713831
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.2306753910
Short name T707
Test name
Test status
Simulation time 7709915049 ps
CPU time 522.65 seconds
Started Mar 05 02:01:36 PM PST 24
Finished Mar 05 02:10:19 PM PST 24
Peak memory 257240 kb
Host smart-829f1126-b401-4eae-894c-c75cee6ad84c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306753910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.2306753910
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3462994826
Short name T496
Test name
Test status
Simulation time 69221074932 ps
CPU time 1471.75 seconds
Started Mar 05 02:01:38 PM PST 24
Finished Mar 05 02:26:10 PM PST 24
Peak memory 273240 kb
Host smart-b0cfb05c-e876-4119-bb67-928cff7868c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462994826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3462994826
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2403205436
Short name T693
Test name
Test status
Simulation time 10842736904 ps
CPU time 192.87 seconds
Started Mar 05 02:01:35 PM PST 24
Finished Mar 05 02:04:48 PM PST 24
Peak memory 256524 kb
Host smart-6e800995-2073-4286-ad22-f99b76056c1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24032
05436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2403205436
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1628474536
Short name T38
Test name
Test status
Simulation time 736159766 ps
CPU time 49.93 seconds
Started Mar 05 02:01:35 PM PST 24
Finished Mar 05 02:02:25 PM PST 24
Peak memory 247820 kb
Host smart-d99a9e3a-e26a-44b3-b59b-f3f86674e9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16284
74536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1628474536
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2722358978
Short name T272
Test name
Test status
Simulation time 111836704469 ps
CPU time 1675.64 seconds
Started Mar 05 02:01:36 PM PST 24
Finished Mar 05 02:29:32 PM PST 24
Peak memory 272848 kb
Host smart-e033bf82-e0c4-44af-8733-873d7cd9a1b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722358978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2722358978
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2948022361
Short name T599
Test name
Test status
Simulation time 27448315064 ps
CPU time 1624.88 seconds
Started Mar 05 02:01:34 PM PST 24
Finished Mar 05 02:28:39 PM PST 24
Peak memory 273148 kb
Host smart-840615c0-f468-494c-b5ea-b61a05b950a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948022361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2948022361
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.768629142
Short name T326
Test name
Test status
Simulation time 8911654709 ps
CPU time 378.07 seconds
Started Mar 05 02:01:37 PM PST 24
Finished Mar 05 02:07:55 PM PST 24
Peak memory 247808 kb
Host smart-4ac67f8d-025d-422e-8247-5dd81bb7bba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768629142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.768629142
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1960672915
Short name T594
Test name
Test status
Simulation time 3450484885 ps
CPU time 50.4 seconds
Started Mar 05 02:01:34 PM PST 24
Finished Mar 05 02:02:25 PM PST 24
Peak memory 249008 kb
Host smart-327565e9-db67-48c4-8e39-1c9811e88f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606
72915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1960672915
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.798709550
Short name T60
Test name
Test status
Simulation time 684623372 ps
CPU time 41.02 seconds
Started Mar 05 02:01:34 PM PST 24
Finished Mar 05 02:02:15 PM PST 24
Peak memory 247452 kb
Host smart-159212fd-a240-4958-a4e6-69b8c0f0f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79870
9550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.798709550
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.42605816
Short name T665
Test name
Test status
Simulation time 3579784404 ps
CPU time 34.46 seconds
Started Mar 05 02:01:35 PM PST 24
Finished Mar 05 02:02:10 PM PST 24
Peak memory 255508 kb
Host smart-0545b58f-3e72-44de-b660-b91dc17f977e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605
816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.42605816
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2570327378
Short name T26
Test name
Test status
Simulation time 790389918 ps
CPU time 35.19 seconds
Started Mar 05 02:01:35 PM PST 24
Finished Mar 05 02:02:10 PM PST 24
Peak memory 248980 kb
Host smart-ad133fb5-c19d-47a0-ab16-692d297aec7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25703
27378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2570327378
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3292021770
Short name T434
Test name
Test status
Simulation time 3803929761 ps
CPU time 133.85 seconds
Started Mar 05 02:01:44 PM PST 24
Finished Mar 05 02:03:58 PM PST 24
Peak memory 255976 kb
Host smart-ac77f1d6-8d02-4014-b12e-21b785b137e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292021770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3292021770
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3149733229
Short name T200
Test name
Test status
Simulation time 305315178742 ps
CPU time 8437.92 seconds
Started Mar 05 02:01:42 PM PST 24
Finished Mar 05 04:22:21 PM PST 24
Peak memory 368224 kb
Host smart-25b134e4-c382-46fa-a6aa-04aed7ef29cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149733229 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3149733229
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3833523068
Short name T215
Test name
Test status
Simulation time 29226949 ps
CPU time 3.09 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:58:05 PM PST 24
Peak memory 249152 kb
Host smart-043688c4-ac0c-424c-9f0b-c75d8e9eaebb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3833523068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3833523068
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2483475392
Short name T387
Test name
Test status
Simulation time 40264226723 ps
CPU time 2755.39 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 02:43:57 PM PST 24
Peak memory 281356 kb
Host smart-1a843045-2ee1-44f0-92fb-d0e2b07d99df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483475392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2483475392
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1070648814
Short name T36
Test name
Test status
Simulation time 1449640450 ps
CPU time 60.82 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:59:02 PM PST 24
Peak memory 240756 kb
Host smart-ddcdbda4-ea14-4c3f-9c5a-6720cab83c0f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1070648814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1070648814
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.83843089
Short name T512
Test name
Test status
Simulation time 9548703565 ps
CPU time 92.82 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:59:34 PM PST 24
Peak memory 257124 kb
Host smart-1770e011-0b8e-4a8f-b4d9-00f59c29bfa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83843
089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.83843089
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3587498167
Short name T396
Test name
Test status
Simulation time 64258300 ps
CPU time 5.09 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:58:15 PM PST 24
Peak memory 238988 kb
Host smart-c34705b4-fe18-4f3e-b10b-b87bc0eace4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
98167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3587498167
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.142943186
Short name T513
Test name
Test status
Simulation time 45355599570 ps
CPU time 1218.77 seconds
Started Mar 05 01:58:02 PM PST 24
Finished Mar 05 02:18:22 PM PST 24
Peak memory 285312 kb
Host smart-e9b8761e-6778-41bc-bcf9-4d5986f3e3dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142943186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.142943186
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.945348990
Short name T275
Test name
Test status
Simulation time 31745194455 ps
CPU time 718.36 seconds
Started Mar 05 01:58:00 PM PST 24
Finished Mar 05 02:09:59 PM PST 24
Peak memory 265464 kb
Host smart-e072523d-91cf-43ae-86ed-550a29aaca3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945348990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.945348990
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3122466613
Short name T688
Test name
Test status
Simulation time 9726173018 ps
CPU time 201.49 seconds
Started Mar 05 01:58:03 PM PST 24
Finished Mar 05 02:01:24 PM PST 24
Peak memory 247712 kb
Host smart-2adc2b1e-41df-41ae-8797-4e876d7f7286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122466613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3122466613
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3424724717
Short name T577
Test name
Test status
Simulation time 571581231 ps
CPU time 13.92 seconds
Started Mar 05 01:58:01 PM PST 24
Finished Mar 05 01:58:15 PM PST 24
Peak memory 254896 kb
Host smart-dbf4f304-de5a-45d3-9e47-b0c9b61ed210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34247
24717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3424724717
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1066126904
Short name T56
Test name
Test status
Simulation time 1035073912 ps
CPU time 60 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:59:10 PM PST 24
Peak memory 247720 kb
Host smart-4d0e01d8-00cb-4391-9452-f2d6f5de366b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10661
26904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1066126904
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2320516095
Short name T49
Test name
Test status
Simulation time 580556142 ps
CPU time 33.97 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:58:44 PM PST 24
Peak memory 255532 kb
Host smart-6c263b0f-d271-4364-9a46-dc81b8b76eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23205
16095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2320516095
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.1990405475
Short name T482
Test name
Test status
Simulation time 928512531 ps
CPU time 32.39 seconds
Started Mar 05 01:58:02 PM PST 24
Finished Mar 05 01:58:35 PM PST 24
Peak memory 248980 kb
Host smart-4727b352-d6e9-4366-a13c-8b9b45c7c560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
05475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.1990405475
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1833034134
Short name T92
Test name
Test status
Simulation time 27940465678 ps
CPU time 1826.7 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 02:28:37 PM PST 24
Peak memory 281832 kb
Host smart-e70c97e6-2e65-4435-a5db-90a8ee9cc2d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833034134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1833034134
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3567664930
Short name T214
Test name
Test status
Simulation time 171172592 ps
CPU time 3.61 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:58:13 PM PST 24
Peak memory 249120 kb
Host smart-e29725b6-81b9-47aa-817e-cbebf5e61ef3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3567664930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3567664930
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3854515765
Short name T87
Test name
Test status
Simulation time 28515200261 ps
CPU time 1174 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:17:43 PM PST 24
Peak memory 282616 kb
Host smart-d38f5b38-f25f-4557-a7fa-c91d3692773d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854515765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3854515765
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3954483051
Short name T209
Test name
Test status
Simulation time 766323036 ps
CPU time 11.31 seconds
Started Mar 05 01:58:11 PM PST 24
Finished Mar 05 01:58:22 PM PST 24
Peak memory 248964 kb
Host smart-b8421299-3215-410e-ac8a-5f802359e0e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3954483051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3954483051
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3819211057
Short name T690
Test name
Test status
Simulation time 1300616410 ps
CPU time 52.93 seconds
Started Mar 05 01:58:12 PM PST 24
Finished Mar 05 01:59:05 PM PST 24
Peak memory 249000 kb
Host smart-26b15ab0-7d07-4174-9eb5-4e59908b173f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38192
11057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3819211057
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2833341638
Short name T571
Test name
Test status
Simulation time 170651009 ps
CPU time 20.3 seconds
Started Mar 05 01:58:11 PM PST 24
Finished Mar 05 01:58:31 PM PST 24
Peak memory 255084 kb
Host smart-9d7ebdf2-ff5a-496f-90a2-d4cd8f72dcb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28333
41638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2833341638
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2784613939
Short name T526
Test name
Test status
Simulation time 19525432137 ps
CPU time 1314.81 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:20:05 PM PST 24
Peak memory 272936 kb
Host smart-e4b4c58e-948d-4e7f-8ad0-3e1c1151d751
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784613939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2784613939
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2297834832
Short name T572
Test name
Test status
Simulation time 182728731916 ps
CPU time 2388.2 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:37:58 PM PST 24
Peak memory 289892 kb
Host smart-523d8ec4-151b-4803-9e47-c38d0611b48f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297834832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2297834832
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2248921223
Short name T298
Test name
Test status
Simulation time 6291830975 ps
CPU time 274.67 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 02:02:53 PM PST 24
Peak memory 247668 kb
Host smart-e1d61d89-8356-4220-b7aa-7cab9f95381d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248921223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2248921223
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.4265672576
Short name T378
Test name
Test status
Simulation time 320245902 ps
CPU time 26.01 seconds
Started Mar 05 01:58:08 PM PST 24
Finished Mar 05 01:58:34 PM PST 24
Peak memory 255740 kb
Host smart-e2b75a98-a10b-45db-a67a-4549bcdff094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42656
72576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.4265672576
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1760044595
Short name T29
Test name
Test status
Simulation time 93473525 ps
CPU time 6.2 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 01:58:16 PM PST 24
Peak memory 248436 kb
Host smart-d5d96524-d510-4753-bee7-d53d39821976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17600
44595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1760044595
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2649600231
Short name T255
Test name
Test status
Simulation time 1125097375 ps
CPU time 35.92 seconds
Started Mar 05 01:58:08 PM PST 24
Finished Mar 05 01:58:44 PM PST 24
Peak memory 256192 kb
Host smart-af844b3f-3d5a-4f79-98c5-d3a09cdbfe57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26496
00231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2649600231
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4066730383
Short name T667
Test name
Test status
Simulation time 767980698 ps
CPU time 52.86 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 01:59:02 PM PST 24
Peak memory 255768 kb
Host smart-d74c98f1-ab1e-4fb9-bddb-0ceb998f85c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40667
30383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4066730383
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3065509655
Short name T258
Test name
Test status
Simulation time 69209546391 ps
CPU time 4313.69 seconds
Started Mar 05 01:58:08 PM PST 24
Finished Mar 05 03:10:02 PM PST 24
Peak memory 300776 kb
Host smart-dbed7a11-8679-4936-949d-417f8f454f44
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065509655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3065509655
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3284439101
Short name T576
Test name
Test status
Simulation time 81448129798 ps
CPU time 1539.56 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:23:49 PM PST 24
Peak memory 289924 kb
Host smart-934c8e22-617f-4048-8608-eafc990bc68d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284439101 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3284439101
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2038812589
Short name T222
Test name
Test status
Simulation time 38215808 ps
CPU time 2.49 seconds
Started Mar 05 01:58:17 PM PST 24
Finished Mar 05 01:58:19 PM PST 24
Peak memory 249168 kb
Host smart-c62ca258-e0c0-47da-aec6-806f547a6177
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2038812589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2038812589
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3700785741
Short name T510
Test name
Test status
Simulation time 93877585922 ps
CPU time 2638.09 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:42:08 PM PST 24
Peak memory 272920 kb
Host smart-90d5bd02-6675-41d1-a30c-bb93698effa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700785741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3700785741
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3852886901
Short name T557
Test name
Test status
Simulation time 1222829301 ps
CPU time 55.25 seconds
Started Mar 05 01:58:19 PM PST 24
Finished Mar 05 01:59:14 PM PST 24
Peak memory 240760 kb
Host smart-bbbab85d-2077-44c8-af5e-da7884fbab7b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3852886901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3852886901
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1802759318
Short name T475
Test name
Test status
Simulation time 13440352404 ps
CPU time 218.31 seconds
Started Mar 05 01:58:07 PM PST 24
Finished Mar 05 02:01:46 PM PST 24
Peak memory 257176 kb
Host smart-0fdaa4ec-b34f-4ddd-8572-a8461bc78fd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18027
59318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1802759318
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2114785876
Short name T530
Test name
Test status
Simulation time 81143564 ps
CPU time 9.34 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 01:58:19 PM PST 24
Peak memory 254452 kb
Host smart-d2f92997-cb71-4d3c-8b70-182431933c19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21147
85876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2114785876
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.152289144
Short name T330
Test name
Test status
Simulation time 20149365778 ps
CPU time 769.42 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 02:11:08 PM PST 24
Peak memory 273036 kb
Host smart-a219da30-eabf-4458-b9fb-4778a80efbca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152289144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.152289144
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.1793988453
Short name T551
Test name
Test status
Simulation time 15060775974 ps
CPU time 1615.34 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 02:25:14 PM PST 24
Peak memory 289160 kb
Host smart-023218f1-f480-4252-8338-959b5c2d97b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793988453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1793988453
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1715640198
Short name T558
Test name
Test status
Simulation time 15542639170 ps
CPU time 341.53 seconds
Started Mar 05 01:58:09 PM PST 24
Finished Mar 05 02:03:51 PM PST 24
Peak memory 249000 kb
Host smart-0e3fd7c4-098d-461a-a0b0-43d116323a13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715640198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1715640198
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3676869353
Short name T666
Test name
Test status
Simulation time 224220201 ps
CPU time 19.88 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 01:58:38 PM PST 24
Peak memory 248948 kb
Host smart-e5d5112e-292b-4762-b34d-aea50abe7c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36768
69353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3676869353
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1171443412
Short name T640
Test name
Test status
Simulation time 246503193 ps
CPU time 7.97 seconds
Started Mar 05 01:58:10 PM PST 24
Finished Mar 05 01:58:18 PM PST 24
Peak memory 252020 kb
Host smart-342bfd4e-b1da-4ec3-8ada-59d544afda2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11714
43412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1171443412
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1020185069
Short name T401
Test name
Test status
Simulation time 124493532 ps
CPU time 4.25 seconds
Started Mar 05 01:58:08 PM PST 24
Finished Mar 05 01:58:12 PM PST 24
Peak memory 240776 kb
Host smart-41a33bdd-2964-47f6-bd4d-df5b5dfa809a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10201
85069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1020185069
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3903276759
Short name T394
Test name
Test status
Simulation time 1844117640 ps
CPU time 176.4 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 02:01:14 PM PST 24
Peak memory 257192 kb
Host smart-4f252d4e-174e-4533-a83d-0506c2cbb989
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903276759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3903276759
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1146504942
Short name T212
Test name
Test status
Simulation time 29830514 ps
CPU time 2.55 seconds
Started Mar 05 01:58:19 PM PST 24
Finished Mar 05 01:58:22 PM PST 24
Peak memory 249156 kb
Host smart-b9f1f78d-40f3-45d9-b990-9214192f7ea4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1146504942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1146504942
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1956782823
Short name T596
Test name
Test status
Simulation time 408571240958 ps
CPU time 1833.7 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 02:29:07 PM PST 24
Peak memory 281820 kb
Host smart-83142c46-ab5c-410b-9051-611dbe993b1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956782823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1956782823
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4018250895
Short name T409
Test name
Test status
Simulation time 408078683 ps
CPU time 19.44 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:39 PM PST 24
Peak memory 240744 kb
Host smart-423279fd-4c51-4957-a2da-2ffcf3c6852f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4018250895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4018250895
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2951904235
Short name T376
Test name
Test status
Simulation time 275911264 ps
CPU time 26.52 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 01:58:45 PM PST 24
Peak memory 248448 kb
Host smart-ebc0d22b-7e4d-4509-91ee-84de24007af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29519
04235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2951904235
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3014177409
Short name T521
Test name
Test status
Simulation time 3063669569 ps
CPU time 43.44 seconds
Started Mar 05 01:58:17 PM PST 24
Finished Mar 05 01:59:00 PM PST 24
Peak memory 255464 kb
Host smart-c3843bb8-c72e-42ac-a773-e6cf68056b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30141
77409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3014177409
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2315418730
Short name T277
Test name
Test status
Simulation time 15685693660 ps
CPU time 1559.7 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 02:24:20 PM PST 24
Peak memory 281636 kb
Host smart-ea0fc464-e77c-47e1-8e90-0488915a8fe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315418730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2315418730
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.357182640
Short name T610
Test name
Test status
Simulation time 232723214858 ps
CPU time 2721.46 seconds
Started Mar 05 01:58:30 PM PST 24
Finished Mar 05 02:43:52 PM PST 24
Peak memory 289532 kb
Host smart-9268e537-6d5e-41e3-8c8a-09d13f68daf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357182640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.357182640
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.325573917
Short name T67
Test name
Test status
Simulation time 15011817794 ps
CPU time 199.47 seconds
Started Mar 05 01:58:17 PM PST 24
Finished Mar 05 02:01:36 PM PST 24
Peak memory 247824 kb
Host smart-77e8f2e8-c093-4d3b-b489-3217248e7efc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325573917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.325573917
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2072846835
Short name T567
Test name
Test status
Simulation time 116092019 ps
CPU time 11.05 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 01:58:29 PM PST 24
Peak memory 254268 kb
Host smart-c2ec2a25-c80b-4edc-82b5-e35ef4754d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20728
46835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2072846835
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2021626176
Short name T271
Test name
Test status
Simulation time 1521979709 ps
CPU time 49.24 seconds
Started Mar 05 01:58:16 PM PST 24
Finished Mar 05 01:59:05 PM PST 24
Peak memory 255848 kb
Host smart-f22b5779-0f5f-4ca0-81f8-841db2f295f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20216
26176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2021626176
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.583562754
Short name T395
Test name
Test status
Simulation time 371162107 ps
CPU time 8.51 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:28 PM PST 24
Peak memory 250788 kb
Host smart-31dd2359-5f51-4732-8fab-ccf74fade59c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58356
2754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.583562754
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3237029321
Short name T639
Test name
Test status
Simulation time 829195395 ps
CPU time 53.1 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 01:59:26 PM PST 24
Peak memory 248972 kb
Host smart-c294b580-db26-4162-b69e-562d18c5d361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32370
29321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3237029321
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.718803524
Short name T257
Test name
Test status
Simulation time 5270013293 ps
CPU time 150.63 seconds
Started Mar 05 01:58:17 PM PST 24
Finished Mar 05 02:00:48 PM PST 24
Peak memory 257176 kb
Host smart-47cc0efb-9ab6-4a3a-b06e-bd3778a405f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718803524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.718803524
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3128510407
Short name T230
Test name
Test status
Simulation time 26862092 ps
CPU time 2.74 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 01:58:29 PM PST 24
Peak memory 249084 kb
Host smart-39ae2316-45c7-4147-9386-ceaf54f63001
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3128510407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3128510407
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.832644164
Short name T72
Test name
Test status
Simulation time 72535490719 ps
CPU time 2226.1 seconds
Started Mar 05 01:58:27 PM PST 24
Finished Mar 05 02:35:34 PM PST 24
Peak memory 286332 kb
Host smart-6b0e2f6d-f666-43c3-bcf8-d715ec4e0d59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832644164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.832644164
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3267952482
Short name T484
Test name
Test status
Simulation time 320204010 ps
CPU time 9.69 seconds
Started Mar 05 01:58:27 PM PST 24
Finished Mar 05 01:58:37 PM PST 24
Peak memory 240740 kb
Host smart-e27647c1-a6d7-4619-9ef4-012a5ca7c247
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3267952482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3267952482
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2273164783
Short name T509
Test name
Test status
Simulation time 158754560 ps
CPU time 12.77 seconds
Started Mar 05 01:58:33 PM PST 24
Finished Mar 05 01:58:46 PM PST 24
Peak memory 253076 kb
Host smart-f3243d9f-5074-4c0d-8a32-46621705393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22731
64783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2273164783
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2481558510
Short name T600
Test name
Test status
Simulation time 218338656 ps
CPU time 8.35 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:29 PM PST 24
Peak memory 249632 kb
Host smart-2b38bef2-e852-4f21-ba9c-b33b2b9240cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24815
58510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2481558510
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3981832689
Short name T295
Test name
Test status
Simulation time 47117905879 ps
CPU time 2657.07 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 02:42:44 PM PST 24
Peak memory 281820 kb
Host smart-cc3afda6-9da6-4552-9a2f-05ec42ec8828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981832689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3981832689
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2836044176
Short name T439
Test name
Test status
Simulation time 44566379729 ps
CPU time 1561.88 seconds
Started Mar 05 01:58:26 PM PST 24
Finished Mar 05 02:24:28 PM PST 24
Peak memory 273260 kb
Host smart-7fd99908-4185-494a-aabb-305af21c6309
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836044176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2836044176
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2741183343
Short name T614
Test name
Test status
Simulation time 1227918979 ps
CPU time 22.16 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:43 PM PST 24
Peak memory 248972 kb
Host smart-3bc6c2ab-479c-4542-9f2d-f768843bad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27411
83343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2741183343
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4293827838
Short name T489
Test name
Test status
Simulation time 394623984 ps
CPU time 19.19 seconds
Started Mar 05 01:58:18 PM PST 24
Finished Mar 05 01:58:37 PM PST 24
Peak memory 247288 kb
Host smart-037945db-da5a-444b-8575-3dc8e0d1cc56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42938
27838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4293827838
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2175668672
Short name T703
Test name
Test status
Simulation time 404652538 ps
CPU time 18.28 seconds
Started Mar 05 01:58:20 PM PST 24
Finished Mar 05 01:58:39 PM PST 24
Peak memory 248968 kb
Host smart-ebbbeab0-6d7c-4e1a-a072-8d2bb9b4ce66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21756
68672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2175668672
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2427705257
Short name T80
Test name
Test status
Simulation time 60306195223 ps
CPU time 821.84 seconds
Started Mar 05 01:58:25 PM PST 24
Finished Mar 05 02:12:07 PM PST 24
Peak memory 265420 kb
Host smart-10247328-f02b-4c1b-8e71-a82d1653bddd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427705257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2427705257
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1639751760
Short name T103
Test name
Test status
Simulation time 155900625026 ps
CPU time 2466.43 seconds
Started Mar 05 01:58:29 PM PST 24
Finished Mar 05 02:39:36 PM PST 24
Peak memory 305412 kb
Host smart-c28cfcb9-03a0-4913-8609-7f875be91e4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639751760 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1639751760
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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