Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	67134	1			T21	1		T31	559		T32	174
class_i[0x1]	77438	1			T4	2		T21	18		T24	2
class_i[0x2]	70647	1			T5	4395		T21	1		T31	1199
class_i[0x3]	68751	1			T21	3		T31	170		T33	73

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	68822	1			T4	1		T5	991		T31	53
alert[0x1]	75625	1			T5	1155		T21	5		T31	1000
alert[0x2]	67788	1			T5	1125		T21	7		T24	2
alert[0x3]	71735	1			T4	1		T5	1124		T21	11

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

283664

1

T4

2

T5

4395

T21

16

esc_ping_fail

306

1

T21

7

T22

2

T23

11

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	68740	1			T4	1		T5	991		T31	53
esc_integrity_fail	alert[0x1]	75541	1			T5	1155		T21	3		T31	1000
esc_integrity_fail	alert[0x2]	67711	1			T5	1125		T21	5		T24	2
esc_integrity_fail	alert[0x3]	71672	1			T4	1		T5	1124		T21	8
esc_ping_fail	alert[0x0]	82	1			T23	2		T125	3		T65	1
esc_ping_fail	alert[0x1]	84	1			T21	2		T22	1		T23	4
esc_ping_fail	alert[0x2]	77	1			T21	2		T22	1		T23	3
esc_ping_fail	alert[0x3]	63	1			T21	3		T23	2		T125	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	67083	1			T31	559		T32	174		T33	896
esc_integrity_fail	class_i[0x1]	77340	1			T4	2		T21	16		T24	2
esc_integrity_fail	class_i[0x2]	70571	1			T5	4395		T31	1199		T33	48
esc_integrity_fail	class_i[0x3]	68670	1			T31	170		T33	73		T27	37
esc_ping_fail	class_i[0x0]	51	1			T21	1		T22	2		T260	5
esc_ping_fail	class_i[0x1]	98	1			T21	2		T65	4		T293	5
esc_ping_fail	class_i[0x2]	76	1			T21	1		T23	11		T290	5
esc_ping_fail	class_i[0x3]	81	1			T21	3		T125	8		T289	10