Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	674113279	0	0	0
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	674113279	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	674113279	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	674113279	673942298	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	674113279	673942298	0	0
tb.dut.EdnKnownO_A	0	0	674113279	673942298	0	0
tb.dut.EscPKnownO_A	0	0	674113279	673942298	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	674113279	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	674113279	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	674113279	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	674113279	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	674113279	80	0	0
tb.dut.IrqAKnownO_A	0	0	674113279	673942298	0	0
tb.dut.IrqBKnownO_A	0	0	674113279	673942298	0	0
tb.dut.IrqCKnownO_A	0	0	674113279	673942298	0	0
tb.dut.IrqDKnownO_A	0	0	674113279	673942298	0	0
tb.dut.TlAReadyKnownO_A	0	0	674113279	673942298	0	0
tb.dut.TlDValidKnownO_A	0	0	674113279	673942298	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	698160105	2039417	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	698160105	12854	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	698160105	12887	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	698160105	13647	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	698160105	12758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	698160105	13460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	698160105	13620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	698160105	13323	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	698160105	14525	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	698160105	12337	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	698160105	13650	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	698160105	12621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	698160105	13548	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	698160105	12520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	698160105	12559	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	698160105	12982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	698160105	13740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	698160105	14099	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	698160105	13622	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	698160105	13576	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	698160105	12257	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	698160105	13656	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	698160105	14898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	698160105	12568	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	698160105	12908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	698160105	12441	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	698160105	13596	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	698160105	12118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	698160105	13423	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	698160105	13592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	698160105	13720	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	698160105	13558	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	698160105	13719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	698160105	12502	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	698160105	12355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	698160105	12288	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	698160105	13236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	698160105	14677	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	698160105	12456	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	698160105	12372	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	698160105	12528	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	698160105	13892	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	698160105	13791	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	698160105	12551	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	698160105	12986	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	698160105	13756	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	698160105	14832	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	698160105	12620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	698160105	12197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	698160105	12918	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	698160105	12548	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	698160105	12196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	698160105	12769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	698160105	12719	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	698160105	12363	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	698160105	13474	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	698160105	13691	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	698160105	13879	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	698160105	12542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	698160105	12747	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	698160105	12471	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	698160105	12494	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	698160105	12752	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	698160105	13760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	698160105	12606	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	698160105	14423	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	698160105	14854	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	698160105	12466	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	698160105	12510	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	698160105	12303	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	698160105	23844	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	698160105	13897	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	698160105	12158	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	698160105	12674	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	698160105	12164	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	698160105	11977	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	698160105	13709	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	698160105	12579	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	698160105	12708	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	674113279	1116	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	674113279	208221	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	674113279	326853482	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	674113279	287	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	674113279	716	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	674113279	59	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	674113279	336	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	673960922	221518406	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	674113279	824	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	674113279	810	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	674113279	794	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	674113279	777	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	674113279	1814	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	674113279	130994	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	674113279	1691	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	674113279	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674113279	1479	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	674113279	1239	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	674113279	673942298	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	674113279	9112	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	674113279	247316	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	674113279	366124249	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	674113279	276	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	674113279	499	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	674113279	22	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	674113279	222	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	673960922	303570196	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	674113279	573	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	674113279	567	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	674113279	556	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	674113279	541	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	674113279	1222	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	674113279	93554	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	674113279	1138	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	674113279	62	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674113279	1430	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	674113279	1190	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	674113279	673942298	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	674113279	3301	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	674113279	183608	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	674113279	351715903	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	674113279	300	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	674113279	530	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	674113279	20	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	674113279	236	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	673960922	264911215	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	674113279	593	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	674113279	578	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	674113279	563	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	674113279	552	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	674113279	595	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	674113279	71412	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	674113279	521	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	674113279	54	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674113279	1510	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	674113279	1270	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	674113279	673942298	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	674113279	80	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	674113279	212580	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	674113279	349160198	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	674113279	304	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	674113279	495	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	674113279	16	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	674113279	213	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	673960922	273276968	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	674113279	551	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	674113279	543	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	674113279	538	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	674113279	532	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	674113279	1345	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	674113279	108145	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	674113279	1276	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	674113279	51	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	674113279	1467	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	674113279	1227	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	674113279	673942298	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	698160105	122263107	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	698160105	697470921	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	698160105	697470921	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	698160105	186116940	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	698160105	697470921	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	698160105	697470921	0	0
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