Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T5	1		T6	1		T31	1
class_index[0x1]	62	1			T3	1		T18	1		T5	2
class_index[0x2]	54	1			T5	1		T31	1		T32	1
class_index[0x3]	51	1			T5	1		T31	2		T33	2

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	107	1			T3	1		T5	5		T31	3
intr_timeout_cnt[1]	35	1			T18	1		T6	1		T74	1
intr_timeout_cnt[2]	21	1			T33	1		T74	1		T77	1
intr_timeout_cnt[3]	8	1			T53	1		T82	2		T263	1
intr_timeout_cnt[4]	19	1			T31	1		T33	1		T73	3
intr_timeout_cnt[5]	14	1			T32	1		T264	4		T113	1
intr_timeout_cnt[6]	7	1			T27	1		T91	1		T94	1
intr_timeout_cnt[7]	5	1			T32	1		T33	1		T247	1
intr_timeout_cnt[8]	7	1			T33	3		T27	1		T119	1
intr_timeout_cnt[9]	6	1			T77	1		T94	2		T101	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	32	1			T5	1		T31	1		T34	1
class_index[0x0]	intr_timeout_cnt[1]	8	1			T6	1		T77	1		T59	2
class_index[0x0]	intr_timeout_cnt[2]	5	1			T77	1		T59	1		T265	1
class_index[0x0]	intr_timeout_cnt[3]	3	1			T53	1		T266	1		T267	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T104	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T27	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	3	1			T32	1		T247	1		T268	1
class_index[0x0]	intr_timeout_cnt[8]	4	1			T33	3		T119	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	4	1			T77	1		T94	2		T101	1
class_index[0x1]	intr_timeout_cnt[0]	34	1			T3	1		T5	2		T76	1
class_index[0x1]	intr_timeout_cnt[1]	5	1			T18	1		T74	1		T77	1
class_index[0x1]	intr_timeout_cnt[2]	7	1			T59	4		T114	1		T249	2
class_index[0x1]	intr_timeout_cnt[3]	3	1			T82	1		T263	1		T269	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T42	1		T86	1		T270	1
class_index[0x1]	intr_timeout_cnt[5]	5	1			T264	4		T271	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T101	1		T272	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	1	1			T33	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T273	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T273	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T5	1		T39	1		T79	1
class_index[0x2]	intr_timeout_cnt[1]	13	1			T78	1		T58	1		T274	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T275	1		T266	1		T276	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T82	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	9	1			T31	1		T73	3		T51	1
class_index[0x2]	intr_timeout_cnt[5]	4	1			T32	1		T188	1		T83	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T94	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T104	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	19	1			T5	1		T31	2		T112	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T113	1		T246	1		T83	2
class_index[0x3]	intr_timeout_cnt[2]	6	1			T33	1		T74	1		T188	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T225	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	5	1			T33	1		T277	1		T278	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T113	1		T279	1		T280	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T91	1		T188	1		T281	1
class_index[0x3]	intr_timeout_cnt[7]	1	1			T282	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T27	1		T283	1		-	-