Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	347403	1			T2	1461		T3	37		T18	19
all_values[1]	347403	1			T2	1461		T3	37		T18	19
all_values[2]	347403	1			T2	1461		T3	37		T18	19
all_values[3]	347403	1			T2	1461		T3	37		T18	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

691536

1

T2

2824

T3

79

T18

34

auto[1]

698076

1

T2

3020

T3

69

T18

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814977

1

T2

2944

T3

77

T18

41

auto[1]

574635

1

T2

2900

T3

71

T18

35

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	97685	1			T2	350		T3	7		T18	3
all_values[0]	auto[0]	auto[1]	75187	1			T2	342		T3	6		T18	2
all_values[0]	auto[1]	auto[0]	99421	1			T2	390		T3	12		T18	7
all_values[0]	auto[1]	auto[1]	75110	1			T2	379		T3	12		T18	7
all_values[1]	auto[0]	auto[0]	101708	1			T2	359		T3	10		T18	4
all_values[1]	auto[0]	auto[1]	70684	1			T2	349		T3	9		T18	4
all_values[1]	auto[1]	auto[0]	103793	1			T2	380		T3	9		T18	6
all_values[1]	auto[1]	auto[1]	71218	1			T2	373		T3	9		T18	5
all_values[2]	auto[0]	auto[0]	102507	1			T2	350		T3	13		T18	4
all_values[2]	auto[0]	auto[1]	70889	1			T2	350		T3	13		T18	4
all_values[2]	auto[1]	auto[0]	103390	1			T2	381		T3	7		T18	6
all_values[2]	auto[1]	auto[1]	70617	1			T2	380		T3	4		T18	5
all_values[3]	auto[0]	auto[0]	102382	1			T2	362		T3	11		T18	8
all_values[3]	auto[0]	auto[1]	70494	1			T2	362		T3	10		T18	5
all_values[3]	auto[1]	auto[0]	104091	1			T2	372		T3	8		T18	3
all_values[3]	auto[1]	auto[1]	70436	1			T2	365		T3	8		T18	3