Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	347403	1			T2	1461		T3	37		T18	19
all_pins[1]	347403	1			T2	1461		T3	37		T18	19
all_pins[2]	347403	1			T2	1461		T3	37		T18	19
all_pins[3]	347403	1			T2	1461		T3	37		T18	19

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1102231	1			T2	4347		T3	115		T18	56
values[0x1]	287381	1			T2	1497		T3	33		T18	20
transitions[0x0=>0x1]	190121	1			T2	913		T3	21		T18	11
transitions[0x1=>0x0]	190368	1			T2	913		T3	22		T18	12

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	272293	1			T2	1082		T3	25		T18	12
all_pins[0]	values[0x1]	75110	1			T2	379		T3	12		T18	7
all_pins[0]	transitions[0x0=>0x1]	74507	1			T2	379		T3	11		T18	6
all_pins[0]	transitions[0x1=>0x0]	70080	1			T2	365		T3	8		T18	3
all_pins[1]	values[0x0]	276185	1			T2	1088		T3	28		T18	14
all_pins[1]	values[0x1]	71218	1			T2	373		T3	9		T18	5
all_pins[1]	transitions[0x0=>0x1]	38655	1			T2	183		T3	2		T18	2
all_pins[1]	transitions[0x1=>0x0]	42547	1			T2	189		T3	5		T18	4
all_pins[2]	values[0x0]	276786	1			T2	1081		T3	33		T18	14
all_pins[2]	values[0x1]	70617	1			T2	380		T3	4		T18	5
all_pins[2]	transitions[0x0=>0x1]	38660	1			T2	182		T3	3		T18	1
all_pins[2]	transitions[0x1=>0x0]	39261	1			T2	175		T3	8		T18	1
all_pins[3]	values[0x0]	276967	1			T2	1096		T3	29		T18	16
all_pins[3]	values[0x1]	70436	1			T2	365		T3	8		T18	3
all_pins[3]	transitions[0x0=>0x1]	38299	1			T2	169		T3	5		T18	2
all_pins[3]	transitions[0x1=>0x0]	38480	1			T2	184		T3	1		T18	4