Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	101423	1			T2	1469		T5	521		T6	375
accum_cnt_1000	245576	1			T2	1683		T4	43		T12	1579
accum_cnt_100	26929	1			T2	91		T4	11		T12	140
accum_cnt_50	54905	1			T2	59		T3	42		T18	4
accum_cnt_10	187672	1			T2	1128		T3	23		T18	48
accum_cnt_0	363292	1			T2	6		T3	79		T18	20

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	256381	1			T2	1109		T3	36		T18	18
class_index[0x1]	256381	1			T2	1109		T3	36		T18	18
class_index[0x2]	256381	1			T2	1109		T3	36		T18	18
class_index[0x3]	256381	1			T2	1109		T3	36		T18	18

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	23223	1			T2	512		T5	521		T26	206
class_index[0x0]	accum_cnt_1000	64904	1			T2	540		T4	43		T5	514
class_index[0x0]	accum_cnt_100	7271	1			T2	27		T4	11		T5	53
class_index[0x0]	accum_cnt_50	16712	1			T2	21		T4	11		T30	8
class_index[0x0]	accum_cnt_10	48004	1			T2	7		T4	32		T8	5
class_index[0x0]	accum_cnt_0	84720	1			T2	2		T3	36		T18	18
class_index[0x1]	accum_cnt_2000	25731	1			T2	417		T24	228		T25	200
class_index[0x1]	accum_cnt_1000	60615	1			T2	621		T12	788		T5	4
class_index[0x1]	accum_cnt_100	5570	1			T2	41		T12	81		T28	8
class_index[0x1]	accum_cnt_50	10146	1			T2	19		T3	20		T18	4
class_index[0x1]	accum_cnt_10	46843	1			T2	9		T3	13		T18	14
class_index[0x1]	accum_cnt_0	93393	1			T2	2		T3	3		T7	12
class_index[0x2]	accum_cnt_2000	25789	1			T2	540		T6	375		T25	279
class_index[0x2]	accum_cnt_1000	62740	1			T2	522		T5	37		T6	624
class_index[0x2]	accum_cnt_100	6613	1			T2	23		T5	29		T6	79
class_index[0x2]	accum_cnt_50	14678	1			T2	19		T3	22		T7	4
class_index[0x2]	accum_cnt_10	46818	1			T2	3		T3	10		T18	16
class_index[0x2]	accum_cnt_0	92631	1			T2	2		T3	4		T18	2
class_index[0x3]	accum_cnt_2000	26680	1			T25	200		T106	488		T95	579
class_index[0x3]	accum_cnt_1000	57317	1			T12	791		T20	790		T24	969
class_index[0x3]	accum_cnt_100	7475	1			T12	59		T5	55		T20	182
class_index[0x3]	accum_cnt_50	13369	1			T7	7		T4	1		T12	86
class_index[0x3]	accum_cnt_10	46007	1			T2	1109		T18	18		T7	4
class_index[0x3]	accum_cnt_0	92548	1			T3	36		T7	1		T4	119