Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	3771	1			T21	1		T26	60		T32	11
alert[0x1]	5958	1			T34	193		T227	2		T43	4
alert[0x2]	14947	1			T6	1		T31	20		T33	12
alert[0x3]	8800	1			T6	2		T32	1		T34	177
alert[0x4]	3158	1			T31	1		T33	567		T27	35
alert[0x5]	3733	1			T21	1		T33	7		T34	13
alert[0x6]	12272	1			T21	1		T26	2171		T121	340
alert[0x7]	4397	1			T12	1		T26	9		T43	44
alert[0x8]	10194	1			T21	1		T27	3		T77	1
alert[0x9]	5255	1			T31	2		T26	840		T33	3
alert[0xa]	5889	1			T5	8		T31	4		T26	23
alert[0xb]	4780	1			T31	2		T33	9		T27	10
alert[0xc]	8111	1			T34	73		T43	18		T23	1
alert[0xd]	7393	1			T31	4		T34	119		T75	90
alert[0xe]	3389	1			T6	2		T26	84		T32	2
alert[0xf]	4285	1			T31	8		T32	21		T33	5
alert[0x10]	8487	1			T26	69		T32	3		T34	12
alert[0x11]	3594	1			T33	14		T43	37		T23	1
alert[0x12]	2667	1			T21	1		T33	2		T34	10
alert[0x13]	2377	1			T21	1		T26	15		T27	6
alert[0x14]	5033	1			T31	3		T34	45		T43	272
alert[0x15]	8039	1			T31	1		T27	27		T43	534
alert[0x16]	9269	1			T31	3		T27	1		T76	1
alert[0x17]	5575	1			T31	7		T27	1		T74	1
alert[0x18]	8375	1			T26	225		T32	3		T42	2
alert[0x19]	5738	1			T33	7		T125	1		T65	1
alert[0x1a]	6819	1			T6	2		T121	500		T75	19
alert[0x1b]	5924	1			T5	5		T32	2		T27	20
alert[0x1c]	4269	1			T121	89		T50	1		T289	1
alert[0x1d]	7006	1			T21	2		T31	10		T26	1396
alert[0x1e]	8849	1			T5	4		T21	1		T26	17
alert[0x1f]	6232	1			T20	1		T32	5		T33	95
alert[0x20]	8106	1			T21	1		T26	125		T34	1345
alert[0x21]	2688	1			T31	7		T26	39		T121	28
alert[0x22]	8270	1			T34	16		T23	3		T121	19
alert[0x23]	9940	1			T26	234		T33	25		T43	9
alert[0x24]	13243	1			T26	93		T33	9		T34	12
alert[0x25]	4333	1			T31	2		T43	871		T121	141
alert[0x26]	7507	1			T21	1		T43	872		T77	3
alert[0x27]	4013	1			T26	9		T32	4		T27	300
alert[0x28]	11795	1			T21	1		T26	28		T33	1
alert[0x29]	4196	1			T26	287		T27	4		T34	51
alert[0x2a]	7481	1			T33	145		T125	1		T88	134
alert[0x2b]	13702	1			T4	1		T31	2		T43	92
alert[0x2c]	4369	1			T5	2		T26	5		T33	6
alert[0x2d]	8370	1			T5	1		T26	1111		T33	6
alert[0x2e]	1650	1			T6	1		T21	1		T22	1
alert[0x2f]	15323	1			T21	2		T32	2		T33	51
alert[0x30]	4082	1			T6	1		T21	1		T22	2
alert[0x31]	6161	1			T21	1		T33	7		T27	7
alert[0x32]	9617	1			T21	1		T26	4		T32	4
alert[0x33]	2380	1			T31	3		T26	95		T23	1
alert[0x34]	5057	1			T33	27		T34	226		T125	1
alert[0x35]	9576	1			T6	19		T33	210		T27	1
alert[0x36]	9182	1			T33	216		T34	107		T75	142
alert[0x37]	3110	1			T21	1		T26	278		T32	2
alert[0x38]	2925	1			T6	1		T27	1		T77	3
alert[0x39]	2380	1			T34	6		T42	11		T43	26
alert[0x3a]	3806	1			T75	169		T65	1		T290	1
alert[0x3b]	4517	1			T4	1		T21	1		T227	3
alert[0x3c]	8709	1			T34	36		T75	155		T289	1
alert[0x3d]	4678	1			T32	4		T33	67		T34	2
alert[0x3e]	7112	1			T21	1		T31	1		T33	8
alert[0x3f]	8940	1			T43	1276		T125	1		T77	19
alert[0x40]	11970	1			T32	1		T27	13		T34	33

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	116303	1			T6	14		T31	17		T26	7194
class_i[0x1]	103284	1			T6	11		T31	7		T26	15
class_i[0x2]	106817	1			T12	1		T5	2		T6	4
class_i[0x3]	107369	1			T4	2		T5	18		T31	56

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

433099

1

T4

2

T5

20

T6

29

alert_ping_fail

674

1

T12

1

T21

21

T20

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	3758	1			T26	60		T32	11		T27	14
alert_integrity_fail	alert[0x1]	5945	1			T34	193		T227	2		T43	4
alert_integrity_fail	alert[0x2]	14929	1			T6	1		T31	20		T33	12
alert_integrity_fail	alert[0x3]	8794	1			T6	2		T32	1		T34	177
alert_integrity_fail	alert[0x4]	3147	1			T31	1		T33	567		T27	35
alert_integrity_fail	alert[0x5]	3721	1			T33	7		T34	13		T121	33
alert_integrity_fail	alert[0x6]	12260	1			T26	2171		T121	340		T54	790
alert_integrity_fail	alert[0x7]	4384	1			T26	9		T43	44		T75	68
alert_integrity_fail	alert[0x8]	10179	1			T27	3		T77	1		T88	78
alert_integrity_fail	alert[0x9]	5247	1			T31	2		T26	840		T33	3
alert_integrity_fail	alert[0xa]	5876	1			T5	8		T31	4		T26	23
alert_integrity_fail	alert[0xb]	4771	1			T31	2		T33	9		T27	10
alert_integrity_fail	alert[0xc]	8105	1			T34	73		T43	18		T121	44
alert_integrity_fail	alert[0xd]	7379	1			T31	4		T34	119		T75	90
alert_integrity_fail	alert[0xe]	3379	1			T6	2		T26	84		T32	2
alert_integrity_fail	alert[0xf]	4272	1			T31	8		T32	21		T33	5
alert_integrity_fail	alert[0x10]	8475	1			T26	69		T32	3		T34	12
alert_integrity_fail	alert[0x11]	3581	1			T33	14		T43	37		T76	5
alert_integrity_fail	alert[0x12]	2660	1			T33	2		T34	10		T121	2
alert_integrity_fail	alert[0x13]	2367	1			T26	15		T27	6		T34	26
alert_integrity_fail	alert[0x14]	5025	1			T31	3		T34	45		T43	272
alert_integrity_fail	alert[0x15]	8031	1			T31	1		T27	27		T43	534
alert_integrity_fail	alert[0x16]	9259	1			T31	3		T27	1		T76	1
alert_integrity_fail	alert[0x17]	5571	1			T31	7		T27	1		T74	1
alert_integrity_fail	alert[0x18]	8367	1			T26	225		T32	3		T42	2
alert_integrity_fail	alert[0x19]	5731	1			T33	7		T77	8		T54	213
alert_integrity_fail	alert[0x1a]	6810	1			T6	2		T121	500		T75	19
alert_integrity_fail	alert[0x1b]	5920	1			T5	5		T32	2		T27	20
alert_integrity_fail	alert[0x1c]	4260	1			T121	89		T50	1		T55	1
alert_integrity_fail	alert[0x1d]	6995	1			T31	10		T26	1396		T32	122
alert_integrity_fail	alert[0x1e]	8840	1			T5	4		T26	17		T43	115
alert_integrity_fail	alert[0x1f]	6217	1			T32	5		T33	95		T34	9
alert_integrity_fail	alert[0x20]	8094	1			T26	125		T34	1345		T74	2
alert_integrity_fail	alert[0x21]	2677	1			T31	7		T26	39		T121	28
alert_integrity_fail	alert[0x22]	8256	1			T34	16		T121	19		T54	94
alert_integrity_fail	alert[0x23]	9928	1			T26	234		T33	25		T43	9
alert_integrity_fail	alert[0x24]	13232	1			T26	93		T33	9		T34	12
alert_integrity_fail	alert[0x25]	4326	1			T31	2		T43	871		T121	141
alert_integrity_fail	alert[0x26]	7502	1			T43	872		T77	3		T54	442
alert_integrity_fail	alert[0x27]	4003	1			T26	9		T32	4		T27	300
alert_integrity_fail	alert[0x28]	11784	1			T26	28		T33	1		T27	5
alert_integrity_fail	alert[0x29]	4184	1			T26	287		T27	4		T34	51
alert_integrity_fail	alert[0x2a]	7470	1			T33	145		T88	134		T119	2
alert_integrity_fail	alert[0x2b]	13694	1			T4	1		T31	2		T43	92
alert_integrity_fail	alert[0x2c]	4354	1			T5	2		T26	5		T33	6
alert_integrity_fail	alert[0x2d]	8355	1			T5	1		T26	1111		T33	6
alert_integrity_fail	alert[0x2e]	1632	1			T6	1		T34	11		T75	80
alert_integrity_fail	alert[0x2f]	15313	1			T32	2		T33	51		T27	5
alert_integrity_fail	alert[0x30]	4067	1			T6	1		T34	369		T121	64
alert_integrity_fail	alert[0x31]	6154	1			T33	7		T27	7		T43	162
alert_integrity_fail	alert[0x32]	9605	1			T26	4		T32	4		T33	428
alert_integrity_fail	alert[0x33]	2367	1			T31	3		T26	95		T121	180
alert_integrity_fail	alert[0x34]	5049	1			T33	27		T34	226		T50	2
alert_integrity_fail	alert[0x35]	9567	1			T6	19		T33	210		T27	1
alert_integrity_fail	alert[0x36]	9172	1			T33	216		T34	107		T75	142
alert_integrity_fail	alert[0x37]	3097	1			T26	278		T32	2		T43	18
alert_integrity_fail	alert[0x38]	2915	1			T6	1		T27	1		T77	3
alert_integrity_fail	alert[0x39]	2373	1			T34	6		T42	11		T43	26
alert_integrity_fail	alert[0x3a]	3795	1			T75	169		T88	48		T15	12
alert_integrity_fail	alert[0x3b]	4506	1			T4	1		T227	3		T43	1
alert_integrity_fail	alert[0x3c]	8699	1			T34	36		T75	155		T232	1
alert_integrity_fail	alert[0x3d]	4669	1			T32	4		T33	67		T34	2
alert_integrity_fail	alert[0x3e]	7101	1			T31	1		T33	8		T34	210
alert_integrity_fail	alert[0x3f]	8937	1			T43	1276		T77	19		T54	22
alert_integrity_fail	alert[0x40]	11967	1			T32	1		T27	13		T34	33
alert_ping_fail	alert[0x0]	13	1			T21	1		T23	1		T65	1
alert_ping_fail	alert[0x1]	13	1			T23	2		T289	1		T291	1
alert_ping_fail	alert[0x2]	18	1			T23	2		T125	1		T292	1
alert_ping_fail	alert[0x3]	6	1			T23	1		T293	1		T294	1
alert_ping_fail	alert[0x4]	11	1			T65	1		T289	1		T295	2
alert_ping_fail	alert[0x5]	12	1			T21	1		T293	1		T238	1
alert_ping_fail	alert[0x6]	12	1			T21	1		T290	1		T289	1
alert_ping_fail	alert[0x7]	13	1			T12	1		T65	1		T289	2
alert_ping_fail	alert[0x8]	15	1			T21	1		T293	1		T89	1
alert_ping_fail	alert[0x9]	8	1			T296	1		T295	1		T234	1
alert_ping_fail	alert[0xa]	13	1			T289	1		T292	1		T297	1
alert_ping_fail	alert[0xb]	9	1			T297	1		T298	1		T299	1
alert_ping_fail	alert[0xc]	6	1			T23	1		T289	1		T298	1
alert_ping_fail	alert[0xd]	14	1			T297	1		T296	1		T300	1
alert_ping_fail	alert[0xe]	10	1			T125	1		T298	1		T295	1
alert_ping_fail	alert[0xf]	13	1			T23	1		T289	1		T301	1
alert_ping_fail	alert[0x10]	12	1			T23	1		T125	1		T65	1
alert_ping_fail	alert[0x11]	13	1			T23	1		T125	1		T292	1
alert_ping_fail	alert[0x12]	7	1			T21	1		T293	1		T260	1
alert_ping_fail	alert[0x13]	10	1			T21	1		T289	1		T294	1
alert_ping_fail	alert[0x14]	8	1			T290	1		T293	1		T238	1
alert_ping_fail	alert[0x15]	8	1			T289	1		T294	1		T296	1
alert_ping_fail	alert[0x16]	10	1			T231	1		T256	2		T292	1
alert_ping_fail	alert[0x17]	4	1			T23	1		T298	1		T302	1
alert_ping_fail	alert[0x18]	8	1			T289	1		T292	1		T297	1
alert_ping_fail	alert[0x19]	7	1			T125	1		T65	1		T298	2
alert_ping_fail	alert[0x1a]	9	1			T290	1		T260	2		T299	1
alert_ping_fail	alert[0x1b]	4	1			T234	1		T303	1		T304	1
alert_ping_fail	alert[0x1c]	9	1			T289	1		T260	1		T300	2
alert_ping_fail	alert[0x1d]	11	1			T21	2		T125	2		T292	2
alert_ping_fail	alert[0x1e]	9	1			T21	1		T65	1		T294	1
alert_ping_fail	alert[0x1f]	15	1			T20	1		T108	2		T23	1
alert_ping_fail	alert[0x20]	12	1			T21	1		T65	1		T301	1
alert_ping_fail	alert[0x21]	11	1			T125	1		T65	1		T290	1
alert_ping_fail	alert[0x22]	14	1			T23	3		T287	1		T238	2
alert_ping_fail	alert[0x23]	12	1			T301	1		T305	3		T294	1
alert_ping_fail	alert[0x24]	11	1			T125	1		T260	3		T298	1
alert_ping_fail	alert[0x25]	7	1			T65	1		T294	1		T306	1
alert_ping_fail	alert[0x26]	5	1			T21	1		T292	1		T298	1
alert_ping_fail	alert[0x27]	10	1			T23	1		T290	1		T291	1
alert_ping_fail	alert[0x28]	11	1			T21	1		T125	1		T292	1
alert_ping_fail	alert[0x29]	12	1			T65	1		T290	1		T305	1
alert_ping_fail	alert[0x2a]	11	1			T125	1		T305	1		T296	1
alert_ping_fail	alert[0x2b]	8	1			T125	1		T289	1		T297	1
alert_ping_fail	alert[0x2c]	15	1			T65	1		T66	1		T307	1
alert_ping_fail	alert[0x2d]	15	1			T288	1		T292	1		T301	1
alert_ping_fail	alert[0x2e]	18	1			T21	1		T22	1		T23	1
alert_ping_fail	alert[0x2f]	10	1			T21	2		T23	1		T301	1
alert_ping_fail	alert[0x30]	15	1			T21	1		T22	2		T293	1
alert_ping_fail	alert[0x31]	7	1			T21	1		T301	1		T294	1
alert_ping_fail	alert[0x32]	12	1			T21	1		T125	1		T293	1
alert_ping_fail	alert[0x33]	13	1			T23	1		T125	1		T289	2
alert_ping_fail	alert[0x34]	8	1			T125	1		T292	1		T294	3
alert_ping_fail	alert[0x35]	9	1			T125	1		T301	1		T260	2
alert_ping_fail	alert[0x36]	10	1			T65	1		T301	1		T260	1
alert_ping_fail	alert[0x37]	13	1			T21	1		T260	1		T298	1
alert_ping_fail	alert[0x38]	10	1			T289	1		T292	1		T190	1
alert_ping_fail	alert[0x39]	7	1			T289	1		T308	1		T309	2
alert_ping_fail	alert[0x3a]	11	1			T65	1		T290	1		T293	1
alert_ping_fail	alert[0x3b]	11	1			T21	1		T296	1		T310	1
alert_ping_fail	alert[0x3c]	10	1			T289	1		T309	1		T311	1
alert_ping_fail	alert[0x3d]	9	1			T125	1		T290	1		T294	3
alert_ping_fail	alert[0x3e]	11	1			T21	1		T125	1		T301	1
alert_ping_fail	alert[0x3f]	3	1			T125	1		T297	1		T312	1
alert_ping_fail	alert[0x40]	3	1			T234	1		T303	1		T313	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	116158	1			T6	14		T31	17		T26	7194
alert_integrity_fail	class_i[0x1]	103110	1			T6	11		T31	7		T26	15
alert_integrity_fail	class_i[0x2]	106638	1			T5	2		T6	4		T26	8
alert_integrity_fail	class_i[0x3]	107193	1			T4	2		T5	18		T31	56
alert_ping_fail	class_i[0x0]	145	1			T22	2		T125	1		T290	2
alert_ping_fail	class_i[0x1]	174	1			T108	2		T125	4		T65	13
alert_ping_fail	class_i[0x2]	179	1			T12	1		T21	21		T20	1
alert_ping_fail	class_i[0x3]	176	1			T22	1		T23	19		T125	12