Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.49 99.99 98.71 92.05 100.00 100.00 99.30 99.40


Total test records in report: 824
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T181 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2866344281 Mar 07 01:10:04 PM PST 24 Mar 07 01:10:07 PM PST 24 24020363 ps
T148 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4046061717 Mar 07 01:09:36 PM PST 24 Mar 07 01:12:13 PM PST 24 8315908060 ps
T178 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3912324313 Mar 07 01:10:00 PM PST 24 Mar 07 01:10:05 PM PST 24 53685926 ps
T139 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1156518330 Mar 07 01:09:49 PM PST 24 Mar 07 01:28:18 PM PST 24 13332780107 ps
T771 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.479837015 Mar 07 01:10:17 PM PST 24 Mar 07 01:10:19 PM PST 24 12776790 ps
T772 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.705008762 Mar 07 01:09:53 PM PST 24 Mar 07 01:10:06 PM PST 24 176304429 ps
T773 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2869984108 Mar 07 01:09:49 PM PST 24 Mar 07 01:09:55 PM PST 24 110582275 ps
T774 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3413525331 Mar 07 01:09:54 PM PST 24 Mar 07 01:09:59 PM PST 24 232230130 ps
T775 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1321973255 Mar 07 01:09:39 PM PST 24 Mar 07 01:09:44 PM PST 24 53497550 ps
T776 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.764743193 Mar 07 01:10:01 PM PST 24 Mar 07 01:10:03 PM PST 24 10084871 ps
T149 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1852123172 Mar 07 01:10:00 PM PST 24 Mar 07 01:12:07 PM PST 24 7645393286 ps
T777 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3911499653 Mar 07 01:10:03 PM PST 24 Mar 07 01:10:05 PM PST 24 11156474 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.404238361 Mar 07 01:09:40 PM PST 24 Mar 07 01:09:46 PM PST 24 105286830 ps
T779 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2334549775 Mar 07 01:09:43 PM PST 24 Mar 07 01:09:51 PM PST 24 268542679 ps
T780 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1547833241 Mar 07 01:10:04 PM PST 24 Mar 07 01:10:05 PM PST 24 18746523 ps
T781 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1520711307 Mar 07 01:09:43 PM PST 24 Mar 07 01:14:30 PM PST 24 4595686427 ps
T187 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.885262256 Mar 07 01:10:02 PM PST 24 Mar 07 01:11:31 PM PST 24 12397418049 ps
T155 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3654728568 Mar 07 01:09:31 PM PST 24 Mar 07 01:18:40 PM PST 24 18394861411 ps
T782 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3719899441 Mar 07 01:10:00 PM PST 24 Mar 07 01:10:50 PM PST 24 2722164710 ps
T153 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2618519114 Mar 07 01:09:35 PM PST 24 Mar 07 01:14:42 PM PST 24 4230486526 ps
T783 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3454313879 Mar 07 01:09:50 PM PST 24 Mar 07 01:10:13 PM PST 24 340587992 ps
T164 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2280751294 Mar 07 01:09:50 PM PST 24 Mar 07 01:12:20 PM PST 24 2274619842 ps
T784 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.566026483 Mar 07 01:09:50 PM PST 24 Mar 07 01:09:52 PM PST 24 12786222 ps
T785 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3645461194 Mar 07 01:10:00 PM PST 24 Mar 07 01:10:08 PM PST 24 365938467 ps
T156 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.96356682 Mar 07 01:09:48 PM PST 24 Mar 07 01:26:28 PM PST 24 126797252986 ps
T162 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3497591465 Mar 07 01:10:02 PM PST 24 Mar 07 01:18:41 PM PST 24 12406902142 ps
T786 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1468786474 Mar 07 01:09:37 PM PST 24 Mar 07 01:09:44 PM PST 24 46340768 ps
T154 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2076810191 Mar 07 01:09:56 PM PST 24 Mar 07 01:20:44 PM PST 24 8765144441 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.936366197 Mar 07 01:09:40 PM PST 24 Mar 07 01:09:41 PM PST 24 16487622 ps
T788 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.290097474 Mar 07 01:10:15 PM PST 24 Mar 07 01:10:17 PM PST 24 6941250 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.149183626 Mar 07 01:09:50 PM PST 24 Mar 07 01:14:59 PM PST 24 28038075142 ps
T789 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2511885168 Mar 07 01:10:03 PM PST 24 Mar 07 01:10:05 PM PST 24 12633236 ps
T790 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1827342670 Mar 07 01:09:38 PM PST 24 Mar 07 01:09:39 PM PST 24 11863867 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1299096504 Mar 07 01:09:41 PM PST 24 Mar 07 01:09:43 PM PST 24 11106106 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1684286522 Mar 07 01:09:43 PM PST 24 Mar 07 01:09:54 PM PST 24 117140411 ps
T157 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3097332105 Mar 07 01:09:47 PM PST 24 Mar 07 01:12:46 PM PST 24 2824360865 ps
T793 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2627176810 Mar 07 01:09:35 PM PST 24 Mar 07 01:09:40 PM PST 24 214745190 ps
T794 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1606229596 Mar 07 01:10:04 PM PST 24 Mar 07 01:10:06 PM PST 24 25988652 ps
T795 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2552774167 Mar 07 01:09:36 PM PST 24 Mar 07 01:09:56 PM PST 24 1031212557 ps
T796 /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4224349063 Mar 07 01:09:44 PM PST 24 Mar 07 01:09:54 PM PST 24 69754841 ps
T797 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.803274401 Mar 07 01:10:00 PM PST 24 Mar 07 01:10:21 PM PST 24 304423905 ps
T798 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1138162522 Mar 07 01:09:45 PM PST 24 Mar 07 01:10:00 PM PST 24 365485719 ps
T799 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1285338774 Mar 07 01:10:05 PM PST 24 Mar 07 01:10:06 PM PST 24 15649700 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3983231958 Mar 07 01:09:36 PM PST 24 Mar 07 01:11:42 PM PST 24 6806718901 ps
T179 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1371591433 Mar 07 01:09:53 PM PST 24 Mar 07 01:11:11 PM PST 24 2426317424 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4285235168 Mar 07 01:09:39 PM PST 24 Mar 07 01:09:45 PM PST 24 230203863 ps
T802 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.556270171 Mar 07 01:09:33 PM PST 24 Mar 07 01:09:39 PM PST 24 56313341 ps
T803 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3231700916 Mar 07 01:09:46 PM PST 24 Mar 07 01:09:48 PM PST 24 8907505 ps
T161 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.156230173 Mar 07 01:09:29 PM PST 24 Mar 07 01:15:00 PM PST 24 2318082028 ps
T804 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1021690775 Mar 07 01:10:14 PM PST 24 Mar 07 01:10:15 PM PST 24 9563966 ps
T163 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1623229282 Mar 07 01:09:42 PM PST 24 Mar 07 01:15:58 PM PST 24 5437308586 ps
T805 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1078602877 Mar 07 01:09:45 PM PST 24 Mar 07 01:10:28 PM PST 24 1166897145 ps
T806 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.869253086 Mar 07 01:09:56 PM PST 24 Mar 07 01:10:10 PM PST 24 176059416 ps
T807 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1459027361 Mar 07 01:09:59 PM PST 24 Mar 07 01:10:01 PM PST 24 21562332 ps
T808 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1062883522 Mar 07 01:09:57 PM PST 24 Mar 07 01:10:22 PM PST 24 351334576 ps
T809 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2240913936 Mar 07 01:09:48 PM PST 24 Mar 07 01:09:57 PM PST 24 62115008 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3078045886 Mar 07 01:09:56 PM PST 24 Mar 07 01:10:14 PM PST 24 490655925 ps
T811 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2281999863 Mar 07 01:09:52 PM PST 24 Mar 07 01:10:01 PM PST 24 64969791 ps
T812 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2202982298 Mar 07 01:09:34 PM PST 24 Mar 07 01:12:46 PM PST 24 1541493798 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1016681489 Mar 07 01:09:40 PM PST 24 Mar 07 01:09:46 PM PST 24 153508300 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4284253823 Mar 07 01:09:48 PM PST 24 Mar 07 01:09:57 PM PST 24 473322317 ps
T158 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1698122009 Mar 07 01:09:48 PM PST 24 Mar 07 01:12:52 PM PST 24 6312499169 ps
T815 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2560763907 Mar 07 01:09:50 PM PST 24 Mar 07 01:14:32 PM PST 24 4261630748 ps
T816 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3875938356 Mar 07 01:09:56 PM PST 24 Mar 07 01:10:18 PM PST 24 495730231 ps
T160 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1316992018 Mar 07 01:09:59 PM PST 24 Mar 07 01:26:33 PM PST 24 50368689846 ps
T817 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2146297429 Mar 07 01:09:32 PM PST 24 Mar 07 01:09:38 PM PST 24 57524712 ps
T818 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2312999188 Mar 07 01:09:33 PM PST 24 Mar 07 01:09:58 PM PST 24 1131033068 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2360025157 Mar 07 01:09:38 PM PST 24 Mar 07 01:09:49 PM PST 24 142143856 ps
T820 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2020407491 Mar 07 01:09:36 PM PST 24 Mar 07 01:09:49 PM PST 24 200253760 ps
T171 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.578659584 Mar 07 01:09:50 PM PST 24 Mar 07 01:09:52 PM PST 24 59316916 ps
T821 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1928507886 Mar 07 01:09:38 PM PST 24 Mar 07 01:09:44 PM PST 24 92453454 ps
T822 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.608116013 Mar 07 01:10:02 PM PST 24 Mar 07 01:10:04 PM PST 24 29981471 ps
T823 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4035723354 Mar 07 01:09:39 PM PST 24 Mar 07 01:09:48 PM PST 24 323644330 ps
T824 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4187194748 Mar 07 01:10:01 PM PST 24 Mar 07 01:10:03 PM PST 24 8075884 ps

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3473331341
Short name T4
Test name
Test status
Simulation time 17585119942 ps
CPU time 574.85 seconds
Started Mar 07 01:52:24 PM PST 24
Finished Mar 07 02:01:59 PM PST 24
Peak memory 266516 kb
Host smart-b1a0ddc7-29e2-47c2-af90-ed74277b0dbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473331341 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3473331341
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.205398814
Short name T5
Test name
Test status
Simulation time 100181425881 ps
CPU time 3003.14 seconds
Started Mar 07 01:52:09 PM PST 24
Finished Mar 07 02:42:13 PM PST 24
Peak memory 290012 kb
Host smart-b326a7de-d462-4ac7-a1b3-db0315ee09b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205398814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.205398814
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2449024913
Short name T9
Test name
Test status
Simulation time 174899679 ps
CPU time 11.77 seconds
Started Mar 07 01:51:10 PM PST 24
Finished Mar 07 01:51:22 PM PST 24
Peak memory 273588 kb
Host smart-65fd683c-805b-4f01-81bd-5dfc55b99758
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2449024913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2449024913
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1745285851
Short name T167
Test name
Test status
Simulation time 353389134 ps
CPU time 18.21 seconds
Started Mar 07 01:09:52 PM PST 24
Finished Mar 07 01:10:11 PM PST 24
Peak memory 236824 kb
Host smart-234fbb54-1b30-4164-b75c-325c002c9a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1745285851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1745285851
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3720834519
Short name T34
Test name
Test status
Simulation time 14369710051 ps
CPU time 1570.47 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 02:17:41 PM PST 24
Peak memory 281936 kb
Host smart-e385ad1f-5ed7-47af-9508-7dedd33b9add
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720834519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3720834519
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.205202908
Short name T53
Test name
Test status
Simulation time 948163332997 ps
CPU time 6965.76 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 03:47:37 PM PST 24
Peak memory 322872 kb
Host smart-4176fbd6-6e2e-46a8-827f-ee3feedcd817
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205202908 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.205202908
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3371238643
Short name T20
Test name
Test status
Simulation time 74418058091 ps
CPU time 2637.16 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 02:35:12 PM PST 24
Peak memory 284572 kb
Host smart-6f1ca410-0e36-4853-97c5-9e042ca55d1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371238643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3371238643
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.550392064
Short name T137
Test name
Test status
Simulation time 16495957736 ps
CPU time 599.76 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:19:39 PM PST 24
Peak memory 265336 kb
Host smart-23cf7415-a56c-4132-8fd5-0a27ca92d536
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550392064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.550392064
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.2377100527
Short name T27
Test name
Test status
Simulation time 357304563364 ps
CPU time 5601.65 seconds
Started Mar 07 01:53:45 PM PST 24
Finished Mar 07 03:27:08 PM PST 24
Peak memory 322292 kb
Host smart-35a2207f-f59d-4c8a-b7bc-94d6d39a328d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377100527 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.2377100527
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.628372505
Short name T87
Test name
Test status
Simulation time 22514252379 ps
CPU time 1562.09 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 02:18:09 PM PST 24
Peak memory 273228 kb
Host smart-a429813f-22cc-4eef-82fa-d5c0bb1b4905
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628372505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.628372505
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.1156518330
Short name T139
Test name
Test status
Simulation time 13332780107 ps
CPU time 1108.78 seconds
Started Mar 07 01:09:49 PM PST 24
Finished Mar 07 01:28:18 PM PST 24
Peak memory 272384 kb
Host smart-2711ee7a-497c-4093-a4c8-ed15e064663c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156518330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.1156518330
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3671195940
Short name T82
Test name
Test status
Simulation time 820873462119 ps
CPU time 9709.98 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 04:33:43 PM PST 24
Peak memory 354996 kb
Host smart-5d7a2981-4bd5-4b67-92ee-109de9f9d5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671195940 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3671195940
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.959232696
Short name T107
Test name
Test status
Simulation time 1327961875 ps
CPU time 23.1 seconds
Started Mar 07 01:51:05 PM PST 24
Finished Mar 07 01:51:29 PM PST 24
Peak memory 240784 kb
Host smart-7ee78f65-5a13-41cc-94d2-d35ff0d3d0cc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=959232696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.959232696
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1260718378
Short name T141
Test name
Test status
Simulation time 4055000502 ps
CPU time 284.66 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:14:35 PM PST 24
Peak memory 265180 kb
Host smart-ed4ac613-418e-4990-9a88-2e900310ca11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1260718378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1260718378
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.497109829
Short name T98
Test name
Test status
Simulation time 21737644249 ps
CPU time 881.64 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:06:12 PM PST 24
Peak memory 272984 kb
Host smart-6bbddb27-b647-4df3-99a0-9d5cdcdaa604
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497109829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.497109829
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3910008330
Short name T126
Test name
Test status
Simulation time 68272802699 ps
CPU time 1242.8 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:30:23 PM PST 24
Peak memory 265300 kb
Host smart-c41d48fc-3131-4be5-9c86-d32f3e4dbf35
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910008330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3910008330
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2651166342
Short name T125
Test name
Test status
Simulation time 50293529960 ps
CPU time 518.61 seconds
Started Mar 07 01:51:23 PM PST 24
Finished Mar 07 02:00:01 PM PST 24
Peak memory 247884 kb
Host smart-1c067b3d-abfd-4d5d-bce1-7473a7850b39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651166342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2651166342
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3880120134
Short name T108
Test name
Test status
Simulation time 192053880255 ps
CPU time 2980.95 seconds
Started Mar 07 01:53:24 PM PST 24
Finished Mar 07 02:43:05 PM PST 24
Peak memory 289216 kb
Host smart-00ee8d82-95a5-48d0-b65c-91d34077b2e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880120134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3880120134
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3524255238
Short name T331
Test name
Test status
Simulation time 53187314 ps
CPU time 1.43 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:38 PM PST 24
Peak memory 236436 kb
Host smart-88faf457-8a50-48af-a3d8-d7ce349b97ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3524255238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3524255238
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2535977560
Short name T135
Test name
Test status
Simulation time 5837089622 ps
CPU time 310.25 seconds
Started Mar 07 01:09:37 PM PST 24
Finished Mar 07 01:14:48 PM PST 24
Peak memory 265248 kb
Host smart-b3031e64-6e5c-4d7f-9980-5b4daac2f16d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535977560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2535977560
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3407815419
Short name T21
Test name
Test status
Simulation time 22509799847 ps
CPU time 632.34 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 02:02:59 PM PST 24
Peak memory 247688 kb
Host smart-16df6eab-9888-45b9-a12b-4e3ad80eda89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407815419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3407815419
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2074108905
Short name T33
Test name
Test status
Simulation time 52806870081 ps
CPU time 4778.89 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 03:11:01 PM PST 24
Peak memory 322188 kb
Host smart-62d357c3-7961-48ec-9bd4-3e04305e2b6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074108905 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2074108905
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1372172278
Short name T12
Test name
Test status
Simulation time 39110156092 ps
CPU time 1824.94 seconds
Started Mar 07 01:51:36 PM PST 24
Finished Mar 07 02:22:01 PM PST 24
Peak memory 273572 kb
Host smart-b51a7cab-7464-4e2e-9e76-a784a23ce798
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372172278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1372172278
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.44854588
Short name T133
Test name
Test status
Simulation time 12580319676 ps
CPU time 628.39 seconds
Started Mar 07 01:09:52 PM PST 24
Finished Mar 07 01:20:21 PM PST 24
Peak memory 265288 kb
Host smart-ccd297e6-466b-41c4-a757-af656bdfbe10
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44854588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.44854588
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.149183626
Short name T159
Test name
Test status
Simulation time 28038075142 ps
CPU time 308.91 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:14:59 PM PST 24
Peak memory 265188 kb
Host smart-d30d1f73-9be1-4967-834e-5e12e607b53f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=149183626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.149183626
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1635850737
Short name T121
Test name
Test status
Simulation time 48704728943 ps
CPU time 1584.51 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 02:18:52 PM PST 24
Peak memory 282460 kb
Host smart-be0d8142-5a7c-4474-9c4a-514832e2f8a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635850737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1635850737
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.491551756
Short name T289
Test name
Test status
Simulation time 77640758210 ps
CPU time 476.76 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:59:21 PM PST 24
Peak memory 247984 kb
Host smart-2692caee-5eb7-41a4-a09c-3f907ba8c9ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491551756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.491551756
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1415845605
Short name T120
Test name
Test status
Simulation time 162793474787 ps
CPU time 7559.48 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 03:58:02 PM PST 24
Peak memory 394888 kb
Host smart-f62ff8de-cbf6-4b43-bcc2-2d18394bf130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415845605 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1415845605
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2448833652
Short name T144
Test name
Test status
Simulation time 3098033967 ps
CPU time 220.77 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:13:42 PM PST 24
Peak memory 273036 kb
Host smart-0834d839-694d-4674-9f40-06c3c2dab0f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2448833652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2448833652
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1749726155
Short name T307
Test name
Test status
Simulation time 25334057487 ps
CPU time 1549.33 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 02:17:18 PM PST 24
Peak memory 273156 kb
Host smart-fa159590-9508-46c5-938f-7732998955fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749726155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1749726155
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.4068872684
Short name T15
Test name
Test status
Simulation time 28914188120 ps
CPU time 1462.63 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 02:16:05 PM PST 24
Peak memory 273576 kb
Host smart-08ea79ed-6cc2-44ed-9276-bbc1bfdf9369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068872684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.4068872684
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2592397561
Short name T704
Test name
Test status
Simulation time 14643190 ps
CPU time 1.31 seconds
Started Mar 07 01:09:51 PM PST 24
Finished Mar 07 01:09:53 PM PST 24
Peak memory 236300 kb
Host smart-4f67614f-5535-4015-9e8c-1e769b244937
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2592397561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2592397561
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2632626850
Short name T287
Test name
Test status
Simulation time 74470532494 ps
CPU time 1323.81 seconds
Started Mar 07 01:52:00 PM PST 24
Finished Mar 07 02:14:04 PM PST 24
Peak memory 284296 kb
Host smart-64781781-f982-42d6-9b36-078a610d9c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632626850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2632626850
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.4165726481
Short name T234
Test name
Test status
Simulation time 20263621922 ps
CPU time 200.69 seconds
Started Mar 07 01:52:42 PM PST 24
Finished Mar 07 01:56:03 PM PST 24
Peak memory 247856 kb
Host smart-fee36f9f-1ad3-4025-bfd2-cc6fdd1d0263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165726481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.4165726481
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4251387190
Short name T231
Test name
Test status
Simulation time 46535566437 ps
CPU time 2594.64 seconds
Started Mar 07 01:52:44 PM PST 24
Finished Mar 07 02:35:59 PM PST 24
Peak memory 287696 kb
Host smart-cd9019c4-6224-4d81-ac15-8be32c1f8c30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251387190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4251387190
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.2066361894
Short name T77
Test name
Test status
Simulation time 107350060553 ps
CPU time 1650.17 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 02:19:57 PM PST 24
Peak memory 289936 kb
Host smart-060d3113-7f47-497a-bdd6-8184cfe979be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066361894 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.2066361894
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3787309443
Short name T131
Test name
Test status
Simulation time 15251186170 ps
CPU time 1142.35 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:28:50 PM PST 24
Peak memory 265232 kb
Host smart-5acff9c4-c80b-4234-9699-d6d1e347ec43
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787309443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3787309443
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3928219452
Short name T294
Test name
Test status
Simulation time 15976395500 ps
CPU time 655.94 seconds
Started Mar 07 01:51:10 PM PST 24
Finished Mar 07 02:02:06 PM PST 24
Peak memory 247312 kb
Host smart-1f4aed2f-4b9c-4739-8d46-23d509c7067f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928219452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3928219452
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1759879347
Short name T247
Test name
Test status
Simulation time 1028277184 ps
CPU time 23.5 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 01:51:50 PM PST 24
Peak memory 255452 kb
Host smart-86661722-e60a-4f1c-8b4c-c01057d04faf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17598
79347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1759879347
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2173751843
Short name T136
Test name
Test status
Simulation time 6461436202 ps
CPU time 484.7 seconds
Started Mar 07 01:09:54 PM PST 24
Finished Mar 07 01:18:00 PM PST 24
Peak memory 268468 kb
Host smart-7f2b3363-4860-4954-952b-4ca674a37ae9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173751843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2173751843
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2866344281
Short name T181
Test name
Test status
Simulation time 24020363 ps
CPU time 2.34 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:07 PM PST 24
Peak memory 236464 kb
Host smart-6cdc528d-fbf3-4529-a453-03f0bb58245f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2866344281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2866344281
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1172855328
Short name T19
Test name
Test status
Simulation time 31087425131 ps
CPU time 3305.07 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 02:46:24 PM PST 24
Peak memory 322128 kb
Host smart-87219eef-75d8-4cf4-9f25-da2286952485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172855328 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1172855328
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.92359684
Short name T492
Test name
Test status
Simulation time 30683674560 ps
CPU time 1308.51 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 02:13:16 PM PST 24
Peak memory 283328 kb
Host smart-a12d1c91-cc69-4598-ae1e-7aea36c9afe3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92359684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.92359684
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1826564479
Short name T311
Test name
Test status
Simulation time 19507874992 ps
CPU time 435.95 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:59:05 PM PST 24
Peak memory 247916 kb
Host smart-164880f7-c66e-4437-8d2d-c541e804ee91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826564479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1826564479
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1155786016
Short name T489
Test name
Test status
Simulation time 42719824291 ps
CPU time 3147.12 seconds
Started Mar 07 01:51:55 PM PST 24
Finished Mar 07 02:44:23 PM PST 24
Peak memory 300528 kb
Host smart-432c5ee1-3124-422d-a5bd-27e1b53a1d2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155786016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1155786016
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2387682855
Short name T113
Test name
Test status
Simulation time 94110112328 ps
CPU time 4614.89 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 03:08:44 PM PST 24
Peak memory 314700 kb
Host smart-eea4d51a-0b98-4514-a380-d0bcd638f6d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387682855 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2387682855
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3977930914
Short name T94
Test name
Test status
Simulation time 36857914712 ps
CPU time 2249.31 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 02:28:49 PM PST 24
Peak memory 273952 kb
Host smart-f8e3fb24-89dd-4a3e-93a0-0d001ef9c9b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977930914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3977930914
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1852123172
Short name T149
Test name
Test status
Simulation time 7645393286 ps
CPU time 125.86 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:12:07 PM PST 24
Peak memory 265256 kb
Host smart-b9087400-a7b4-480e-8e2e-ede62663e4a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1852123172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1852123172
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1603182881
Short name T31
Test name
Test status
Simulation time 29728569961 ps
CPU time 2092.16 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:26:22 PM PST 24
Peak memory 287928 kb
Host smart-c8de1198-4647-4df5-94d4-7f64f5610f09
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603182881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1603182881
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2375648668
Short name T38
Test name
Test status
Simulation time 205201709 ps
CPU time 3.82 seconds
Started Mar 07 01:51:11 PM PST 24
Finished Mar 07 01:51:15 PM PST 24
Peak memory 249072 kb
Host smart-e65ad25d-8a45-4ff7-b977-11383fd4b66b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2375648668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2375648668
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4137273371
Short name T204
Test name
Test status
Simulation time 116960598 ps
CPU time 3.33 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:23 PM PST 24
Peak memory 249112 kb
Host smart-e3786a7f-286f-4e6e-8322-841d4a9439cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4137273371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4137273371
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.4094908376
Short name T203
Test name
Test status
Simulation time 38856190 ps
CPU time 3.25 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:32 PM PST 24
Peak memory 249168 kb
Host smart-e2a809b7-7a03-45ae-b7d6-02661fe3550f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4094908376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.4094908376
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2738681913
Short name T285
Test name
Test status
Simulation time 47258402804 ps
CPU time 1092.53 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 02:09:46 PM PST 24
Peak memory 283704 kb
Host smart-5a497996-b0d4-4778-88ae-252fe6c726ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738681913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2738681913
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2120164386
Short name T188
Test name
Test status
Simulation time 56162408309 ps
CPU time 923.93 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 02:06:57 PM PST 24
Peak memory 273704 kb
Host smart-971422ed-de96-42ed-9b78-dbadfc44acd3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120164386 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2120164386
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.979880999
Short name T251
Test name
Test status
Simulation time 2596670333 ps
CPU time 114.91 seconds
Started Mar 07 01:51:40 PM PST 24
Finished Mar 07 01:53:35 PM PST 24
Peak memory 247832 kb
Host smart-c3f5f047-3204-4eeb-be8a-8254201067e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979880999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.979880999
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3451159858
Short name T244
Test name
Test status
Simulation time 838596061 ps
CPU time 31.23 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:52:02 PM PST 24
Peak memory 248956 kb
Host smart-281c5896-53a9-4962-b892-0faac8ded9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34511
59858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3451159858
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3774082592
Short name T104
Test name
Test status
Simulation time 66046763868 ps
CPU time 1378.22 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 02:14:15 PM PST 24
Peak memory 289264 kb
Host smart-dca5ac49-2f58-4d56-b306-f29ca2a0979a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774082592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3774082592
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.551614757
Short name T273
Test name
Test status
Simulation time 1093573686 ps
CPU time 32.66 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:53:11 PM PST 24
Peak memory 255644 kb
Host smart-7a1b5bf2-caab-4965-94e0-15f5c944d688
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55161
4757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.551614757
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1998752660
Short name T119
Test name
Test status
Simulation time 70765043290 ps
CPU time 1726.43 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 02:20:45 PM PST 24
Peak memory 289420 kb
Host smart-c3703990-8daa-4cbc-92bf-aea77f441759
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998752660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1998752660
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1698122009
Short name T158
Test name
Test status
Simulation time 6312499169 ps
CPU time 183.14 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:12:52 PM PST 24
Peak memory 265336 kb
Host smart-daf539fb-4d9e-48e7-8bf3-34f634ef235f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1698122009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1698122009
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3814714512
Short name T172
Test name
Test status
Simulation time 2211842970 ps
CPU time 69.24 seconds
Started Mar 07 01:09:51 PM PST 24
Finished Mar 07 01:11:00 PM PST 24
Peak memory 239284 kb
Host smart-6dc1850c-19a4-42cc-886b-5a3be2c46e08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3814714512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3814714512
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2744765932
Short name T702
Test name
Test status
Simulation time 11872233 ps
CPU time 1.69 seconds
Started Mar 07 01:09:32 PM PST 24
Finished Mar 07 01:09:35 PM PST 24
Peak memory 236424 kb
Host smart-739344b9-65ed-49e2-b911-4ae2e81a0404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744765932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2744765932
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.484704690
Short name T101
Test name
Test status
Simulation time 29081202403 ps
CPU time 2059.37 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 02:25:27 PM PST 24
Peak memory 287872 kb
Host smart-1ed64538-6e7b-45b3-bf28-256cfeae957e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484704690 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.484704690
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2730659771
Short name T514
Test name
Test status
Simulation time 6598082041 ps
CPU time 288.57 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:56:16 PM PST 24
Peak memory 247864 kb
Host smart-e02e44c5-bf0e-47ed-a42c-4e3369b6b588
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730659771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2730659771
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.2761584716
Short name T83
Test name
Test status
Simulation time 406098221735 ps
CPU time 7581.97 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 03:57:53 PM PST 24
Peak memory 338168 kb
Host smart-176d0a37-3ed3-4f6e-a8b8-edcb10611469
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761584716 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.2761584716
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3460545599
Short name T626
Test name
Test status
Simulation time 27108944801 ps
CPU time 1156.83 seconds
Started Mar 07 01:51:48 PM PST 24
Finished Mar 07 02:11:05 PM PST 24
Peak memory 289348 kb
Host smart-9e8addfd-bcc1-42de-8f63-56806e1ae9e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460545599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3460545599
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.97770855
Short name T59
Test name
Test status
Simulation time 62120202746 ps
CPU time 3593.31 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 02:51:51 PM PST 24
Peak memory 290008 kb
Host smart-78ed042c-30de-4c7b-b59c-6207b11d61c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97770855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_hand
ler_stress_all.97770855
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.1802762216
Short name T266
Test name
Test status
Simulation time 286059457199 ps
CPU time 4235.88 seconds
Started Mar 07 01:51:39 PM PST 24
Finished Mar 07 03:02:16 PM PST 24
Peak memory 305628 kb
Host smart-1a127191-f5b9-4532-9966-923e1900a318
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802762216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.1802762216
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1361741235
Short name T195
Test name
Test status
Simulation time 41273551943 ps
CPU time 828.65 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 02:05:47 PM PST 24
Peak memory 265420 kb
Host smart-aa20acf8-6ce9-4195-95e0-72e3571c3d21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361741235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1361741235
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1156404716
Short name T282
Test name
Test status
Simulation time 196500000 ps
CPU time 25.81 seconds
Started Mar 07 01:51:55 PM PST 24
Finished Mar 07 01:52:21 PM PST 24
Peak memory 247252 kb
Host smart-6b1b4668-7bcc-4393-836d-957549093534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11564
04716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1156404716
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3761054735
Short name T42
Test name
Test status
Simulation time 288134807 ps
CPU time 22.51 seconds
Started Mar 07 01:52:07 PM PST 24
Finished Mar 07 01:52:31 PM PST 24
Peak memory 254124 kb
Host smart-60cabc76-c7a9-481b-99df-cf2a456769ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
54735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3761054735
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1986540343
Short name T225
Test name
Test status
Simulation time 15053668332 ps
CPU time 713.93 seconds
Started Mar 07 01:52:20 PM PST 24
Finished Mar 07 02:04:14 PM PST 24
Peak memory 267596 kb
Host smart-d1e2d7e6-ca55-48f9-b4bc-03e916ba86a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986540343 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1986540343
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2418650006
Short name T264
Test name
Test status
Simulation time 1006629146 ps
CPU time 18.09 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 01:53:22 PM PST 24
Peak memory 254616 kb
Host smart-710c9ed0-4313-4ad8-811d-f9e1a929a083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24186
50006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2418650006
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2997311449
Short name T230
Test name
Test status
Simulation time 450836415 ps
CPU time 8.89 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:35 PM PST 24
Peak memory 249664 kb
Host smart-0edf3b72-73d6-4124-ad42-d85c2b7df1c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29973
11449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2997311449
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3797266669
Short name T68
Test name
Test status
Simulation time 53976800905 ps
CPU time 1327.31 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 02:13:30 PM PST 24
Peak memory 284892 kb
Host smart-65c57277-55e6-4b8a-a4b3-646afce8cc5c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797266669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3797266669
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3959229504
Short name T13
Test name
Test status
Simulation time 164929290046 ps
CPU time 2529.36 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 02:33:59 PM PST 24
Peak memory 290028 kb
Host smart-40c74500-b86c-4e3a-b67c-1fe131c11c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959229504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3959229504
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2618519114
Short name T153
Test name
Test status
Simulation time 4230486526 ps
CPU time 305.82 seconds
Started Mar 07 01:09:35 PM PST 24
Finished Mar 07 01:14:42 PM PST 24
Peak memory 271764 kb
Host smart-f2f22161-71ea-4bbe-ad5f-c71bca36fd2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2618519114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2618519114
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3912324313
Short name T178
Test name
Test status
Simulation time 53685926 ps
CPU time 3.98 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 235540 kb
Host smart-4a2be7cd-35b3-4f9a-a5ab-4dd6c72e0e43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3912324313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3912324313
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.329325520
Short name T118
Test name
Test status
Simulation time 18796061759 ps
CPU time 1580.71 seconds
Started Mar 07 01:52:29 PM PST 24
Finished Mar 07 02:18:50 PM PST 24
Peak memory 290048 kb
Host smart-ac710914-b4a1-485d-949b-30d8cd323ff2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329325520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.329325520
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.578659584
Short name T171
Test name
Test status
Simulation time 59316916 ps
CPU time 2.61 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:09:52 PM PST 24
Peak memory 237360 kb
Host smart-a20562ee-f675-4005-b8a1-e399a86a6a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=578659584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.578659584
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1212540778
Short name T176
Test name
Test status
Simulation time 183422826 ps
CPU time 3.79 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:43 PM PST 24
Peak memory 236372 kb
Host smart-b8ba6591-279b-4155-8561-18010811dcef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1212540778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1212540778
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4048326325
Short name T165
Test name
Test status
Simulation time 1714100134 ps
CPU time 37.67 seconds
Started Mar 07 01:09:42 PM PST 24
Finished Mar 07 01:10:20 PM PST 24
Peak memory 240344 kb
Host smart-0d97bd2f-c0f4-4a37-ab80-e28603b772c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4048326325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4048326325
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3097332105
Short name T157
Test name
Test status
Simulation time 2824360865 ps
CPU time 179.41 seconds
Started Mar 07 01:09:47 PM PST 24
Finished Mar 07 01:12:46 PM PST 24
Peak memory 256056 kb
Host smart-1a18eb47-50b7-417a-902d-d8a0087b435b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3097332105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3097332105
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3362853093
Short name T140
Test name
Test status
Simulation time 13334308605 ps
CPU time 1070.22 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:27:41 PM PST 24
Peak memory 265300 kb
Host smart-fe188a25-5739-401d-995c-850daae8cd40
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362853093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3362853093
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2832295783
Short name T173
Test name
Test status
Simulation time 36043445 ps
CPU time 3.09 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:09:56 PM PST 24
Peak memory 236216 kb
Host smart-2dfe9351-b66e-4e9e-ac59-c52c51245dc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2832295783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2832295783
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1371591433
Short name T179
Test name
Test status
Simulation time 2426317424 ps
CPU time 77.92 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:11:11 PM PST 24
Peak memory 240200 kb
Host smart-2db33447-3b75-4392-a3b9-8db9632b3446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1371591433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1371591433
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.945294492
Short name T127
Test name
Test status
Simulation time 2870401422 ps
CPU time 172.95 seconds
Started Mar 07 01:09:52 PM PST 24
Finished Mar 07 01:12:45 PM PST 24
Peak memory 265340 kb
Host smart-45a6d9ac-4175-45d7-aec4-dab81d7b3532
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=945294492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.945294492
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.885262256
Short name T187
Test name
Test status
Simulation time 12397418049 ps
CPU time 88.85 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:11:31 PM PST 24
Peak memory 237724 kb
Host smart-1d819e08-0bdd-4023-b29d-ae03c1efcae4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=885262256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.885262256
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1196554064
Short name T174
Test name
Test status
Simulation time 363841333 ps
CPU time 45.48 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:10:25 PM PST 24
Peak memory 240248 kb
Host smart-5915c91c-131e-4a4d-acc0-00e71975eab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1196554064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1196554064
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3602880146
Short name T177
Test name
Test status
Simulation time 1648457750 ps
CPU time 34.23 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:10:12 PM PST 24
Peak memory 244852 kb
Host smart-fdf857c0-f5c3-46de-8133-1e4e2d1f4fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3602880146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3602880146
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.35588560
Short name T180
Test name
Test status
Simulation time 483018241 ps
CPU time 37.34 seconds
Started Mar 07 01:09:31 PM PST 24
Finished Mar 07 01:10:09 PM PST 24
Peak memory 236372 kb
Host smart-518d68d2-5fa0-4473-ba6e-130179cc0178
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=35588560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.35588560
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2181460448
Short name T184
Test name
Test status
Simulation time 609693401 ps
CPU time 26.35 seconds
Started Mar 07 01:09:32 PM PST 24
Finished Mar 07 01:09:59 PM PST 24
Peak memory 240324 kb
Host smart-5be975db-486a-4c77-b8c7-6299fdb91c65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2181460448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2181460448
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3910906702
Short name T183
Test name
Test status
Simulation time 63222021 ps
CPU time 3.27 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:09:49 PM PST 24
Peak memory 236416 kb
Host smart-ec870004-afc8-4fa8-8585-791ecfc294d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3910906702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3910906702
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3557608867
Short name T175
Test name
Test status
Simulation time 34296665 ps
CPU time 2.28 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:42 PM PST 24
Peak memory 236512 kb
Host smart-f16d8d00-d627-480b-8bbf-bf455deb6771
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3557608867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3557608867
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1370767211
Short name T185
Test name
Test status
Simulation time 169315534 ps
CPU time 4.05 seconds
Started Mar 07 01:09:46 PM PST 24
Finished Mar 07 01:09:50 PM PST 24
Peak memory 236392 kb
Host smart-ad3a5c34-3fdb-48ac-8d69-0d515395229f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1370767211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1370767211
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1075855799
Short name T749
Test name
Test status
Simulation time 1105451704 ps
CPU time 160.4 seconds
Started Mar 07 01:09:32 PM PST 24
Finished Mar 07 01:12:13 PM PST 24
Peak memory 238196 kb
Host smart-49cd22ed-7c0f-40a2-8f08-1b3e978c30a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1075855799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1075855799
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.4048822493
Short name T339
Test name
Test status
Simulation time 1670191743 ps
CPU time 103.98 seconds
Started Mar 07 01:09:29 PM PST 24
Finished Mar 07 01:11:15 PM PST 24
Peak memory 240244 kb
Host smart-2be80f94-babb-494c-999d-fd810e500a21
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4048822493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.4048822493
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.556270171
Short name T802
Test name
Test status
Simulation time 56313341 ps
CPU time 5.59 seconds
Started Mar 07 01:09:33 PM PST 24
Finished Mar 07 01:09:39 PM PST 24
Peak memory 240248 kb
Host smart-e05f50a8-aa51-429f-b796-bc24c0c46c19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=556270171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.556270171
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.150329098
Short name T765
Test name
Test status
Simulation time 97921920 ps
CPU time 7.9 seconds
Started Mar 07 01:09:30 PM PST 24
Finished Mar 07 01:09:39 PM PST 24
Peak memory 237596 kb
Host smart-1c7e3b8a-f14a-4d82-8854-ce2a436ec13b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150329098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.150329098
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2421295047
Short name T770
Test name
Test status
Simulation time 421782509 ps
CPU time 6.36 seconds
Started Mar 07 01:09:31 PM PST 24
Finished Mar 07 01:09:38 PM PST 24
Peak memory 236336 kb
Host smart-3d3613d1-e629-4146-bafa-228679249b99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2421295047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2421295047
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1513882517
Short name T755
Test name
Test status
Simulation time 273749926 ps
CPU time 20.09 seconds
Started Mar 07 01:09:30 PM PST 24
Finished Mar 07 01:09:52 PM PST 24
Peak memory 240344 kb
Host smart-6bcd18c9-afab-405a-9ccc-15f18cd76444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1513882517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1513882517
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3196787992
Short name T143
Test name
Test status
Simulation time 2400012541 ps
CPU time 166.19 seconds
Started Mar 07 01:09:35 PM PST 24
Finished Mar 07 01:12:21 PM PST 24
Peak memory 257004 kb
Host smart-62ade0b0-0515-4c11-8ef2-ac479785db72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3196787992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3196787992
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.156230173
Short name T161
Test name
Test status
Simulation time 2318082028 ps
CPU time 328.1 seconds
Started Mar 07 01:09:29 PM PST 24
Finished Mar 07 01:15:00 PM PST 24
Peak memory 265220 kb
Host smart-e1c83a7d-e681-43fb-b22a-26b038fcab85
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156230173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.156230173
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1434775884
Short name T699
Test name
Test status
Simulation time 82124478 ps
CPU time 5.7 seconds
Started Mar 07 01:09:30 PM PST 24
Finished Mar 07 01:09:37 PM PST 24
Peak memory 248268 kb
Host smart-fae1ffd2-cdb6-47f9-9865-13f9fe90e8ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434775884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1434775884
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2202982298
Short name T812
Test name
Test status
Simulation time 1541493798 ps
CPU time 190.89 seconds
Started Mar 07 01:09:34 PM PST 24
Finished Mar 07 01:12:46 PM PST 24
Peak memory 240248 kb
Host smart-0791d7aa-1fbb-4053-8dc8-da4e3b89ef38
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2202982298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2202982298
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.676080099
Short name T758
Test name
Test status
Simulation time 18134053293 ps
CPU time 180.89 seconds
Started Mar 07 01:09:32 PM PST 24
Finished Mar 07 01:12:34 PM PST 24
Peak memory 240324 kb
Host smart-c762fa7e-d5cf-4ca0-acb0-e7389f7e9cd7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=676080099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.676080099
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.2146297429
Short name T817
Test name
Test status
Simulation time 57524712 ps
CPU time 5.26 seconds
Started Mar 07 01:09:32 PM PST 24
Finished Mar 07 01:09:38 PM PST 24
Peak memory 240204 kb
Host smart-6f1db4e9-af86-4429-9e56-72402336916a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2146297429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.2146297429
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1734243000
Short name T707
Test name
Test status
Simulation time 106950076 ps
CPU time 8.61 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 239684 kb
Host smart-a0d139ff-373e-482c-b99c-776767fb585e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734243000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1734243000
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2627176810
Short name T793
Test name
Test status
Simulation time 214745190 ps
CPU time 4.97 seconds
Started Mar 07 01:09:35 PM PST 24
Finished Mar 07 01:09:40 PM PST 24
Peak memory 239336 kb
Host smart-5e38d8f6-9b8e-4b65-9f70-8523eb6dfd8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2627176810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2627176810
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2567234258
Short name T170
Test name
Test status
Simulation time 9840704 ps
CPU time 1.43 seconds
Started Mar 07 01:09:31 PM PST 24
Finished Mar 07 01:09:34 PM PST 24
Peak memory 235460 kb
Host smart-49f5a18d-d767-43d5-afc3-96cc52d3777f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2567234258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2567234258
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2312999188
Short name T818
Test name
Test status
Simulation time 1131033068 ps
CPU time 25.09 seconds
Started Mar 07 01:09:33 PM PST 24
Finished Mar 07 01:09:58 PM PST 24
Peak memory 244592 kb
Host smart-f2d1f1b4-da8f-4531-ae83-bd84bd43853f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2312999188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2312999188
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3005143976
Short name T150
Test name
Test status
Simulation time 1555480313 ps
CPU time 111.39 seconds
Started Mar 07 01:09:33 PM PST 24
Finished Mar 07 01:11:25 PM PST 24
Peak memory 256280 kb
Host smart-99fca18b-85da-40b6-b95a-dea1b1965333
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3005143976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3005143976
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3654728568
Short name T155
Test name
Test status
Simulation time 18394861411 ps
CPU time 547.44 seconds
Started Mar 07 01:09:31 PM PST 24
Finished Mar 07 01:18:40 PM PST 24
Peak memory 265032 kb
Host smart-c4acb7bf-3329-4577-bf49-b50b1ec92fdd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654728568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3654728568
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.919036196
Short name T740
Test name
Test status
Simulation time 177510149 ps
CPU time 12.84 seconds
Started Mar 07 01:09:33 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 252028 kb
Host smart-bbef0970-363b-4809-9191-2a2e16a51dbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=919036196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.919036196
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2905147113
Short name T340
Test name
Test status
Simulation time 564943606 ps
CPU time 11.63 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:10:00 PM PST 24
Peak memory 242528 kb
Host smart-38002974-7efd-4018-85e9-06996fd83411
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905147113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2905147113
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.220143522
Short name T731
Test name
Test status
Simulation time 92483161 ps
CPU time 5.05 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:09:50 PM PST 24
Peak memory 236336 kb
Host smart-3a6e8fc7-aa23-420d-b161-39a632255e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=220143522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.220143522
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3656977621
Short name T169
Test name
Test status
Simulation time 10647605 ps
CPU time 1.56 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 236400 kb
Host smart-ab8d5313-9a33-4730-a486-e464c0f0bd39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656977621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3656977621
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2473394259
Short name T744
Test name
Test status
Simulation time 362254911 ps
CPU time 24.88 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:10:13 PM PST 24
Peak memory 244616 kb
Host smart-b14f2dc7-a803-4f46-8e78-c7b7ac428354
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2473394259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2473394259
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3380470461
Short name T750
Test name
Test status
Simulation time 264803672 ps
CPU time 21.01 seconds
Started Mar 07 01:09:49 PM PST 24
Finished Mar 07 01:10:10 PM PST 24
Peak memory 248268 kb
Host smart-1be1e248-ae1f-4740-8c87-3bc5cb2306d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3380470461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3380470461
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.4029198487
Short name T741
Test name
Test status
Simulation time 152564818 ps
CPU time 13.9 seconds
Started Mar 07 01:09:46 PM PST 24
Finished Mar 07 01:10:01 PM PST 24
Peak memory 250652 kb
Host smart-1f733592-34c0-41b3-ae8b-6c1fc1f6ace1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029198487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.4029198487
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3857948817
Short name T733
Test name
Test status
Simulation time 173601361 ps
CPU time 4.69 seconds
Started Mar 07 01:09:57 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 235432 kb
Host smart-0fe7703e-7613-4baf-a1be-0e5cf7b42c30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3857948817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3857948817
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2339613419
Short name T334
Test name
Test status
Simulation time 15411717 ps
CPU time 1.84 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:09:50 PM PST 24
Peak memory 234556 kb
Host smart-c4393acf-940e-4b52-a4ba-e3fefa979dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2339613419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2339613419
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3875938356
Short name T816
Test name
Test status
Simulation time 495730231 ps
CPU time 19.72 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:10:18 PM PST 24
Peak memory 243752 kb
Host smart-1ec024a3-282e-4ce1-b52f-d5bf77deb7ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3875938356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3875938356
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1305143578
Short name T710
Test name
Test status
Simulation time 52863225 ps
CPU time 6.55 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:09:55 PM PST 24
Peak memory 248416 kb
Host smart-a4d69044-e070-4032-aeee-3501a1cbfd3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1305143578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1305143578
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2869984108
Short name T773
Test name
Test status
Simulation time 110582275 ps
CPU time 5.59 seconds
Started Mar 07 01:09:49 PM PST 24
Finished Mar 07 01:09:55 PM PST 24
Peak memory 238492 kb
Host smart-88b705a1-5f69-4514-9491-95bb1bbdaa4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869984108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2869984108
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.621008831
Short name T736
Test name
Test status
Simulation time 124510045 ps
CPU time 9.33 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:10:02 PM PST 24
Peak memory 236168 kb
Host smart-3d42e34b-634f-4978-8793-b0ce132767df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=621008831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.621008831
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3231700916
Short name T803
Test name
Test status
Simulation time 8907505 ps
CPU time 1.28 seconds
Started Mar 07 01:09:46 PM PST 24
Finished Mar 07 01:09:48 PM PST 24
Peak memory 236340 kb
Host smart-7c4a2b38-9505-4864-aaf5-40509ec396d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3231700916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3231700916
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3454313879
Short name T783
Test name
Test status
Simulation time 340587992 ps
CPU time 22.83 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:10:13 PM PST 24
Peak memory 240312 kb
Host smart-8428d1e0-c6a2-4e9e-84c1-ca03875c585c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3454313879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3454313879
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2280751294
Short name T164
Test name
Test status
Simulation time 2274619842 ps
CPU time 149.59 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:12:20 PM PST 24
Peak memory 256984 kb
Host smart-0541d11c-2926-44ca-ac75-c283f111778c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2280751294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2280751294
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3958827631
Short name T725
Test name
Test status
Simulation time 214834108 ps
CPU time 14.52 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:10:04 PM PST 24
Peak memory 248480 kb
Host smart-fe714498-6e73-4af3-bf4b-c25c3e5635df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3958827631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3958827631
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3081712249
Short name T335
Test name
Test status
Simulation time 132835057 ps
CPU time 10.33 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:10:08 PM PST 24
Peak memory 240412 kb
Host smart-0c607808-3a37-4382-9b77-3d10973763f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081712249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3081712249
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2040376961
Short name T757
Test name
Test status
Simulation time 59508506 ps
CPU time 4.39 seconds
Started Mar 07 01:09:52 PM PST 24
Finished Mar 07 01:09:57 PM PST 24
Peak memory 235584 kb
Host smart-47d60422-1f23-4f65-a864-ef129a718db1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2040376961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2040376961
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.566026483
Short name T784
Test name
Test status
Simulation time 12786222 ps
CPU time 1.66 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:09:52 PM PST 24
Peak memory 236416 kb
Host smart-5af1f83c-e3ad-49b1-8ab8-796721977f19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=566026483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.566026483
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1062883522
Short name T808
Test name
Test status
Simulation time 351334576 ps
CPU time 24.08 seconds
Started Mar 07 01:09:57 PM PST 24
Finished Mar 07 01:10:22 PM PST 24
Peak memory 244572 kb
Host smart-2add399e-a6a7-493f-b094-3192bcc427a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1062883522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1062883522
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.96356682
Short name T156
Test name
Test status
Simulation time 126797252986 ps
CPU time 999.78 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:26:28 PM PST 24
Peak memory 265228 kb
Host smart-5edf10ff-0d35-4230-9cb9-a6143fc59366
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96356682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.96356682
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3137742107
Short name T723
Test name
Test status
Simulation time 66973389 ps
CPU time 8.06 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:10:02 PM PST 24
Peak memory 248528 kb
Host smart-612e9dd4-dae1-4745-9c2e-9e38851c38e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3137742107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3137742107
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2281999863
Short name T811
Test name
Test status
Simulation time 64969791 ps
CPU time 9.19 seconds
Started Mar 07 01:09:52 PM PST 24
Finished Mar 07 01:10:01 PM PST 24
Peak memory 253344 kb
Host smart-11bcc96c-01d7-46a2-9b64-0dbebd209cab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281999863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2281999863
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3413525331
Short name T774
Test name
Test status
Simulation time 232230130 ps
CPU time 5.01 seconds
Started Mar 07 01:09:54 PM PST 24
Finished Mar 07 01:09:59 PM PST 24
Peak memory 239360 kb
Host smart-ab8d417a-9fd0-4641-9be1-513af79c2e8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3413525331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3413525331
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2031287352
Short name T753
Test name
Test status
Simulation time 1350979622 ps
CPU time 18.34 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:10:12 PM PST 24
Peak memory 243716 kb
Host smart-f6d21e25-85c0-44b8-ba4a-37824ffaf71b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2031287352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2031287352
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.705008762
Short name T772
Test name
Test status
Simulation time 176304429 ps
CPU time 13.37 seconds
Started Mar 07 01:09:53 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 252440 kb
Host smart-e1557d7a-70d0-4bb7-8d0a-a563748aea99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=705008762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.705008762
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3587210683
Short name T338
Test name
Test status
Simulation time 203527224 ps
CPU time 8.47 seconds
Started Mar 07 01:09:49 PM PST 24
Finished Mar 07 01:09:58 PM PST 24
Peak memory 239068 kb
Host smart-9f82f7df-3745-4881-b639-5177bd2662c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587210683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3587210683
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2793500162
Short name T199
Test name
Test status
Simulation time 62520482 ps
CPU time 3.46 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:09:49 PM PST 24
Peak memory 236324 kb
Host smart-df068c5a-168e-4617-b27e-856fbac14837
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2793500162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2793500162
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2876839725
Short name T720
Test name
Test status
Simulation time 11951323 ps
CPU time 1.69 seconds
Started Mar 07 01:09:57 PM PST 24
Finished Mar 07 01:10:00 PM PST 24
Peak memory 235520 kb
Host smart-dbb18f54-2807-4520-bff7-6dabb08d2ff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2876839725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2876839725
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.869253086
Short name T806
Test name
Test status
Simulation time 176059416 ps
CPU time 11.66 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:10:10 PM PST 24
Peak memory 243748 kb
Host smart-7522a493-0da3-4a63-8f3e-1f6349bee5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=869253086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.869253086
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1938799675
Short name T128
Test name
Test status
Simulation time 7948714982 ps
CPU time 156.06 seconds
Started Mar 07 01:09:51 PM PST 24
Finished Mar 07 01:12:27 PM PST 24
Peak memory 265204 kb
Host smart-20c9a1fb-98bc-41a6-9beb-7bd87e2be45b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1938799675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1938799675
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2076810191
Short name T154
Test name
Test status
Simulation time 8765144441 ps
CPU time 645.77 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:20:44 PM PST 24
Peak memory 271944 kb
Host smart-0db9b4bf-fccd-4792-8baf-c6ab1feb6a80
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076810191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2076810191
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3078045886
Short name T810
Test name
Test status
Simulation time 490655925 ps
CPU time 16.26 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 248212 kb
Host smart-bf69cb26-a101-424a-ad3a-78404a503795
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3078045886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3078045886
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2741467856
Short name T336
Test name
Test status
Simulation time 920853560 ps
CPU time 14.53 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 254796 kb
Host smart-61062d89-f40d-46ea-b6af-3218bfabb0f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741467856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2741467856
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3665209747
Short name T761
Test name
Test status
Simulation time 117803871 ps
CPU time 4.81 seconds
Started Mar 07 01:10:05 PM PST 24
Finished Mar 07 01:10:10 PM PST 24
Peak memory 240228 kb
Host smart-31e403f4-fe84-49c1-9b85-551c983e34b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3665209747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3665209747
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2340257500
Short name T766
Test name
Test status
Simulation time 7986763 ps
CPU time 1.54 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:04 PM PST 24
Peak memory 235536 kb
Host smart-87b24944-fbf5-4827-a577-1f8d02260a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2340257500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2340257500
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.34997324
Short name T729
Test name
Test status
Simulation time 504172642 ps
CPU time 19.78 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:21 PM PST 24
Peak memory 244600 kb
Host smart-516ebc87-e80f-4312-9466-0fbff97e8fb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=34997324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_outs
tanding.34997324
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1188988691
Short name T701
Test name
Test status
Simulation time 88580998 ps
CPU time 11.6 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 248352 kb
Host smart-8b215b31-5e05-49de-b9d3-b51a50334a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1188988691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1188988691
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3359729633
Short name T337
Test name
Test status
Simulation time 215890209 ps
CPU time 7.72 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:10 PM PST 24
Peak memory 251956 kb
Host smart-daad7c3f-8fe6-4548-9212-a162cf365a57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359729633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3359729633
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3645461194
Short name T785
Test name
Test status
Simulation time 365938467 ps
CPU time 7.28 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:08 PM PST 24
Peak memory 235496 kb
Host smart-90990708-5f8e-43ec-b5b2-9f316b1456dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3645461194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3645461194
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4187194748
Short name T824
Test name
Test status
Simulation time 8075884 ps
CPU time 1.54 seconds
Started Mar 07 01:10:01 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 236416 kb
Host smart-a3c24f7c-4101-4757-a886-1062e5393c02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4187194748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4187194748
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.3719899441
Short name T782
Test name
Test status
Simulation time 2722164710 ps
CPU time 48.39 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:50 PM PST 24
Peak memory 244656 kb
Host smart-851e5e1a-1446-48e5-bc51-5d5a7cdf7963
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3719899441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.3719899441
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3497591465
Short name T162
Test name
Test status
Simulation time 12406902142 ps
CPU time 519.32 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:18:41 PM PST 24
Peak memory 265224 kb
Host smart-84f83a2d-abaa-42c0-a606-203abe22287f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497591465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3497591465
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3575424808
Short name T700
Test name
Test status
Simulation time 41713268 ps
CPU time 6.75 seconds
Started Mar 07 01:09:57 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 248144 kb
Host smart-9bea009c-d890-4146-99f5-4ecc8f14c345
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3575424808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3575424808
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3739560888
Short name T751
Test name
Test status
Simulation time 163100357 ps
CPU time 12.48 seconds
Started Mar 07 01:10:01 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 255128 kb
Host smart-09c43b55-d724-4ead-b34a-dfe2d5589c85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739560888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3739560888
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.2422855906
Short name T718
Test name
Test status
Simulation time 36514425 ps
CPU time 5.68 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:08 PM PST 24
Peak memory 240172 kb
Host smart-0bb11875-ff16-4b2e-897b-55df82da1274
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2422855906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.2422855906
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.524482189
Short name T721
Test name
Test status
Simulation time 8625101 ps
CPU time 1.61 seconds
Started Mar 07 01:10:01 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 236400 kb
Host smart-dadfce13-208f-4433-8b40-fff556cc9490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=524482189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.524482189
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2288589725
Short name T745
Test name
Test status
Simulation time 676925389 ps
CPU time 24.67 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:28 PM PST 24
Peak memory 243708 kb
Host smart-ac7cfe93-9ce1-4537-9d5c-60293d753ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2288589725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2288589725
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1318745061
Short name T152
Test name
Test status
Simulation time 2406039670 ps
CPU time 168.19 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:12:51 PM PST 24
Peak memory 264708 kb
Host smart-8144cbf8-8d9c-4561-9d06-5ba40af4cbf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1318745061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1318745061
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1316992018
Short name T160
Test name
Test status
Simulation time 50368689846 ps
CPU time 992.86 seconds
Started Mar 07 01:09:59 PM PST 24
Finished Mar 07 01:26:33 PM PST 24
Peak memory 265256 kb
Host smart-45c9f03c-67f9-4902-bc2b-ea4dedcbec32
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316992018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1316992018
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1806243229
Short name T764
Test name
Test status
Simulation time 390210701 ps
CPU time 13.84 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:17 PM PST 24
Peak memory 248508 kb
Host smart-1d4e3270-be17-4466-8e2c-a032c22f2879
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1806243229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1806243229
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.4082240813
Short name T166
Test name
Test status
Simulation time 185069272 ps
CPU time 2.62 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 235484 kb
Host smart-e91dc461-d391-4f08-be1d-24a913e3d6bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4082240813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.4082240813
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.22984015
Short name T739
Test name
Test status
Simulation time 1533716551 ps
CPU time 12.32 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:15 PM PST 24
Peak memory 249584 kb
Host smart-5081c7fa-d157-45b8-ab2c-420aeeb464b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22984015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.alert_handler_csr_mem_rw_with_rand_reset.22984015
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4180919231
Short name T714
Test name
Test status
Simulation time 114357708 ps
CPU time 8.24 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:12 PM PST 24
Peak memory 235464 kb
Host smart-0919a648-9e1b-4428-84e8-9a267997cb3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4180919231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4180919231
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1268354625
Short name T727
Test name
Test status
Simulation time 10195912 ps
CPU time 1.56 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 235516 kb
Host smart-9bd6de9d-7624-41fa-a5f4-f18da100afb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1268354625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1268354625
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.4114309266
Short name T752
Test name
Test status
Simulation time 2201147364 ps
CPU time 46.54 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:51 PM PST 24
Peak memory 244732 kb
Host smart-590003e9-f943-4a8f-aab6-930fec206fc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4114309266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.4114309266
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2137665786
Short name T147
Test name
Test status
Simulation time 8117153066 ps
CPU time 507.75 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:18:30 PM PST 24
Peak memory 265228 kb
Host smart-4fcbd4e1-2c16-4877-a043-cf0ee5610468
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137665786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2137665786
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.803274401
Short name T797
Test name
Test status
Simulation time 304423905 ps
CPU time 19.9 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:21 PM PST 24
Peak memory 252188 kb
Host smart-a2ad429a-aa73-4e31-8813-9fc769a29fa6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=803274401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.803274401
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1520711307
Short name T781
Test name
Test status
Simulation time 4595686427 ps
CPU time 286.9 seconds
Started Mar 07 01:09:43 PM PST 24
Finished Mar 07 01:14:30 PM PST 24
Peak memory 240276 kb
Host smart-adaf6b63-5ca9-4a0f-b5a2-5670bd2aa2e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1520711307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1520711307
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3155927223
Short name T722
Test name
Test status
Simulation time 3274031206 ps
CPU time 92.73 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:11:09 PM PST 24
Peak memory 235556 kb
Host smart-3a4032f5-6b7e-434a-96a8-e56a32976e46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3155927223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3155927223
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1468786474
Short name T786
Test name
Test status
Simulation time 46340768 ps
CPU time 7.11 seconds
Started Mar 07 01:09:37 PM PST 24
Finished Mar 07 01:09:44 PM PST 24
Peak memory 240216 kb
Host smart-5ada959e-da1c-458e-bb9f-01d79010b733
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1468786474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1468786474
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.404238361
Short name T778
Test name
Test status
Simulation time 105286830 ps
CPU time 6.15 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:09:46 PM PST 24
Peak memory 240224 kb
Host smart-9fb1351e-c868-406e-881c-9f238d93e80c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404238361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.alert_handler_csr_mem_rw_with_rand_reset.404238361
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1397275082
Short name T748
Test name
Test status
Simulation time 21139433 ps
CPU time 3.29 seconds
Started Mar 07 01:09:35 PM PST 24
Finished Mar 07 01:09:39 PM PST 24
Peak memory 236332 kb
Host smart-5b06f7d4-bd35-411e-a048-165caacd33b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1397275082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1397275082
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2552774167
Short name T795
Test name
Test status
Simulation time 1031212557 ps
CPU time 19.33 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:56 PM PST 24
Peak memory 240324 kb
Host smart-d3a2847e-f9ac-437b-a74c-acac77532b4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2552774167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2552774167
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4046061717
Short name T148
Test name
Test status
Simulation time 8315908060 ps
CPU time 157.3 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:12:13 PM PST 24
Peak memory 265244 kb
Host smart-b68c3689-ee2e-45e5-84ff-efec6d8ebe1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4046061717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4046061717
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1354388730
Short name T146
Test name
Test status
Simulation time 17797118789 ps
CPU time 677.95 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:20:54 PM PST 24
Peak memory 265320 kb
Host smart-a80086e6-0517-48fd-864a-e6cfea041dbd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354388730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1354388730
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2334549775
Short name T779
Test name
Test status
Simulation time 268542679 ps
CPU time 8.17 seconds
Started Mar 07 01:09:43 PM PST 24
Finished Mar 07 01:09:51 PM PST 24
Peak memory 248516 kb
Host smart-eb4d0555-e7be-4afd-b118-5def5d33c7bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2334549775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2334549775
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3359495031
Short name T284
Test name
Test status
Simulation time 319010997 ps
CPU time 21.82 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:58 PM PST 24
Peak memory 239336 kb
Host smart-9bebf0b7-7062-4913-829c-dab330f8dd9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3359495031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3359495031
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.655861697
Short name T769
Test name
Test status
Simulation time 18799056 ps
CPU time 1.86 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 236416 kb
Host smart-8ab56555-f16b-47bd-8e48-40c5a81d3f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=655861697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.655861697
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4230498043
Short name T711
Test name
Test status
Simulation time 7616799 ps
CPU time 1.49 seconds
Started Mar 07 01:10:00 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 235544 kb
Host smart-d03cc22f-27a1-41ba-b6d0-70dcfd058356
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4230498043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4230498043
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1285338774
Short name T799
Test name
Test status
Simulation time 15649700 ps
CPU time 1.27 seconds
Started Mar 07 01:10:05 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 236408 kb
Host smart-d086a8a0-f9d4-461c-87bf-776388f0e53e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1285338774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1285338774
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1459027361
Short name T807
Test name
Test status
Simulation time 21562332 ps
CPU time 2.03 seconds
Started Mar 07 01:09:59 PM PST 24
Finished Mar 07 01:10:01 PM PST 24
Peak memory 235540 kb
Host smart-5c9cf1b6-0f38-4c77-b022-7bbe54d56ec5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1459027361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1459027361
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3048363512
Short name T333
Test name
Test status
Simulation time 13179690 ps
CPU time 1.34 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:04 PM PST 24
Peak memory 235632 kb
Host smart-bc5a16ff-c34c-47b8-9907-4d386d0a1a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3048363512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3048363512
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1345679705
Short name T759
Test name
Test status
Simulation time 7833452 ps
CPU time 1.48 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 234488 kb
Host smart-59128649-90f5-4218-9ae0-e62ba71ff91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345679705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1345679705
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2511885168
Short name T789
Test name
Test status
Simulation time 12633236 ps
CPU time 1.44 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 236416 kb
Host smart-129c1fda-d24e-4cf2-bfdb-600773a3dbe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2511885168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2511885168
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3250748414
Short name T719
Test name
Test status
Simulation time 16431560 ps
CPU time 1.28 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 234564 kb
Host smart-15226e19-9a33-4053-8735-e5033b10aef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3250748414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3250748414
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1547833241
Short name T780
Test name
Test status
Simulation time 18746523 ps
CPU time 1.26 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 235544 kb
Host smart-13e1d466-0ef0-46e3-8fcf-59205ac559e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1547833241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1547833241
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.608116013
Short name T822
Test name
Test status
Simulation time 29981471 ps
CPU time 1.63 seconds
Started Mar 07 01:10:02 PM PST 24
Finished Mar 07 01:10:04 PM PST 24
Peak memory 236380 kb
Host smart-e8f2beb8-89e7-48ec-a7be-a41bdc45f335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=608116013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.608116013
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3983231958
Short name T800
Test name
Test status
Simulation time 6806718901 ps
CPU time 125.35 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:11:42 PM PST 24
Peak memory 236420 kb
Host smart-8a400e81-2788-4193-b5e6-e97a1031810c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3983231958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3983231958
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2679396251
Short name T732
Test name
Test status
Simulation time 6286804562 ps
CPU time 108.84 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:11:28 PM PST 24
Peak memory 236204 kb
Host smart-834234b6-5e0b-468e-8e15-2e9ef045356f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2679396251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2679396251
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2360025157
Short name T819
Test name
Test status
Simulation time 142143856 ps
CPU time 10.51 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:09:49 PM PST 24
Peak memory 240232 kb
Host smart-0a0ddab0-dfb5-4afa-946d-8ab9a6d7d8d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2360025157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2360025157
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1321973255
Short name T775
Test name
Test status
Simulation time 53497550 ps
CPU time 5.38 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:44 PM PST 24
Peak memory 239392 kb
Host smart-0a0b0a80-d552-44a6-9840-1d46a573390c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321973255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1321973255
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3994354498
Short name T767
Test name
Test status
Simulation time 36462439 ps
CPU time 5.28 seconds
Started Mar 07 01:09:42 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 236328 kb
Host smart-79b5d92c-773c-4586-a85f-2c23064e3669
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3994354498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3994354498
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.936366197
Short name T787
Test name
Test status
Simulation time 16487622 ps
CPU time 1.34 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:09:41 PM PST 24
Peak memory 235532 kb
Host smart-e8b1f720-5032-4f67-aafd-752a7ec4b8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=936366197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.936366197
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2020407491
Short name T820
Test name
Test status
Simulation time 200253760 ps
CPU time 12.45 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:49 PM PST 24
Peak memory 244596 kb
Host smart-5a13ff4d-869f-46c5-9b98-4d3ce817a2ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2020407491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2020407491
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2500295987
Short name T151
Test name
Test status
Simulation time 4043748218 ps
CPU time 224.38 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:13:22 PM PST 24
Peak memory 256996 kb
Host smart-672b8385-5b69-4954-9ff5-a406c4f853e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2500295987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2500295987
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1016681489
Short name T813
Test name
Test status
Simulation time 153508300 ps
CPU time 5.69 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:09:46 PM PST 24
Peak memory 247888 kb
Host smart-5ff03fa9-69b9-4bca-a5c5-8b4a04493fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1016681489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1016681489
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3911499653
Short name T777
Test name
Test status
Simulation time 11156474 ps
CPU time 1.4 seconds
Started Mar 07 01:10:03 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 234416 kb
Host smart-3a97540a-5b4b-4a58-a417-7f2c3121ebfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3911499653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3911499653
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.764743193
Short name T776
Test name
Test status
Simulation time 10084871 ps
CPU time 1.49 seconds
Started Mar 07 01:10:01 PM PST 24
Finished Mar 07 01:10:03 PM PST 24
Peak memory 236400 kb
Host smart-c5a03f53-938b-4123-8201-939111271a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=764743193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.764743193
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2788399689
Short name T737
Test name
Test status
Simulation time 6443427 ps
CPU time 1.4 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 236424 kb
Host smart-0646c55b-e540-421d-80d8-889f065128c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2788399689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2788399689
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1688414094
Short name T742
Test name
Test status
Simulation time 6418679 ps
CPU time 1.45 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 235424 kb
Host smart-2917bf25-64bf-4163-b79a-d0455062f340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1688414094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1688414094
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1606229596
Short name T794
Test name
Test status
Simulation time 25988652 ps
CPU time 1.49 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:06 PM PST 24
Peak memory 235456 kb
Host smart-14248e12-9504-4a73-8f4b-910a5d6f2275
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606229596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1606229596
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1228399415
Short name T730
Test name
Test status
Simulation time 12939693 ps
CPU time 1.55 seconds
Started Mar 07 01:10:04 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 234568 kb
Host smart-3a7d6cfc-59d4-4e24-aa72-163a01d51a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1228399415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1228399415
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.954440846
Short name T717
Test name
Test status
Simulation time 8294961 ps
CPU time 1.51 seconds
Started Mar 07 01:10:13 PM PST 24
Finished Mar 07 01:10:15 PM PST 24
Peak memory 236416 kb
Host smart-0a7bb88c-e569-4579-a097-5b21db46eed6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=954440846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.954440846
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3181196649
Short name T706
Test name
Test status
Simulation time 12498774 ps
CPU time 1.31 seconds
Started Mar 07 01:10:17 PM PST 24
Finished Mar 07 01:10:18 PM PST 24
Peak memory 235612 kb
Host smart-051eccce-05ad-4fa2-95f4-51f2209071a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3181196649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3181196649
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.929717934
Short name T168
Test name
Test status
Simulation time 42304296 ps
CPU time 1.42 seconds
Started Mar 07 01:10:13 PM PST 24
Finished Mar 07 01:10:15 PM PST 24
Peak memory 236420 kb
Host smart-4162c99a-cdaa-4118-a58c-18da2f9eb145
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=929717934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.929717934
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1021690775
Short name T804
Test name
Test status
Simulation time 9563966 ps
CPU time 1.31 seconds
Started Mar 07 01:10:14 PM PST 24
Finished Mar 07 01:10:15 PM PST 24
Peak memory 236436 kb
Host smart-a8553197-0d3c-461d-ad6f-3ab4b104d651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1021690775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1021690775
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4144061233
Short name T713
Test name
Test status
Simulation time 598738796 ps
CPU time 89.47 seconds
Started Mar 07 01:09:44 PM PST 24
Finished Mar 07 01:11:13 PM PST 24
Peak memory 236324 kb
Host smart-0b9bca75-08bf-4557-9191-89b02c5da285
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4144061233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4144061233
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3011343621
Short name T728
Test name
Test status
Simulation time 3270719458 ps
CPU time 119.6 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:11:40 PM PST 24
Peak memory 240312 kb
Host smart-67633014-b337-4b22-b108-32439ecfb486
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3011343621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3011343621
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1684286522
Short name T792
Test name
Test status
Simulation time 117140411 ps
CPU time 10.43 seconds
Started Mar 07 01:09:43 PM PST 24
Finished Mar 07 01:09:54 PM PST 24
Peak memory 240248 kb
Host smart-5605a83b-ef02-446c-abb5-a75998a66bcd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1684286522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1684286522
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1547454265
Short name T756
Test name
Test status
Simulation time 297489977 ps
CPU time 4.4 seconds
Started Mar 07 01:09:35 PM PST 24
Finished Mar 07 01:09:40 PM PST 24
Peak memory 237912 kb
Host smart-a872a95c-38bc-43be-8ddf-be0a7936e321
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547454265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1547454265
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3027884389
Short name T724
Test name
Test status
Simulation time 48229802 ps
CPU time 4.74 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:41 PM PST 24
Peak memory 236256 kb
Host smart-961e6856-859e-4a9b-aa2f-6280d9d92fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3027884389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3027884389
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.2982638599
Short name T747
Test name
Test status
Simulation time 22893219 ps
CPU time 1.43 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:41 PM PST 24
Peak memory 235560 kb
Host smart-ba091a1e-2dbf-4bd8-b1e8-3692ae193c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2982638599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.2982638599
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3107228105
Short name T705
Test name
Test status
Simulation time 664243047 ps
CPU time 20.88 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:10:01 PM PST 24
Peak memory 243728 kb
Host smart-82b52111-ca77-4c0b-ad34-11de6337e87a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3107228105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3107228105
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1651859189
Short name T129
Test name
Test status
Simulation time 2761247995 ps
CPU time 174.38 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:12:33 PM PST 24
Peak memory 257060 kb
Host smart-f5006bcb-c7da-4f4d-80ae-e39e6e7da4d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1651859189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1651859189
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2937229828
Short name T762
Test name
Test status
Simulation time 187224683 ps
CPU time 12.47 seconds
Started Mar 07 01:09:37 PM PST 24
Finished Mar 07 01:09:50 PM PST 24
Peak memory 249496 kb
Host smart-cb1b014a-42e1-4be7-9e37-7461ff58c7b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2937229828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2937229828
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.290097474
Short name T788
Test name
Test status
Simulation time 6941250 ps
CPU time 1.45 seconds
Started Mar 07 01:10:15 PM PST 24
Finished Mar 07 01:10:17 PM PST 24
Peak memory 235612 kb
Host smart-e51d5b93-54a3-4bd9-a932-28b24538c1c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=290097474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.290097474
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2555649554
Short name T715
Test name
Test status
Simulation time 7738304 ps
CPU time 1.41 seconds
Started Mar 07 01:10:13 PM PST 24
Finished Mar 07 01:10:15 PM PST 24
Peak memory 236436 kb
Host smart-4cad1d2e-19cd-46ec-9801-e389799b1d46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555649554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2555649554
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3126192143
Short name T768
Test name
Test status
Simulation time 9955740 ps
CPU time 1.24 seconds
Started Mar 07 01:10:13 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 234384 kb
Host smart-4639c8f3-c4fb-477d-819e-91c3512cbb8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3126192143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3126192143
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.479837015
Short name T771
Test name
Test status
Simulation time 12776790 ps
CPU time 1.37 seconds
Started Mar 07 01:10:17 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 235660 kb
Host smart-a15b0f5e-0096-44c3-8afc-7fb25eafdf23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=479837015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.479837015
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1306944209
Short name T735
Test name
Test status
Simulation time 23122623 ps
CPU time 1.49 seconds
Started Mar 07 01:10:19 PM PST 24
Finished Mar 07 01:10:20 PM PST 24
Peak memory 236408 kb
Host smart-62da60aa-849f-45a1-bb70-d0b36279ca89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1306944209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1306944209
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.1566931555
Short name T763
Test name
Test status
Simulation time 44324714 ps
CPU time 2.73 seconds
Started Mar 07 01:10:14 PM PST 24
Finished Mar 07 01:10:17 PM PST 24
Peak memory 234556 kb
Host smart-34f61f31-1dd9-49d8-9c09-071c7af6e8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1566931555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.1566931555
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2900785182
Short name T738
Test name
Test status
Simulation time 15640012 ps
CPU time 1.43 seconds
Started Mar 07 01:10:10 PM PST 24
Finished Mar 07 01:10:12 PM PST 24
Peak memory 236444 kb
Host smart-1c4a6d65-b6ab-47fc-824a-0bdfbdfa014f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2900785182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2900785182
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1547969892
Short name T224
Test name
Test status
Simulation time 62466834 ps
CPU time 1.37 seconds
Started Mar 07 01:10:14 PM PST 24
Finished Mar 07 01:10:16 PM PST 24
Peak memory 236276 kb
Host smart-b7e8367f-b2ed-4076-a6fe-b9183eea1bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1547969892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1547969892
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2760655831
Short name T703
Test name
Test status
Simulation time 7935624 ps
CPU time 1.52 seconds
Started Mar 07 01:10:13 PM PST 24
Finished Mar 07 01:10:14 PM PST 24
Peak memory 234464 kb
Host smart-365f46eb-22cf-472c-8a5b-2d146398ee0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2760655831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2760655831
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1909606137
Short name T330
Test name
Test status
Simulation time 7572253 ps
CPU time 1.5 seconds
Started Mar 07 01:10:17 PM PST 24
Finished Mar 07 01:10:19 PM PST 24
Peak memory 234600 kb
Host smart-493164f8-07b1-4fda-999c-31da647d453f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1909606137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1909606137
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.4285698828
Short name T186
Test name
Test status
Simulation time 62273933 ps
CPU time 10.26 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:50 PM PST 24
Peak memory 255648 kb
Host smart-c5c3a2ba-0e16-4f28-84de-b83985fb0692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285698828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.4285698828
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2692648705
Short name T754
Test name
Test status
Simulation time 34155490 ps
CPU time 4.9 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:44 PM PST 24
Peak memory 240224 kb
Host smart-ad674bba-0ebe-46a2-a2df-de0a2531187e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2692648705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2692648705
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1299096504
Short name T791
Test name
Test status
Simulation time 11106106 ps
CPU time 1.24 seconds
Started Mar 07 01:09:41 PM PST 24
Finished Mar 07 01:09:43 PM PST 24
Peak memory 236268 kb
Host smart-c4ad71d9-c513-486b-9185-d3b82707603c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1299096504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1299096504
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2232159284
Short name T197
Test name
Test status
Simulation time 682170927 ps
CPU time 26.71 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:10:05 PM PST 24
Peak memory 244652 kb
Host smart-094d57a6-8301-4a63-aa47-a46f2e22b7cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2232159284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2232159284
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.287066115
Short name T130
Test name
Test status
Simulation time 3461198494 ps
CPU time 211.66 seconds
Started Mar 07 01:09:37 PM PST 24
Finished Mar 07 01:13:09 PM PST 24
Peak memory 271788 kb
Host smart-e03f6a9a-a11d-4b7d-a814-893ee8b646cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=287066115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.287066115
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3943039567
Short name T138
Test name
Test status
Simulation time 4504629080 ps
CPU time 592.83 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:19:32 PM PST 24
Peak memory 265184 kb
Host smart-6a665e3b-638b-4fc2-94fb-bff8250a1ebf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943039567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3943039567
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3148697048
Short name T760
Test name
Test status
Simulation time 679692398 ps
CPU time 5.58 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:09:45 PM PST 24
Peak memory 248168 kb
Host smart-9e8c8d83-bbce-4402-a132-11eb618df22c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3148697048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3148697048
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1138162522
Short name T798
Test name
Test status
Simulation time 365485719 ps
CPU time 14.74 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:10:00 PM PST 24
Peak memory 250700 kb
Host smart-7c8f5363-a4db-4517-94db-68d9a58c20f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138162522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1138162522
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.4035723354
Short name T823
Test name
Test status
Simulation time 323644330 ps
CPU time 9.55 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:48 PM PST 24
Peak memory 236352 kb
Host smart-42f9ac2d-adb2-49d6-b8a8-a46b354d0cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4035723354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.4035723354
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1091871387
Short name T223
Test name
Test status
Simulation time 16659198 ps
CPU time 1.36 seconds
Started Mar 07 01:09:41 PM PST 24
Finished Mar 07 01:09:42 PM PST 24
Peak memory 236440 kb
Host smart-bc52aa11-ea47-41aa-9251-c0072f2592dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1091871387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1091871387
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3307270181
Short name T709
Test name
Test status
Simulation time 166538425 ps
CPU time 11.4 seconds
Started Mar 07 01:09:40 PM PST 24
Finished Mar 07 01:09:51 PM PST 24
Peak memory 240328 kb
Host smart-dc74c2f3-e8b2-4dd2-99dc-8fff68474358
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3307270181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3307270181
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2331886650
Short name T145
Test name
Test status
Simulation time 2388601422 ps
CPU time 327.04 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:15:05 PM PST 24
Peak memory 268456 kb
Host smart-3670d481-e8b9-412b-8d7b-4de952846c83
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331886650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2331886650
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3946275780
Short name T708
Test name
Test status
Simulation time 281458759 ps
CPU time 5.07 seconds
Started Mar 07 01:09:37 PM PST 24
Finished Mar 07 01:09:42 PM PST 24
Peak memory 240232 kb
Host smart-5a8eaba7-afe8-4a7b-ab88-c6473a1ae5b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3946275780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3946275780
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1078602877
Short name T805
Test name
Test status
Simulation time 1166897145 ps
CPU time 42.87 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:10:28 PM PST 24
Peak memory 236572 kb
Host smart-c37e15b5-92ed-4a2f-884d-b2d463122168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1078602877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1078602877
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.714714370
Short name T716
Test name
Test status
Simulation time 67003232 ps
CPU time 4.75 seconds
Started Mar 07 01:09:36 PM PST 24
Finished Mar 07 01:09:41 PM PST 24
Peak memory 241952 kb
Host smart-8d492844-cc5f-4c68-82bf-6a9a8bd8b7b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714714370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.714714370
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4285235168
Short name T801
Test name
Test status
Simulation time 230203863 ps
CPU time 5.35 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:09:45 PM PST 24
Peak memory 240088 kb
Host smart-c7aee813-9c9f-404f-b3d0-8181617272f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4285235168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4285235168
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.1827342670
Short name T790
Test name
Test status
Simulation time 11863867 ps
CPU time 1.31 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:09:39 PM PST 24
Peak memory 236432 kb
Host smart-3d30a91f-0ed6-444c-b6af-139dcdd8203b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1827342670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1827342670
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.2022528837
Short name T182
Test name
Test status
Simulation time 2481609335 ps
CPU time 42.8 seconds
Started Mar 07 01:09:39 PM PST 24
Finished Mar 07 01:10:22 PM PST 24
Peak memory 244672 kb
Host smart-065f4632-eff3-44da-9889-648a2fcd99b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2022528837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.2022528837
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.1623229282
Short name T163
Test name
Test status
Simulation time 5437308586 ps
CPU time 375.82 seconds
Started Mar 07 01:09:42 PM PST 24
Finished Mar 07 01:15:58 PM PST 24
Peak memory 270832 kb
Host smart-a3938007-8781-4ab3-b849-4dc91788177d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1623229282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.1623229282
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1928507886
Short name T821
Test name
Test status
Simulation time 92453454 ps
CPU time 6.46 seconds
Started Mar 07 01:09:38 PM PST 24
Finished Mar 07 01:09:44 PM PST 24
Peak memory 247928 kb
Host smart-003cbd51-558c-4d9e-aa2b-46890fcf1371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1928507886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1928507886
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.622376839
Short name T743
Test name
Test status
Simulation time 578287576 ps
CPU time 12.06 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:10:00 PM PST 24
Peak memory 250600 kb
Host smart-33f9343d-c098-4a43-9ad1-8cb13dd1864e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622376839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.622376839
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.4284253823
Short name T814
Test name
Test status
Simulation time 473322317 ps
CPU time 8.67 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:09:57 PM PST 24
Peak memory 236300 kb
Host smart-f0f2ebbf-a182-4d68-b55c-c615648e07f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4284253823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.4284253823
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3391272734
Short name T726
Test name
Test status
Simulation time 26999393 ps
CPU time 1.43 seconds
Started Mar 07 01:09:43 PM PST 24
Finished Mar 07 01:09:44 PM PST 24
Peak memory 236452 kb
Host smart-7a68174e-70c5-437d-b736-f3c51e495777
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3391272734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3391272734
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1166503665
Short name T734
Test name
Test status
Simulation time 1887781742 ps
CPU time 21.76 seconds
Started Mar 07 01:09:56 PM PST 24
Finished Mar 07 01:10:20 PM PST 24
Peak memory 243692 kb
Host smart-c766d4ab-af4d-4f07-9d1a-d36e472dce00
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1166503665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1166503665
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1393396545
Short name T132
Test name
Test status
Simulation time 19169268026 ps
CPU time 347.3 seconds
Started Mar 07 01:09:51 PM PST 24
Finished Mar 07 01:15:39 PM PST 24
Peak memory 265180 kb
Host smart-504cf041-e1a7-4c6d-aa28-3535f62b7552
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1393396545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1393396545
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2346165996
Short name T134
Test name
Test status
Simulation time 17515546432 ps
CPU time 1296.65 seconds
Started Mar 07 01:09:43 PM PST 24
Finished Mar 07 01:31:20 PM PST 24
Peak memory 265312 kb
Host smart-de30a593-270f-4607-a6fa-654a9bd88ada
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346165996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2346165996
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.4039568183
Short name T746
Test name
Test status
Simulation time 428806179 ps
CPU time 13.59 seconds
Started Mar 07 01:09:42 PM PST 24
Finished Mar 07 01:09:56 PM PST 24
Peak memory 247264 kb
Host smart-d912377a-679f-45e5-8d5e-b35927b40615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4039568183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.4039568183
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2240913936
Short name T809
Test name
Test status
Simulation time 62115008 ps
CPU time 9.67 seconds
Started Mar 07 01:09:48 PM PST 24
Finished Mar 07 01:09:57 PM PST 24
Peak memory 254356 kb
Host smart-ce908db3-12d1-49cf-932a-9adddcc7cf0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240913936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2240913936
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2452613451
Short name T712
Test name
Test status
Simulation time 35621017 ps
CPU time 6.87 seconds
Started Mar 07 01:09:42 PM PST 24
Finished Mar 07 01:09:49 PM PST 24
Peak memory 240096 kb
Host smart-3b66e3e6-98fa-4073-81bc-2f6bbbef0a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2452613451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2452613451
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1518054163
Short name T332
Test name
Test status
Simulation time 9942718 ps
CPU time 1.29 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:09:47 PM PST 24
Peak memory 236396 kb
Host smart-4d401907-5903-4c90-9113-f84ea29641bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1518054163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1518054163
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2521259223
Short name T198
Test name
Test status
Simulation time 2719117175 ps
CPU time 50.19 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:10:36 PM PST 24
Peak memory 244640 kb
Host smart-c63e8803-13fe-45e4-b1ae-bdff10911da4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2521259223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2521259223
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4215592624
Short name T142
Test name
Test status
Simulation time 10068633263 ps
CPU time 178.95 seconds
Started Mar 07 01:09:45 PM PST 24
Finished Mar 07 01:12:44 PM PST 24
Peak memory 265208 kb
Host smart-3b876a41-55b8-49e8-889b-3f7a89d60b70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4215592624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4215592624
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2560763907
Short name T815
Test name
Test status
Simulation time 4261630748 ps
CPU time 281.93 seconds
Started Mar 07 01:09:50 PM PST 24
Finished Mar 07 01:14:32 PM PST 24
Peak memory 265172 kb
Host smart-27d755ef-4aec-4e59-b66f-e883f2c5a410
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560763907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2560763907
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.4224349063
Short name T796
Test name
Test status
Simulation time 69754841 ps
CPU time 9.01 seconds
Started Mar 07 01:09:44 PM PST 24
Finished Mar 07 01:09:54 PM PST 24
Peak memory 247896 kb
Host smart-3f2a1287-5f2f-4653-85d7-0165ba461678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4224349063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4224349063
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3769467946
Short name T671
Test name
Test status
Simulation time 172456067 ps
CPU time 4.05 seconds
Started Mar 07 01:51:12 PM PST 24
Finished Mar 07 01:51:16 PM PST 24
Peak memory 249172 kb
Host smart-bef332b9-6d86-4ebb-9ae6-dfc89317f7c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3769467946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3769467946
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2096922638
Short name T253
Test name
Test status
Simulation time 59608704281 ps
CPU time 1987.05 seconds
Started Mar 07 01:50:53 PM PST 24
Finished Mar 07 02:24:00 PM PST 24
Peak memory 282640 kb
Host smart-684c9ef7-3f5f-4589-9d83-5e3bd209ef50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096922638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2096922638
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1894646586
Short name T378
Test name
Test status
Simulation time 99768903 ps
CPU time 6.45 seconds
Started Mar 07 01:51:13 PM PST 24
Finished Mar 07 01:51:19 PM PST 24
Peak memory 240804 kb
Host smart-f559e036-88b6-434a-83e9-b92c471dc963
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1894646586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1894646586
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1305936559
Short name T110
Test name
Test status
Simulation time 4547565646 ps
CPU time 252.61 seconds
Started Mar 07 01:50:57 PM PST 24
Finished Mar 07 01:55:10 PM PST 24
Peak memory 256576 kb
Host smart-f10a65db-9672-426c-80b2-31078a3a7f3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13059
36559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1305936559
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1812574604
Short name T579
Test name
Test status
Simulation time 68455588 ps
CPU time 7.29 seconds
Started Mar 07 01:50:54 PM PST 24
Finished Mar 07 01:51:01 PM PST 24
Peak memory 252564 kb
Host smart-71afd352-24a7-415a-872b-8c65c10a956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18125
74604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1812574604
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.902566859
Short name T325
Test name
Test status
Simulation time 20133462582 ps
CPU time 1429.6 seconds
Started Mar 07 01:50:59 PM PST 24
Finished Mar 07 02:14:49 PM PST 24
Peak memory 288856 kb
Host smart-c851e5bd-d703-4859-856c-66536d4f9706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902566859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.902566859
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3008264684
Short name T665
Test name
Test status
Simulation time 64318128563 ps
CPU time 1955.31 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 02:23:50 PM PST 24
Peak memory 289616 kb
Host smart-7f1757b2-3bee-4e34-aaff-dd5e723c1038
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008264684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3008264684
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1887457416
Short name T202
Test name
Test status
Simulation time 185467733 ps
CPU time 19.88 seconds
Started Mar 07 01:50:54 PM PST 24
Finished Mar 07 01:51:14 PM PST 24
Peak memory 249032 kb
Host smart-407fe9ab-900e-4d83-912d-5fbdccd93488
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18874
57416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1887457416
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.495191840
Short name T60
Test name
Test status
Simulation time 746664897 ps
CPU time 38.87 seconds
Started Mar 07 01:51:03 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 255288 kb
Host smart-2088b61f-bda0-4b0c-8ada-0ccf18b20a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49519
1840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.495191840
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.370791405
Short name T265
Test name
Test status
Simulation time 533538918 ps
CPU time 14.14 seconds
Started Mar 07 01:50:54 PM PST 24
Finished Mar 07 01:51:09 PM PST 24
Peak memory 255088 kb
Host smart-48e22950-74bf-4bf1-9e62-015921925500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37079
1405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.370791405
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2973685864
Short name T352
Test name
Test status
Simulation time 38368402 ps
CPU time 5.65 seconds
Started Mar 07 01:50:53 PM PST 24
Finished Mar 07 01:50:59 PM PST 24
Peak memory 249012 kb
Host smart-fbe1fa60-ecca-4a2f-9af6-fa3475a18633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29736
85864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2973685864
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1906873926
Short name T612
Test name
Test status
Simulation time 246876487933 ps
CPU time 1688.8 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 02:19:23 PM PST 24
Peak memory 289700 kb
Host smart-4f1fca21-77f5-437d-ae80-8a8e96cc1971
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906873926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1906873926
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.671583353
Short name T656
Test name
Test status
Simulation time 42669368073 ps
CPU time 985.14 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 02:07:32 PM PST 24
Peak memory 272996 kb
Host smart-46ab4577-6243-4ff8-b6fe-75a25015092a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671583353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.671583353
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3681162326
Short name T683
Test name
Test status
Simulation time 2639919984 ps
CPU time 146.47 seconds
Started Mar 07 01:51:11 PM PST 24
Finished Mar 07 01:53:38 PM PST 24
Peak memory 248448 kb
Host smart-85c2ccf3-eb81-4e35-bd32-ca0782d18c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
62326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3681162326
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1225335718
Short name T3
Test name
Test status
Simulation time 441027500 ps
CPU time 30.41 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 01:51:45 PM PST 24
Peak memory 255432 kb
Host smart-631c0383-bc52-43c7-adee-ad0b940c5bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12253
35718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1225335718
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.403342797
Short name T328
Test name
Test status
Simulation time 19818298697 ps
CPU time 848.07 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 02:05:17 PM PST 24
Peak memory 265396 kb
Host smart-9337beaf-aeda-4bb3-a0ec-db248b5943cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403342797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.403342797
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.300705047
Short name T85
Test name
Test status
Simulation time 125453172435 ps
CPU time 2202.75 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 02:27:52 PM PST 24
Peak memory 288780 kb
Host smart-4c17606e-e899-46ba-89e0-b5d56427d8b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300705047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.300705047
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1041957489
Short name T589
Test name
Test status
Simulation time 59642443279 ps
CPU time 534.97 seconds
Started Mar 07 01:51:12 PM PST 24
Finished Mar 07 02:00:07 PM PST 24
Peak memory 247936 kb
Host smart-ab0c6eac-e217-4585-9321-e70de4fcf032
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041957489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1041957489
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1872941838
Short name T547
Test name
Test status
Simulation time 1100191806 ps
CPU time 27.32 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 01:51:37 PM PST 24
Peak memory 249116 kb
Host smart-12e04618-9e3c-4821-8d87-b3b7963a34a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18729
41838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1872941838
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3107891053
Short name T71
Test name
Test status
Simulation time 810421338 ps
CPU time 34.42 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 254260 kb
Host smart-d1da7b4c-c764-4744-b4dd-6e868f4e59f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31078
91053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3107891053
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2571560928
Short name T10
Test name
Test status
Simulation time 808382128 ps
CPU time 25.71 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:51:41 PM PST 24
Peak memory 277664 kb
Host smart-c49aee7e-1720-4aff-9386-5177fcb625f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2571560928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2571560928
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.357283683
Short name T78
Test name
Test status
Simulation time 1093221088 ps
CPU time 20.04 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:29 PM PST 24
Peak memory 247220 kb
Host smart-15feb9a2-b3ce-4e74-a8dd-cacdec8212a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35728
3683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.357283683
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.4060713222
Short name T684
Test name
Test status
Simulation time 560288607 ps
CPU time 33.92 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 01:51:44 PM PST 24
Peak memory 255328 kb
Host smart-68ca49eb-85aa-4a5a-b14c-ff84ed6480e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40607
13222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.4060713222
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.768241460
Short name T594
Test name
Test status
Simulation time 11837895556 ps
CPU time 166.42 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:54:02 PM PST 24
Peak memory 255468 kb
Host smart-abeec713-afb3-4cdb-abcb-4e9f372b671f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768241460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.768241460
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.808544323
Short name T76
Test name
Test status
Simulation time 103069182851 ps
CPU time 2920.57 seconds
Started Mar 07 01:51:18 PM PST 24
Finished Mar 07 02:40:00 PM PST 24
Peak memory 288104 kb
Host smart-3829c48e-9e97-4096-ae77-72a98ea645cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808544323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.808544323
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.46925283
Short name T402
Test name
Test status
Simulation time 252099853 ps
CPU time 14.26 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 248916 kb
Host smart-f996c22e-2cc3-4e51-b8e4-d3e708d5c421
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=46925283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.46925283
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1039808333
Short name T70
Test name
Test status
Simulation time 99456300 ps
CPU time 10.44 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:39 PM PST 24
Peak memory 253932 kb
Host smart-c498d3fb-3d21-4521-b8cc-67e03dc6ad01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10398
08333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1039808333
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.887622154
Short name T379
Test name
Test status
Simulation time 62845724 ps
CPU time 6.73 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 01:51:33 PM PST 24
Peak memory 248540 kb
Host smart-8159985f-d5ba-4952-b187-643ae375f73c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88762
2154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.887622154
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2512630785
Short name T568
Test name
Test status
Simulation time 23561142908 ps
CPU time 1190.45 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 02:11:14 PM PST 24
Peak memory 283508 kb
Host smart-181ad566-2b79-4ad4-8814-30194adc1ee5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512630785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2512630785
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2344476876
Short name T384
Test name
Test status
Simulation time 10618163551 ps
CPU time 768.61 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 02:04:13 PM PST 24
Peak memory 269564 kb
Host smart-d754dc8c-eaba-442f-9799-c512d6c32e08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344476876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2344476876
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3274107410
Short name T312
Test name
Test status
Simulation time 18408789615 ps
CPU time 386.18 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:57:47 PM PST 24
Peak memory 248992 kb
Host smart-0ddf61a5-e0c2-4c42-8a9c-f7acd0d39c3b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274107410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3274107410
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1892608031
Short name T399
Test name
Test status
Simulation time 4918963100 ps
CPU time 36.62 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:58 PM PST 24
Peak memory 255216 kb
Host smart-a6f38981-5c50-4eea-9071-a132c5ce0e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
08031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1892608031
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1480354424
Short name T542
Test name
Test status
Simulation time 1563046193 ps
CPU time 51.72 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:52:20 PM PST 24
Peak memory 255412 kb
Host smart-4ec2f7e2-aa47-4b16-be6b-69cbcb186e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14803
54424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1480354424
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.4121533660
Short name T283
Test name
Test status
Simulation time 9084056108 ps
CPU time 33.06 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 255184 kb
Host smart-e6454e2a-2ef8-446a-b8c8-8be949198def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41215
33660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4121533660
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1750579285
Short name T67
Test name
Test status
Simulation time 445337175 ps
CPU time 32.69 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:54 PM PST 24
Peak memory 255708 kb
Host smart-a42d8a07-f07f-463b-94f8-c1e59a294f0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17505
79285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1750579285
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3596843815
Short name T263
Test name
Test status
Simulation time 441320924328 ps
CPU time 3141.67 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 02:43:46 PM PST 24
Peak memory 289064 kb
Host smart-b8219745-8e31-468c-b5a0-ff7e5083be5c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596843815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3596843815
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.636688608
Short name T232
Test name
Test status
Simulation time 65474009349 ps
CPU time 1380.78 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 02:14:22 PM PST 24
Peak memory 287416 kb
Host smart-7d8b91f9-a1e7-4b4a-840d-af29d0d9168e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636688608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.636688608
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3002296295
Short name T645
Test name
Test status
Simulation time 3047741377 ps
CPU time 39.72 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:52:03 PM PST 24
Peak memory 249040 kb
Host smart-7b4cc3de-8c30-4e68-8e11-d0f5c7be8e7f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3002296295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3002296295
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3205665056
Short name T419
Test name
Test status
Simulation time 5156051803 ps
CPU time 286.53 seconds
Started Mar 07 01:51:23 PM PST 24
Finished Mar 07 01:56:10 PM PST 24
Peak memory 256676 kb
Host smart-3a3adb9a-e992-450e-abe6-a2ca4dc6b6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32056
65056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3205665056
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.156600381
Short name T368
Test name
Test status
Simulation time 558574030 ps
CPU time 8.43 seconds
Started Mar 07 01:51:23 PM PST 24
Finished Mar 07 01:51:32 PM PST 24
Peak memory 251884 kb
Host smart-4c92db73-f506-45ed-8810-5a1bfe7b664b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15660
0381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.156600381
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2748739428
Short name T458
Test name
Test status
Simulation time 40339055680 ps
CPU time 1154.37 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 02:10:41 PM PST 24
Peak memory 272744 kb
Host smart-419a5546-14ab-4d12-b89f-9bb787dc413a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748739428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2748739428
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2696783303
Short name T45
Test name
Test status
Simulation time 218106140 ps
CPU time 12.21 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:51:37 PM PST 24
Peak memory 254612 kb
Host smart-46d3fb6a-812e-4636-8f37-76440a0fb8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26967
83303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2696783303
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.467169472
Short name T92
Test name
Test status
Simulation time 772508078 ps
CPU time 46.84 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:52:08 PM PST 24
Peak memory 255472 kb
Host smart-c89b499a-73ab-4a57-9f14-b82dbb227964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46716
9472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.467169472
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3116455665
Short name T667
Test name
Test status
Simulation time 2780679006 ps
CPU time 39.56 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:52:05 PM PST 24
Peak memory 255952 kb
Host smart-7e124480-5643-4f80-a504-28d8518d3d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31164
55665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3116455665
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1613667183
Short name T261
Test name
Test status
Simulation time 193252483662 ps
CPU time 3000.9 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 02:41:27 PM PST 24
Peak memory 289984 kb
Host smart-98e69b80-31d8-4d7e-8195-36fc40684f8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613667183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1613667183
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2110541862
Short name T681
Test name
Test status
Simulation time 47022403 ps
CPU time 2.85 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:31 PM PST 24
Peak memory 249036 kb
Host smart-e38b05d6-b879-4031-9b85-1932a913578f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2110541862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2110541862
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.30297097
Short name T2
Test name
Test status
Simulation time 13010280419 ps
CPU time 1387.57 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 02:14:38 PM PST 24
Peak memory 283608 kb
Host smart-6a41ac16-bf79-411c-9f35-0e09837a8369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30297097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.30297097
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3564888187
Short name T640
Test name
Test status
Simulation time 1917057480 ps
CPU time 6.81 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:37 PM PST 24
Peak memory 240752 kb
Host smart-1d282ca5-c496-4e0e-a16e-d557e2498696
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3564888187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3564888187
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2366374201
Short name T603
Test name
Test status
Simulation time 5728126251 ps
CPU time 102.6 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:53:12 PM PST 24
Peak memory 256800 kb
Host smart-c98f8233-674a-449c-9822-a13d8558cd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
74201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2366374201
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1977153430
Short name T605
Test name
Test status
Simulation time 182402048 ps
CPU time 18.29 seconds
Started Mar 07 01:51:23 PM PST 24
Finished Mar 07 01:51:42 PM PST 24
Peak memory 254608 kb
Host smart-5e7f181a-0785-4593-b172-f94a66d63928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19771
53430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1977153430
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2563529419
Short name T490
Test name
Test status
Simulation time 109502784281 ps
CPU time 1382.73 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 02:14:30 PM PST 24
Peak memory 273224 kb
Host smart-6b2606e0-1a5b-41cb-8fe1-53014aed26a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563529419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2563529419
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2672822701
Short name T470
Test name
Test status
Simulation time 10879494046 ps
CPU time 117.7 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 01:53:31 PM PST 24
Peak memory 246876 kb
Host smart-f986d3f5-682c-4264-afb0-68ef2a54e4b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672822701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2672822701
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3477218631
Short name T662
Test name
Test status
Simulation time 1428528696 ps
CPU time 23.6 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 01:51:50 PM PST 24
Peak memory 248900 kb
Host smart-e41f6cbd-d98f-4fc2-bd7d-c1f33b46a897
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34772
18631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3477218631
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2606798620
Short name T358
Test name
Test status
Simulation time 240474054 ps
CPU time 18.3 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:51:42 PM PST 24
Peak memory 248436 kb
Host smart-3d26e9c5-0d73-4621-921e-0c1d5ec5ddf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26067
98620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2606798620
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1641604403
Short name T508
Test name
Test status
Simulation time 164341167 ps
CPU time 10.87 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:51:41 PM PST 24
Peak memory 247172 kb
Host smart-46c86cc3-7976-4a64-9d91-9eafb13703fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16416
04403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1641604403
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3370526151
Short name T691
Test name
Test status
Simulation time 3355773596 ps
CPU time 48.75 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:52:14 PM PST 24
Peak memory 249044 kb
Host smart-d3a50bbd-beaa-4279-94b1-b0945f01f19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33705
26151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3370526151
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3840262607
Short name T69
Test name
Test status
Simulation time 156365350 ps
CPU time 2.94 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:32 PM PST 24
Peak memory 249124 kb
Host smart-3e811e57-8452-437a-bdb7-02e832241596
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3840262607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3840262607
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2574839661
Short name T383
Test name
Test status
Simulation time 47393159468 ps
CPU time 1242.9 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 02:12:09 PM PST 24
Peak memory 283632 kb
Host smart-55d1905c-7c4a-4bc3-8e20-d743aec9eb68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574839661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2574839661
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2605233940
Short name T638
Test name
Test status
Simulation time 149175616 ps
CPU time 10.06 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 240780 kb
Host smart-90e6e010-b6e5-403a-a891-0de8623a95bd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2605233940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2605233940
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3756913252
Short name T486
Test name
Test status
Simulation time 8887063769 ps
CPU time 121.58 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:53:27 PM PST 24
Peak memory 256512 kb
Host smart-40b330fc-f1b1-483e-80e4-5eb978297fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37569
13252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3756913252
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3371464320
Short name T678
Test name
Test status
Simulation time 228066665 ps
CPU time 15.03 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 01:51:47 PM PST 24
Peak memory 251808 kb
Host smart-30b4c20a-bc3e-40a8-ba94-9068eafa2ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33714
64320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3371464320
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1700605219
Short name T423
Test name
Test status
Simulation time 11566286417 ps
CPU time 699.99 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:03:10 PM PST 24
Peak memory 265416 kb
Host smart-da729876-c811-46b4-bae1-ec4a197e18d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700605219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1700605219
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1615922672
Short name T194
Test name
Test status
Simulation time 470895523 ps
CPU time 13.32 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 249004 kb
Host smart-32eca844-6d16-4f40-9f22-872a53cae8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16159
22672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1615922672
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.2940680812
Short name T595
Test name
Test status
Simulation time 8274192899 ps
CPU time 45.27 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:52:14 PM PST 24
Peak memory 254248 kb
Host smart-5b0039ce-4af1-4724-a4a7-5aae1ea92311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29406
80812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.2940680812
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.730978822
Short name T437
Test name
Test status
Simulation time 1293420839 ps
CPU time 42.39 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:52:13 PM PST 24
Peak memory 255404 kb
Host smart-8f33fbc5-6fb8-4776-a385-82cd279633eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73097
8822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.730978822
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3483348963
Short name T192
Test name
Test status
Simulation time 746560747 ps
CPU time 40.67 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 01:52:12 PM PST 24
Peak memory 255796 kb
Host smart-ca81e487-843c-4449-b896-1177ffaedfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34833
48963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3483348963
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.1979972358
Short name T205
Test name
Test status
Simulation time 20946107 ps
CPU time 2.63 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 249132 kb
Host smart-2eb79169-e723-469a-be9c-c161d1ebd85f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1979972358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.1979972358
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3090279911
Short name T557
Test name
Test status
Simulation time 102963726560 ps
CPU time 2092.37 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:26:22 PM PST 24
Peak memory 286396 kb
Host smart-052978c6-9002-4994-ae99-8c224511d05e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090279911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3090279911
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.660170557
Short name T405
Test name
Test status
Simulation time 469397255 ps
CPU time 7.55 seconds
Started Mar 07 01:51:37 PM PST 24
Finished Mar 07 01:51:45 PM PST 24
Peak memory 240712 kb
Host smart-55f50ba6-702a-48b9-b0b9-3403e62fd9b5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=660170557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.660170557
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2449734853
Short name T388
Test name
Test status
Simulation time 242251496 ps
CPU time 19.19 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 255708 kb
Host smart-5e7884de-f3a7-4f32-ab67-a29bfafc627a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24497
34853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2449734853
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1068053981
Short name T345
Test name
Test status
Simulation time 1036234507 ps
CPU time 26.4 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 01:52:00 PM PST 24
Peak memory 255460 kb
Host smart-6948d16f-9112-4406-8c51-cfdf4f1431bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10680
53981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1068053981
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.587063085
Short name T258
Test name
Test status
Simulation time 56283205912 ps
CPU time 2075.08 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 02:26:04 PM PST 24
Peak memory 284256 kb
Host smart-9113db96-88ea-4293-b811-140e61096e05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587063085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.587063085
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.49715387
Short name T607
Test name
Test status
Simulation time 9737231702 ps
CPU time 208.76 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 01:55:00 PM PST 24
Peak memory 254784 kb
Host smart-dcaa6fac-7b11-4ac8-bc11-e5cf0c0b15bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49715387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.49715387
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.3485829707
Short name T648
Test name
Test status
Simulation time 93754949 ps
CPU time 7.36 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 249044 kb
Host smart-6c141597-a1b8-4e7b-8448-b35b529f9487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34858
29707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.3485829707
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2924882959
Short name T99
Test name
Test status
Simulation time 304067064 ps
CPU time 22.16 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 253620 kb
Host smart-12dfcdbd-1c31-4d66-b3bc-52346c7c30fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29248
82959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2924882959
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.4148650679
Short name T73
Test name
Test status
Simulation time 925732458 ps
CPU time 50.38 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:52:21 PM PST 24
Peak memory 256724 kb
Host smart-b4b54122-ed90-4af6-adb6-7fae867ba440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41486
50679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.4148650679
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.285366185
Short name T530
Test name
Test status
Simulation time 166066903 ps
CPU time 14.53 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 248988 kb
Host smart-2c431847-654b-4e5b-bb0e-26e911640941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28536
6185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.285366185
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1506718802
Short name T494
Test name
Test status
Simulation time 18243230860 ps
CPU time 1378.36 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:14:28 PM PST 24
Peak memory 289748 kb
Host smart-975b5a19-0b9c-41cf-9f1d-f881c794c15e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506718802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1506718802
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1727593194
Short name T257
Test name
Test status
Simulation time 32479036292 ps
CPU time 1878.76 seconds
Started Mar 07 01:51:32 PM PST 24
Finished Mar 07 02:22:51 PM PST 24
Peak memory 290112 kb
Host smart-b86b28f6-0196-4152-9c0f-489c9b4f75d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727593194 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1727593194
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3505668076
Short name T207
Test name
Test status
Simulation time 121098687 ps
CPU time 3.19 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:51:28 PM PST 24
Peak memory 249152 kb
Host smart-b3734004-0b53-45bb-ae21-ae144401536f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3505668076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3505668076
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2413028588
Short name T26
Test name
Test status
Simulation time 149652144925 ps
CPU time 2517.34 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 02:33:29 PM PST 24
Peak memory 289456 kb
Host smart-ec6677ce-3b6d-4013-83e9-94e23b361bec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413028588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2413028588
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.938004512
Short name T511
Test name
Test status
Simulation time 148519895 ps
CPU time 8.95 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:51:31 PM PST 24
Peak memory 240872 kb
Host smart-bf887cc6-1a11-4961-9c03-48110045c086
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=938004512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.938004512
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3855628693
Short name T117
Test name
Test status
Simulation time 6506171996 ps
CPU time 135.18 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:53:44 PM PST 24
Peak memory 257236 kb
Host smart-a1bb3553-4b3f-4cf9-970d-1835bd042d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
28693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3855628693
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.4271101001
Short name T18
Test name
Test status
Simulation time 1076520488 ps
CPU time 19.8 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 247268 kb
Host smart-7f9d3b47-dce4-4ffc-8b1b-dc212d1aff64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711
01001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.4271101001
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.914189155
Short name T318
Test name
Test status
Simulation time 40002740114 ps
CPU time 2282.82 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 02:29:32 PM PST 24
Peak memory 273308 kb
Host smart-16855eb1-38db-4cf0-8650-858a913449c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914189155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.914189155
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2751802590
Short name T552
Test name
Test status
Simulation time 94820900011 ps
CPU time 2047.2 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 02:25:36 PM PST 24
Peak memory 283532 kb
Host smart-751d5107-b63b-4051-8b40-e73ff6924b0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751802590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2751802590
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4145854826
Short name T65
Test name
Test status
Simulation time 31933779733 ps
CPU time 336.05 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:57:05 PM PST 24
Peak memory 247664 kb
Host smart-46126954-c9ad-423a-865b-f461a9e94403
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145854826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4145854826
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4085167940
Short name T575
Test name
Test status
Simulation time 339406053 ps
CPU time 11.66 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 01:51:39 PM PST 24
Peak memory 248972 kb
Host smart-b393a786-2382-4ae7-a0c0-9f3f2a0b1270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
67940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4085167940
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3738232690
Short name T72
Test name
Test status
Simulation time 9114340523 ps
CPU time 34.98 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 01:52:13 PM PST 24
Peak memory 255212 kb
Host smart-73ac0bd5-7e9c-49c4-a5b5-89e5146499a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37382
32690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3738232690
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1984498012
Short name T382
Test name
Test status
Simulation time 780649526 ps
CPU time 20.37 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 01:51:51 PM PST 24
Peak memory 247264 kb
Host smart-11c07d49-cbf4-4e55-b6c8-18c596dc0984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19844
98012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1984498012
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1290298845
Short name T477
Test name
Test status
Simulation time 51786298 ps
CPU time 2.85 seconds
Started Mar 07 01:51:39 PM PST 24
Finished Mar 07 01:51:42 PM PST 24
Peak memory 240752 kb
Host smart-ccb62aa9-bbee-4f69-a334-faecc89dc128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12902
98845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1290298845
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2950269653
Short name T90
Test name
Test status
Simulation time 147882545844 ps
CPU time 2352.29 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 02:30:43 PM PST 24
Peak memory 289368 kb
Host smart-77750b05-903d-409e-8508-a019e5722526
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950269653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2950269653
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1218110725
Short name T212
Test name
Test status
Simulation time 14749450 ps
CPU time 2.36 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 01:51:29 PM PST 24
Peak memory 249164 kb
Host smart-05b293d7-28ba-46ea-a207-c1cafa6617a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1218110725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1218110725
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3666976089
Short name T574
Test name
Test status
Simulation time 87010819983 ps
CPU time 1459.52 seconds
Started Mar 07 01:51:33 PM PST 24
Finished Mar 07 02:15:53 PM PST 24
Peak memory 285416 kb
Host smart-da8eef58-7de3-47e5-8982-3e2309776c9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666976089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3666976089
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.791013204
Short name T446
Test name
Test status
Simulation time 167121252 ps
CPU time 10.14 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 249032 kb
Host smart-9119a57e-4803-4d3b-823f-2c084d0c3901
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=791013204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.791013204
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2523682234
Short name T250
Test name
Test status
Simulation time 1608060653 ps
CPU time 156.05 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:54:05 PM PST 24
Peak memory 250116 kb
Host smart-38fc896f-7766-4a5f-b474-c42b9fd0c456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25236
82234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2523682234
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.327839596
Short name T650
Test name
Test status
Simulation time 161995403 ps
CPU time 16.95 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 01:51:44 PM PST 24
Peak memory 255372 kb
Host smart-a0f3dcdd-0139-4b8f-b4fe-3c013f24a965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32783
9596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.327839596
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3148691064
Short name T116
Test name
Test status
Simulation time 342178974210 ps
CPU time 2942.74 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 02:40:34 PM PST 24
Peak memory 287456 kb
Host smart-43fc370c-eab1-4523-a40d-3a51cdc235c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148691064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3148691064
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3302072070
Short name T680
Test name
Test status
Simulation time 14513174784 ps
CPU time 1580.34 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:17:50 PM PST 24
Peak memory 289208 kb
Host smart-ae45f25f-604c-4626-8541-6a4c39fc2f40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302072070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3302072070
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1648033725
Short name T23
Test name
Test status
Simulation time 13992242293 ps
CPU time 542.57 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 02:00:30 PM PST 24
Peak memory 246936 kb
Host smart-45273cd1-4110-44e0-9c33-fdf23275d206
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648033725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1648033725
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2000802396
Short name T463
Test name
Test status
Simulation time 568111657 ps
CPU time 38.49 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:52:08 PM PST 24
Peak memory 255308 kb
Host smart-045cd224-6f11-447f-ac1d-406305d5e159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20008
02396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2000802396
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3520125179
Short name T396
Test name
Test status
Simulation time 180467378 ps
CPU time 20.11 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 247548 kb
Host smart-8722a961-2e30-4ca9-991c-26bca4698084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35201
25179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3520125179
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4269329819
Short name T235
Test name
Test status
Simulation time 11342619553 ps
CPU time 41.03 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 01:52:19 PM PST 24
Peak memory 255604 kb
Host smart-f9522ede-0b95-4e4d-a169-2663809bcce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42693
29819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4269329819
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3722866455
Short name T342
Test name
Test status
Simulation time 797254755 ps
CPU time 11.79 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 248976 kb
Host smart-2b49a081-1223-4cfe-bf03-f55f1460e965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37228
66455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3722866455
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1457854868
Short name T61
Test name
Test status
Simulation time 250852559302 ps
CPU time 2159.23 seconds
Started Mar 07 01:51:30 PM PST 24
Finished Mar 07 02:27:30 PM PST 24
Peak memory 281832 kb
Host smart-1d8c665c-8313-4138-bed1-b50319cf7afc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457854868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1457854868
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.1139140388
Short name T646
Test name
Test status
Simulation time 140473940607 ps
CPU time 2446.22 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 02:32:17 PM PST 24
Peak memory 285976 kb
Host smart-390b3851-2a79-4aab-ab64-095d92bd94a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139140388 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.1139140388
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1552639090
Short name T44
Test name
Test status
Simulation time 45850910 ps
CPU time 2.95 seconds
Started Mar 07 01:51:54 PM PST 24
Finished Mar 07 01:51:57 PM PST 24
Peak memory 249176 kb
Host smart-ebf663c0-ea1d-4f76-9262-5c741c913ebc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1552639090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1552639090
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3674997823
Short name T365
Test name
Test status
Simulation time 603402307 ps
CPU time 26.83 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 01:52:09 PM PST 24
Peak memory 240760 kb
Host smart-0b954f46-8e3a-47d9-955a-c49e3d3f379a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3674997823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3674997823
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3798512051
Short name T387
Test name
Test status
Simulation time 20822510956 ps
CPU time 75.2 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:53:00 PM PST 24
Peak memory 256396 kb
Host smart-72ba934b-5b1a-4c04-9c8f-73624f50b9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37985
12051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3798512051
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3772097570
Short name T685
Test name
Test status
Simulation time 558158914 ps
CPU time 18.95 seconds
Started Mar 07 01:51:35 PM PST 24
Finished Mar 07 01:51:54 PM PST 24
Peak memory 253980 kb
Host smart-452c785f-f662-45aa-9df7-5c215d10cad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37720
97570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3772097570
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1859748140
Short name T41
Test name
Test status
Simulation time 68676395014 ps
CPU time 1536.35 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 02:17:19 PM PST 24
Peak memory 289824 kb
Host smart-3c36e835-a046-429b-a1f1-748eef5362a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859748140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1859748140
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1340684911
Short name T218
Test name
Test status
Simulation time 24578030 ps
CPU time 3.67 seconds
Started Mar 07 01:51:31 PM PST 24
Finished Mar 07 01:51:35 PM PST 24
Peak memory 240800 kb
Host smart-c9621ebd-03c3-4fd3-b829-1f883146be0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
84911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1340684911
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2330407818
Short name T541
Test name
Test status
Simulation time 837477670 ps
CPU time 57.65 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:52:47 PM PST 24
Peak memory 254768 kb
Host smart-9f6630cd-6c18-403c-9138-434a69b39c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23304
07818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2330407818
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2170884873
Short name T103
Test name
Test status
Simulation time 2659643462 ps
CPU time 20.4 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:52:10 PM PST 24
Peak memory 255788 kb
Host smart-3851ae79-027a-49f4-87a1-b12099bc6118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21708
84873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2170884873
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.67085191
Short name T598
Test name
Test status
Simulation time 30043525710 ps
CPU time 1486.69 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 02:16:25 PM PST 24
Peak memory 289348 kb
Host smart-dcba45d8-357e-41eb-8d5e-0ddd412d2228
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67085191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_hand
ler_stress_all.67085191
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.726189998
Short name T1
Test name
Test status
Simulation time 84791097 ps
CPU time 3.76 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 249196 kb
Host smart-0fa8c034-e93a-4f17-8ea4-43e7176dd452
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=726189998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.726189998
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1418430960
Short name T24
Test name
Test status
Simulation time 121904478633 ps
CPU time 2232.91 seconds
Started Mar 07 01:51:37 PM PST 24
Finished Mar 07 02:28:50 PM PST 24
Peak memory 289244 kb
Host smart-888dc7f8-2edc-4f04-91a2-f3e219689194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418430960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1418430960
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1073801036
Short name T123
Test name
Test status
Simulation time 602526541 ps
CPU time 8.19 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:51:57 PM PST 24
Peak memory 240800 kb
Host smart-a5918040-e01d-43bc-8978-0c4a9163d181
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1073801036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1073801036
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3029845101
Short name T385
Test name
Test status
Simulation time 4906782934 ps
CPU time 307.25 seconds
Started Mar 07 01:51:47 PM PST 24
Finished Mar 07 01:56:54 PM PST 24
Peak memory 256688 kb
Host smart-a8513355-0109-4ebd-b8dd-463026323f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30298
45101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3029845101
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1682419312
Short name T408
Test name
Test status
Simulation time 189043974 ps
CPU time 13.03 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 01:51:51 PM PST 24
Peak memory 255168 kb
Host smart-ce33a847-a3ca-4d21-8b6c-634289e34dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16824
19312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1682419312
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2992706306
Short name T404
Test name
Test status
Simulation time 247411638020 ps
CPU time 2161.61 seconds
Started Mar 07 01:51:35 PM PST 24
Finished Mar 07 02:27:37 PM PST 24
Peak memory 287376 kb
Host smart-699b5c5d-c0bf-4c5e-b933-2f7425813b54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992706306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2992706306
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3166900570
Short name T301
Test name
Test status
Simulation time 57309993145 ps
CPU time 442.36 seconds
Started Mar 07 01:51:51 PM PST 24
Finished Mar 07 01:59:14 PM PST 24
Peak memory 247692 kb
Host smart-a45b93cb-eb22-47a0-a029-76793a30fe44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166900570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3166900570
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3071351653
Short name T687
Test name
Test status
Simulation time 8843543772 ps
CPU time 63.23 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 01:52:44 PM PST 24
Peak memory 249064 kb
Host smart-095a1ac9-1f25-4ec9-88ba-e427fcc2d1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30713
51653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3071351653
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.274095536
Short name T391
Test name
Test status
Simulation time 2272808613 ps
CPU time 31.14 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 01:52:14 PM PST 24
Peak memory 255708 kb
Host smart-a57c218a-c26d-4e47-9534-98dbe19a3674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27409
5536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.274095536
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2261621172
Short name T50
Test name
Test status
Simulation time 1245663248 ps
CPU time 22.5 seconds
Started Mar 07 01:51:38 PM PST 24
Finished Mar 07 01:52:00 PM PST 24
Peak memory 255168 kb
Host smart-d34f88c0-31ac-44fa-b17a-08f9abfdbbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
21172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2261621172
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1121732244
Short name T569
Test name
Test status
Simulation time 59195424 ps
CPU time 4.76 seconds
Started Mar 07 01:51:43 PM PST 24
Finished Mar 07 01:51:48 PM PST 24
Peak memory 240816 kb
Host smart-dbcb73a0-c652-4a9d-99b4-6f75af0b4a01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
32244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1121732244
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.4129855639
Short name T651
Test name
Test status
Simulation time 49287901533 ps
CPU time 1311.51 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 02:13:32 PM PST 24
Peak memory 290024 kb
Host smart-1b7e22ce-3aa8-49ba-a251-5cbe667138d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129855639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.4129855639
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2729109024
Short name T563
Test name
Test status
Simulation time 260279848595 ps
CPU time 5187.06 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 03:18:10 PM PST 24
Peak memory 348632 kb
Host smart-961a4e63-a867-4701-a36c-918b670e2ae8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729109024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2729109024
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.49066508
Short name T213
Test name
Test status
Simulation time 25779149 ps
CPU time 2.25 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 01:51:44 PM PST 24
Peak memory 249180 kb
Host smart-059bbdbb-f3c7-4c8d-bac4-01f84b8b79e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=49066508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.49066508
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1509204873
Short name T493
Test name
Test status
Simulation time 67914079995 ps
CPU time 2059.48 seconds
Started Mar 07 01:51:44 PM PST 24
Finished Mar 07 02:26:04 PM PST 24
Peak memory 286796 kb
Host smart-cd909acb-2868-493e-bb27-81038a0098d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509204873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1509204873
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.422593528
Short name T596
Test name
Test status
Simulation time 2747681531 ps
CPU time 37.46 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 01:52:19 PM PST 24
Peak memory 240860 kb
Host smart-865290bd-05bd-4709-ab58-1ea00f233815
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=422593528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.422593528
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.936388812
Short name T220
Test name
Test status
Simulation time 1755720201 ps
CPU time 129.93 seconds
Started Mar 07 01:51:39 PM PST 24
Finished Mar 07 01:53:49 PM PST 24
Peak memory 256624 kb
Host smart-19ffebd5-bcaf-4bb6-9e36-5ea3d7de32e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93638
8812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.936388812
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.439436160
Short name T430
Test name
Test status
Simulation time 627446267 ps
CPU time 26.61 seconds
Started Mar 07 01:51:36 PM PST 24
Finished Mar 07 01:52:03 PM PST 24
Peak memory 256512 kb
Host smart-10a3d0f8-085e-4a9e-bba0-975b9a9013a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43943
6160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.439436160
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2332019167
Short name T320
Test name
Test status
Simulation time 24322447725 ps
CPU time 1479.92 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 02:16:37 PM PST 24
Peak memory 273132 kb
Host smart-ebb98eb3-92c9-4659-9b1f-93421c120987
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332019167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2332019167
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.875764323
Short name T562
Test name
Test status
Simulation time 65411857423 ps
CPU time 1133.7 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 02:10:36 PM PST 24
Peak memory 265060 kb
Host smart-6ec13bc6-fa94-4da1-997f-63a2ffe72c3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875764323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.875764323
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2035937793
Short name T548
Test name
Test status
Simulation time 16218037794 ps
CPU time 347.38 seconds
Started Mar 07 01:51:37 PM PST 24
Finished Mar 07 01:57:24 PM PST 24
Peak memory 247972 kb
Host smart-552ba375-f1f2-4bc4-ba69-888817bab6ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035937793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2035937793
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.446452587
Short name T694
Test name
Test status
Simulation time 480217531 ps
CPU time 30.37 seconds
Started Mar 07 01:51:46 PM PST 24
Finished Mar 07 01:52:16 PM PST 24
Peak memory 255776 kb
Host smart-5707f1e9-1008-4600-a5b0-ab5df885fe1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44645
2587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.446452587
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3232592614
Short name T462
Test name
Test status
Simulation time 241501208 ps
CPU time 21.55 seconds
Started Mar 07 01:51:35 PM PST 24
Finished Mar 07 01:51:57 PM PST 24
Peak memory 247324 kb
Host smart-ae977391-585a-4c6a-a67a-9f9f2415d4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32325
92614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3232592614
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2573095005
Short name T221
Test name
Test status
Simulation time 51993692 ps
CPU time 3.03 seconds
Started Mar 07 01:51:46 PM PST 24
Finished Mar 07 01:51:50 PM PST 24
Peak memory 240780 kb
Host smart-f76c698d-076c-455a-b6de-14e98d49656f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
95005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2573095005
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1426137808
Short name T509
Test name
Test status
Simulation time 324955351 ps
CPU time 10.66 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 248968 kb
Host smart-0f5601dc-ff73-4e5c-a706-37647d167a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
37808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1426137808
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3065737247
Short name T268
Test name
Test status
Simulation time 350868247576 ps
CPU time 2368.78 seconds
Started Mar 07 01:51:43 PM PST 24
Finished Mar 07 02:31:12 PM PST 24
Peak memory 282444 kb
Host smart-82c73819-09ac-4cbd-9871-ddfdcaa24292
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065737247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3065737247
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2333015402
Short name T208
Test name
Test status
Simulation time 49931049 ps
CPU time 2.27 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:51:18 PM PST 24
Peak memory 249164 kb
Host smart-c9de64f0-c5c1-4648-8a48-eddccf07bb99
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2333015402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2333015402
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.975046688
Short name T550
Test name
Test status
Simulation time 100463262182 ps
CPU time 1577.61 seconds
Started Mar 07 01:51:02 PM PST 24
Finished Mar 07 02:17:20 PM PST 24
Peak memory 265436 kb
Host smart-1a3863f1-e2d8-4a4c-be20-cf2ef0881a25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975046688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.975046688
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1485222890
Short name T472
Test name
Test status
Simulation time 816786239 ps
CPU time 34.88 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 240716 kb
Host smart-79d83149-1bab-4ff0-8a62-669d8935a233
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1485222890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1485222890
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1099154929
Short name T245
Test name
Test status
Simulation time 3756754584 ps
CPU time 217.09 seconds
Started Mar 07 01:51:11 PM PST 24
Finished Mar 07 01:54:48 PM PST 24
Peak memory 251072 kb
Host smart-e912b9bc-a695-4830-ae2b-8a1b757cab02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10991
54929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1099154929
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2652593092
Short name T370
Test name
Test status
Simulation time 758059506 ps
CPU time 19.83 seconds
Started Mar 07 01:51:05 PM PST 24
Finished Mar 07 01:51:26 PM PST 24
Peak memory 255160 kb
Host smart-eba84a4e-0052-49e3-9452-61bc81f1391c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26525
93092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2652593092
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1463383610
Short name T341
Test name
Test status
Simulation time 11842097895 ps
CPU time 1173.21 seconds
Started Mar 07 01:51:11 PM PST 24
Finished Mar 07 02:10:44 PM PST 24
Peak memory 289348 kb
Host smart-6311955b-ffaf-4f34-abc3-153751bcbbf3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463383610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1463383610
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.3516784609
Short name T649
Test name
Test status
Simulation time 167623130602 ps
CPU time 2674.65 seconds
Started Mar 07 01:51:08 PM PST 24
Finished Mar 07 02:35:44 PM PST 24
Peak memory 289312 kb
Host smart-93c6a572-dbea-45d6-87f5-f1af79223a9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516784609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.3516784609
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.596384447
Short name T22
Test name
Test status
Simulation time 6018234399 ps
CPU time 115.71 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 01:53:09 PM PST 24
Peak memory 246868 kb
Host smart-17bcad47-d9e0-4555-9c4b-e85cd1656e76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596384447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.596384447
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.42206585
Short name T449
Test name
Test status
Simulation time 8334643518 ps
CPU time 42.78 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:51 PM PST 24
Peak memory 248972 kb
Host smart-cb6c96a6-502b-41f9-881e-24987739394c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42206
585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.42206585
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.3778486536
Short name T496
Test name
Test status
Simulation time 428889782 ps
CPU time 31.73 seconds
Started Mar 07 01:51:08 PM PST 24
Finished Mar 07 01:51:41 PM PST 24
Peak memory 255312 kb
Host smart-c2fbc51f-9404-4de1-9327-cb83399013a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37784
86536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3778486536
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3035772952
Short name T37
Test name
Test status
Simulation time 175775863 ps
CPU time 11.6 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 01:51:19 PM PST 24
Peak memory 266460 kb
Host smart-9b2616d1-095b-4569-9e3f-8f71d3e93290
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3035772952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3035772952
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.2843365714
Short name T599
Test name
Test status
Simulation time 451234491 ps
CPU time 32.66 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:51:48 PM PST 24
Peak memory 248964 kb
Host smart-c8d0ad9d-1410-487b-b52d-173814e3e967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28433
65714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2843365714
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3703950913
Short name T354
Test name
Test status
Simulation time 421670607 ps
CPU time 36.17 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 248952 kb
Host smart-0e2e9520-6b2b-4e52-85f6-f8656003a888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37039
50913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3703950913
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.116264635
Short name T537
Test name
Test status
Simulation time 35170017065 ps
CPU time 2268.71 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 02:28:58 PM PST 24
Peak memory 286904 kb
Host smart-1a5a448b-2455-4588-af70-b7f633ca5f4b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116264635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.116264635
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1980376947
Short name T252
Test name
Test status
Simulation time 20385674469 ps
CPU time 1376.82 seconds
Started Mar 07 01:51:53 PM PST 24
Finished Mar 07 02:14:50 PM PST 24
Peak memory 272660 kb
Host smart-d4526826-5db9-4c21-a4fa-84ea355905f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980376947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1980376947
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1892626615
Short name T351
Test name
Test status
Simulation time 26886340454 ps
CPU time 322.32 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:57:08 PM PST 24
Peak memory 256616 kb
Host smart-054fcf20-59c8-47e3-b0a9-1f31365a07e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
26615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1892626615
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2012971239
Short name T534
Test name
Test status
Simulation time 616962811 ps
CPU time 11.41 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:52:00 PM PST 24
Peak memory 251852 kb
Host smart-585cbd10-4393-4d62-917c-7e1dc3310356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20129
71239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2012971239
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4120908239
Short name T314
Test name
Test status
Simulation time 60846994375 ps
CPU time 2494.23 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 02:33:23 PM PST 24
Peak memory 273680 kb
Host smart-54e91b78-f992-4562-be2a-8aa143fa649d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120908239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4120908239
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.815487230
Short name T556
Test name
Test status
Simulation time 37045940321 ps
CPU time 2538.24 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 02:34:07 PM PST 24
Peak memory 289128 kb
Host smart-f780b629-75ac-4111-aec0-ccea63570acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815487230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.815487230
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1775219961
Short name T302
Test name
Test status
Simulation time 17399734029 ps
CPU time 141.51 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:54:07 PM PST 24
Peak memory 247760 kb
Host smart-6896ad8e-17ff-4a02-9bf7-a6a499f1e490
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775219961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1775219961
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2532052314
Short name T456
Test name
Test status
Simulation time 297967125 ps
CPU time 19.33 seconds
Started Mar 07 01:51:43 PM PST 24
Finished Mar 07 01:52:02 PM PST 24
Peak memory 254496 kb
Host smart-5d5261f2-9c81-425a-9bad-03148d38b558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25320
52314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2532052314
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.4277274367
Short name T343
Test name
Test status
Simulation time 1532938559 ps
CPU time 53.65 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 01:52:46 PM PST 24
Peak memory 255188 kb
Host smart-91d44325-0639-4b24-9785-5c52e59ca302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42772
74367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.4277274367
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1098086909
Short name T272
Test name
Test status
Simulation time 207609057 ps
CPU time 14.11 seconds
Started Mar 07 01:51:44 PM PST 24
Finished Mar 07 01:51:59 PM PST 24
Peak memory 247328 kb
Host smart-038c818f-041f-4b95-bb08-ec8015c5d70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10980
86909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1098086909
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.508731608
Short name T46
Test name
Test status
Simulation time 774458461 ps
CPU time 44.53 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:52:30 PM PST 24
Peak memory 256076 kb
Host smart-090e4588-8fe0-4816-980d-0e0bfd844290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50873
1608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.508731608
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2561920641
Short name T267
Test name
Test status
Simulation time 94242030719 ps
CPU time 3269.31 seconds
Started Mar 07 01:51:36 PM PST 24
Finished Mar 07 02:46:05 PM PST 24
Peak memory 301720 kb
Host smart-9d09d7df-5376-40ab-b43e-5f61812b8856
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561920641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2561920641
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.859235770
Short name T545
Test name
Test status
Simulation time 5737323754 ps
CPU time 160.34 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:54:30 PM PST 24
Peak memory 248988 kb
Host smart-14a09579-229b-44bc-960f-1ff58a9f44c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85923
5770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.859235770
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.1437389221
Short name T454
Test name
Test status
Simulation time 2103125703 ps
CPU time 59.17 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:52:48 PM PST 24
Peak memory 248780 kb
Host smart-7dbf2693-6bad-4c3d-a8ef-e18f19d014b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14373
89221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.1437389221
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.4177413069
Short name T288
Test name
Test status
Simulation time 10471505353 ps
CPU time 933.94 seconds
Started Mar 07 01:51:44 PM PST 24
Finished Mar 07 02:07:18 PM PST 24
Peak memory 265468 kb
Host smart-55ce5365-d18f-4d87-9744-81d0c418bf8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177413069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.4177413069
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3736264702
Short name T95
Test name
Test status
Simulation time 12301335564 ps
CPU time 1320.78 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 02:13:46 PM PST 24
Peak memory 281816 kb
Host smart-77497290-b375-422e-8134-c2eb24026b87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736264702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3736264702
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.405774820
Short name T610
Test name
Test status
Simulation time 24311334836 ps
CPU time 492.44 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 01:59:54 PM PST 24
Peak memory 247952 kb
Host smart-1d59bda7-1817-4552-b57b-a2fda00f421b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405774820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.405774820
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3191749817
Short name T439
Test name
Test status
Simulation time 344211700 ps
CPU time 9.4 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 01:51:51 PM PST 24
Peak memory 254588 kb
Host smart-a91a5208-2258-4ae5-97a3-139615241064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31917
49817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3191749817
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3814844354
Short name T633
Test name
Test status
Simulation time 200694299 ps
CPU time 8.53 seconds
Started Mar 07 01:51:44 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 247268 kb
Host smart-92f5468c-b240-4c8e-b36a-0dd0a040a73d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38148
44354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3814844354
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1245665831
Short name T280
Test name
Test status
Simulation time 3650241092 ps
CPU time 71.58 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:53:01 PM PST 24
Peak memory 254912 kb
Host smart-0793c2a6-0d3c-479b-bae2-328797796860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12456
65831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1245665831
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.81322487
Short name T346
Test name
Test status
Simulation time 2050017178 ps
CPU time 35.96 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 01:52:17 PM PST 24
Peak memory 248956 kb
Host smart-3ae2d499-2343-410a-b9ec-39a454970322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81322
487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.81322487
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1209470777
Short name T196
Test name
Test status
Simulation time 37397111528 ps
CPU time 4025.16 seconds
Started Mar 07 01:51:35 PM PST 24
Finished Mar 07 02:58:41 PM PST 24
Peak memory 338420 kb
Host smart-772010fa-21b5-41fd-9565-5ac142af8e59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209470777 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1209470777
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1311017022
Short name T518
Test name
Test status
Simulation time 211959651093 ps
CPU time 2451.77 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 02:32:37 PM PST 24
Peak memory 289476 kb
Host smart-08d6112d-86fb-4aaa-8c97-3b5343c0c8c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311017022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1311017022
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.999160399
Short name T674
Test name
Test status
Simulation time 1792582914 ps
CPU time 56.98 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 01:52:50 PM PST 24
Peak memory 255640 kb
Host smart-a6191648-8fa3-4951-bd92-340a109f6d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99916
0399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.999160399
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.680708670
Short name T443
Test name
Test status
Simulation time 1679675609 ps
CPU time 47.03 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 01:52:40 PM PST 24
Peak memory 254724 kb
Host smart-30460ef3-361e-4300-a8b6-d62e7b37a213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68070
8670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.680708670
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1367140179
Short name T546
Test name
Test status
Simulation time 8489160167 ps
CPU time 876.02 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 02:06:28 PM PST 24
Peak memory 272824 kb
Host smart-37313d39-7dac-48fb-aaef-bc30261fd135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367140179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1367140179
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.581599728
Short name T84
Test name
Test status
Simulation time 83592587745 ps
CPU time 1521.5 seconds
Started Mar 07 01:51:41 PM PST 24
Finished Mar 07 02:17:02 PM PST 24
Peak memory 272616 kb
Host smart-eaa83c17-00dc-4163-93d8-493dff75e7bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581599728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.581599728
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1992789158
Short name T304
Test name
Test status
Simulation time 27545198599 ps
CPU time 567.84 seconds
Started Mar 07 01:51:50 PM PST 24
Finished Mar 07 02:01:18 PM PST 24
Peak memory 248928 kb
Host smart-8143f5c0-aed2-4172-bde9-a60fef8ca9bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992789158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1992789158
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3446244515
Short name T111
Test name
Test status
Simulation time 281755010 ps
CPU time 31.12 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:52:16 PM PST 24
Peak memory 255816 kb
Host smart-a6df81f3-4ace-45ad-b04a-c22b06dc576a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34462
44515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3446244515
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.236291520
Short name T690
Test name
Test status
Simulation time 1298557591 ps
CPU time 22.49 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 01:52:15 PM PST 24
Peak memory 255112 kb
Host smart-574bc387-a786-403e-8401-13c9e3b7ab35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23629
1520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.236291520
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3282460102
Short name T647
Test name
Test status
Simulation time 863403361 ps
CPU time 48.87 seconds
Started Mar 07 01:51:42 PM PST 24
Finished Mar 07 01:52:31 PM PST 24
Peak memory 254576 kb
Host smart-2b2bcf53-5f20-46db-b224-30001f2d96b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32824
60102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3282460102
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.1523735084
Short name T585
Test name
Test status
Simulation time 867750492 ps
CPU time 44.28 seconds
Started Mar 07 01:51:43 PM PST 24
Finished Mar 07 01:52:28 PM PST 24
Peak memory 248968 kb
Host smart-6826819d-2f18-4a1f-a212-891cc9876c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
35084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.1523735084
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2629101525
Short name T451
Test name
Test status
Simulation time 71537811100 ps
CPU time 922.2 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 02:07:19 PM PST 24
Peak memory 284452 kb
Host smart-269f8a75-45cd-4a0d-88f3-cd49fcdde01f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629101525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2629101525
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2377507161
Short name T478
Test name
Test status
Simulation time 3161143214 ps
CPU time 184.36 seconds
Started Mar 07 01:51:49 PM PST 24
Finished Mar 07 01:54:54 PM PST 24
Peak memory 256808 kb
Host smart-a6590876-23d9-47df-810f-d29d8d902a23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23775
07161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2377507161
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3750340743
Short name T112
Test name
Test status
Simulation time 229786048 ps
CPU time 10.1 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 01:52:07 PM PST 24
Peak memory 253480 kb
Host smart-a48c8620-05c0-4dec-b228-56c7177f2146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37503
40743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3750340743
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.414869175
Short name T604
Test name
Test status
Simulation time 45707147174 ps
CPU time 1015.03 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 02:08:53 PM PST 24
Peak memory 272812 kb
Host smart-6287edb4-2288-4c6a-83a4-0bda6eb4a590
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414869175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.414869175
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1929831662
Short name T672
Test name
Test status
Simulation time 32871278430 ps
CPU time 1909.24 seconds
Started Mar 07 01:51:48 PM PST 24
Finished Mar 07 02:23:37 PM PST 24
Peak memory 284644 kb
Host smart-cbf8a25a-5750-4c4e-a35c-ec54b0ccf10d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929831662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1929831662
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.697715926
Short name T308
Test name
Test status
Simulation time 3821468663 ps
CPU time 131.18 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 01:54:10 PM PST 24
Peak memory 256120 kb
Host smart-b1e21c14-975e-468f-a8dd-c19ad24a0065
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697715926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.697715926
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1630175265
Short name T558
Test name
Test status
Simulation time 117950893 ps
CPU time 7.62 seconds
Started Mar 07 01:51:45 PM PST 24
Finished Mar 07 01:51:52 PM PST 24
Peak memory 240796 kb
Host smart-a4333f93-874b-4040-a6de-d794909b1b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16301
75265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1630175265
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.4055768158
Short name T554
Test name
Test status
Simulation time 117298484 ps
CPU time 14.23 seconds
Started Mar 07 01:51:56 PM PST 24
Finished Mar 07 01:52:10 PM PST 24
Peak memory 254676 kb
Host smart-51294fcc-10bb-4a74-bbf7-64b186c6d57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40557
68158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.4055768158
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.507233947
Short name T643
Test name
Test status
Simulation time 23496911 ps
CPU time 3.29 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 01:52:00 PM PST 24
Peak memory 240700 kb
Host smart-e2466c8f-adb8-4f61-bcfa-f262097468ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50723
3947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.507233947
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2650726438
Short name T507
Test name
Test status
Simulation time 2480811024 ps
CPU time 45.31 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 01:52:45 PM PST 24
Peak memory 249060 kb
Host smart-103d1cdf-6227-4a37-ba98-228969e5bdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26507
26438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2650726438
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2155942075
Short name T79
Test name
Test status
Simulation time 26579572842 ps
CPU time 1756.31 seconds
Started Mar 07 01:51:47 PM PST 24
Finished Mar 07 02:21:04 PM PST 24
Peak memory 273200 kb
Host smart-12680139-be99-4c55-b0d3-c9131f46f46f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155942075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2155942075
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2122663477
Short name T412
Test name
Test status
Simulation time 32207065392 ps
CPU time 245.31 seconds
Started Mar 07 01:51:53 PM PST 24
Finished Mar 07 01:55:59 PM PST 24
Peak memory 257188 kb
Host smart-83cb7931-97e2-4fe9-abc3-df7beaeca0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21226
63477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2122663477
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3862677346
Short name T426
Test name
Test status
Simulation time 7498983731 ps
CPU time 67.01 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 01:53:05 PM PST 24
Peak memory 255772 kb
Host smart-6a6eabe5-3e7e-4ccf-8545-f944f9466861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
77346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3862677346
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3700462628
Short name T475
Test name
Test status
Simulation time 13184351566 ps
CPU time 1502.9 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 02:17:01 PM PST 24
Peak memory 289872 kb
Host smart-db056a7c-4a14-4c36-ba3d-31eda60d3ca5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700462628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3700462628
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2270754820
Short name T602
Test name
Test status
Simulation time 5392213518 ps
CPU time 80.92 seconds
Started Mar 07 01:51:54 PM PST 24
Finished Mar 07 01:53:15 PM PST 24
Peak memory 256244 kb
Host smart-881d1b52-94c4-49bf-8c5d-0ba4e1f774be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
54820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2270754820
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3547908311
Short name T401
Test name
Test status
Simulation time 501007920 ps
CPU time 44.81 seconds
Started Mar 07 01:51:47 PM PST 24
Finished Mar 07 01:52:31 PM PST 24
Peak memory 255260 kb
Host smart-7d879fe8-e1c8-4e46-b3dc-4da95952e366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35479
08311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3547908311
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.685649262
Short name T29
Test name
Test status
Simulation time 247468177 ps
CPU time 8.79 seconds
Started Mar 07 01:51:52 PM PST 24
Finished Mar 07 01:52:01 PM PST 24
Peak memory 254532 kb
Host smart-4621d9f5-b4c0-422c-89ea-26f0003acb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68564
9262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.685649262
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3255742894
Short name T535
Test name
Test status
Simulation time 370345302 ps
CPU time 8.31 seconds
Started Mar 07 01:51:50 PM PST 24
Finished Mar 07 01:51:58 PM PST 24
Peak memory 249084 kb
Host smart-0f209250-f7fc-42bf-b20b-b1c9615f1303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32557
42894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3255742894
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3876360023
Short name T63
Test name
Test status
Simulation time 37080942682 ps
CPU time 2380.18 seconds
Started Mar 07 01:52:02 PM PST 24
Finished Mar 07 02:31:43 PM PST 24
Peak memory 289856 kb
Host smart-6c1d77ec-b1cc-493d-ac1f-c4f16de954bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876360023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3876360023
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3408448973
Short name T373
Test name
Test status
Simulation time 14809608100 ps
CPU time 1245.89 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 02:12:48 PM PST 24
Peak memory 289120 kb
Host smart-b4977362-7cc7-4117-98b2-4032fc50db71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408448973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3408448973
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1466255805
Short name T219
Test name
Test status
Simulation time 10934246924 ps
CPU time 163.57 seconds
Started Mar 07 01:51:55 PM PST 24
Finished Mar 07 01:54:39 PM PST 24
Peak memory 256496 kb
Host smart-0ac7f487-d641-47fe-8ec2-42b332bb8c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14662
55805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1466255805
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2073194295
Short name T538
Test name
Test status
Simulation time 2640543602 ps
CPU time 23.99 seconds
Started Mar 07 01:52:02 PM PST 24
Finished Mar 07 01:52:26 PM PST 24
Peak memory 256188 kb
Host smart-85cf5bcd-1254-4a4f-a81a-b92d5edbc43c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20731
94295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2073194295
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.692800304
Short name T238
Test name
Test status
Simulation time 201430217881 ps
CPU time 1912.32 seconds
Started Mar 07 01:51:51 PM PST 24
Finished Mar 07 02:23:44 PM PST 24
Peak memory 272032 kb
Host smart-2f94db36-e9dd-47c3-96bf-549aada688a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692800304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.692800304
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1645464034
Short name T618
Test name
Test status
Simulation time 224258772832 ps
CPU time 1569.8 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 02:18:09 PM PST 24
Peak memory 272648 kb
Host smart-85f795d9-0e77-4c25-88e5-8cb691049888
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645464034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1645464034
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1440041991
Short name T298
Test name
Test status
Simulation time 24156528876 ps
CPU time 487.3 seconds
Started Mar 07 01:51:51 PM PST 24
Finished Mar 07 01:59:59 PM PST 24
Peak memory 247732 kb
Host smart-df895d1e-7c60-449a-95c3-a09573045c15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440041991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1440041991
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2928946986
Short name T56
Test name
Test status
Simulation time 598036928 ps
CPU time 28.72 seconds
Started Mar 07 01:51:51 PM PST 24
Finished Mar 07 01:52:20 PM PST 24
Peak memory 248960 kb
Host smart-a92d8182-f77f-4ca5-8281-1dea302c276e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29289
46986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2928946986
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4189804686
Short name T417
Test name
Test status
Simulation time 5051661950 ps
CPU time 74.29 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 01:53:12 PM PST 24
Peak memory 256404 kb
Host smart-908607c8-535e-4b32-8109-859b5076a88a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41898
04686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4189804686
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.262705109
Short name T499
Test name
Test status
Simulation time 324202426 ps
CPU time 42.8 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:45 PM PST 24
Peak memory 248476 kb
Host smart-6d59560f-83f5-45f7-8970-2e0175d62e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26270
5109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.262705109
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1183384592
Short name T363
Test name
Test status
Simulation time 366407009 ps
CPU time 32.82 seconds
Started Mar 07 01:51:47 PM PST 24
Finished Mar 07 01:52:20 PM PST 24
Peak memory 257084 kb
Host smart-901a0201-0d8f-4f5a-b42c-a373d9661283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11833
84592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1183384592
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.360301047
Short name T675
Test name
Test status
Simulation time 38622204175 ps
CPU time 1769.3 seconds
Started Mar 07 01:51:54 PM PST 24
Finished Mar 07 02:21:24 PM PST 24
Peak memory 289564 kb
Host smart-38dad62a-b703-4309-994c-c075ca65b44e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360301047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.360301047
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.357188029
Short name T14
Test name
Test status
Simulation time 52500171270 ps
CPU time 2817.25 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 02:38:56 PM PST 24
Peak memory 289488 kb
Host smart-d966466e-37a1-4cc9-8feb-b1bd4eba4ba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357188029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.357188029
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.492896402
Short name T438
Test name
Test status
Simulation time 3252739534 ps
CPU time 219.31 seconds
Started Mar 07 01:51:54 PM PST 24
Finished Mar 07 01:55:33 PM PST 24
Peak memory 257240 kb
Host smart-0c6018f6-1e16-4cde-98f0-a945667678d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49289
6402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.492896402
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3579587927
Short name T606
Test name
Test status
Simulation time 134419526 ps
CPU time 17.1 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:19 PM PST 24
Peak memory 254824 kb
Host smart-dde30373-e8de-48b3-8854-f9e87df4da88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35795
87927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3579587927
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1358702050
Short name T590
Test name
Test status
Simulation time 16115724948 ps
CPU time 1554.22 seconds
Started Mar 07 01:52:04 PM PST 24
Finished Mar 07 02:17:59 PM PST 24
Peak memory 289636 kb
Host smart-491b5dcf-2583-4594-bfad-67981f213463
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358702050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1358702050
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.208880583
Short name T260
Test name
Test status
Simulation time 43075790908 ps
CPU time 491.86 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 02:00:19 PM PST 24
Peak memory 247704 kb
Host smart-334708b6-69ff-41cb-b7f5-27887b77fb50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208880583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.208880583
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3495325879
Short name T459
Test name
Test status
Simulation time 117108336 ps
CPU time 8.7 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 01:52:08 PM PST 24
Peak memory 248972 kb
Host smart-2d9771c0-c04e-4e57-90f7-23dccd1e0875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34953
25879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3495325879
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4258919902
Short name T62
Test name
Test status
Simulation time 2329798231 ps
CPU time 37.94 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 01:52:36 PM PST 24
Peak memory 249068 kb
Host smart-507d478a-4a9a-4fe7-ab1f-fd399e8ca865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42589
19902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4258919902
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3527879010
Short name T416
Test name
Test status
Simulation time 448797431 ps
CPU time 25.48 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:27 PM PST 24
Peak memory 255432 kb
Host smart-3492ceaf-c0a0-47b3-85e8-24b00d8dc854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35278
79010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3527879010
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3632747052
Short name T424
Test name
Test status
Simulation time 1085025744 ps
CPU time 29.05 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 01:52:29 PM PST 24
Peak memory 254920 kb
Host smart-00af1785-42d4-40b6-8ff0-53283af81fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36327
47052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3632747052
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2791534643
Short name T371
Test name
Test status
Simulation time 3575723834 ps
CPU time 62.64 seconds
Started Mar 07 01:51:58 PM PST 24
Finished Mar 07 01:53:01 PM PST 24
Peak memory 255320 kb
Host smart-1f238899-9d5a-4c06-a2e0-00c911dfc657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27915
34643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2791534643
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3871623695
Short name T66
Test name
Test status
Simulation time 31771511490 ps
CPU time 1875.7 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 02:23:23 PM PST 24
Peak memory 285556 kb
Host smart-cc6f8d3c-2c46-4fce-982e-c04a20c2625b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871623695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3871623695
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.66350615
Short name T592
Test name
Test status
Simulation time 130613973050 ps
CPU time 2221.4 seconds
Started Mar 07 01:52:00 PM PST 24
Finished Mar 07 02:29:03 PM PST 24
Peak memory 285976 kb
Host smart-fddeb59b-8faf-48cb-9747-412ee9d93923
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66350615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.66350615
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1483400470
Short name T291
Test name
Test status
Simulation time 13228051233 ps
CPU time 203.87 seconds
Started Mar 07 01:51:56 PM PST 24
Finished Mar 07 01:55:20 PM PST 24
Peak memory 247820 kb
Host smart-39c7f17c-11d3-4e39-86be-0f61f36edab7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483400470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1483400470
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.944502327
Short name T654
Test name
Test status
Simulation time 297256581 ps
CPU time 22.98 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 01:52:23 PM PST 24
Peak memory 249028 kb
Host smart-3830d482-fa27-4a85-bd6e-ea0e6ea90f2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94450
2327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.944502327
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2919362293
Short name T422
Test name
Test status
Simulation time 152659370 ps
CPU time 16.66 seconds
Started Mar 07 01:51:56 PM PST 24
Finished Mar 07 01:52:13 PM PST 24
Peak memory 255624 kb
Host smart-d149b431-d694-454c-957e-41ba3b655f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29193
62293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2919362293
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3604781967
Short name T584
Test name
Test status
Simulation time 2693459110 ps
CPU time 47.8 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 01:52:54 PM PST 24
Peak memory 248088 kb
Host smart-8b0016e7-e45b-4ae3-8459-2ce97cf4caec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36047
81967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3604781967
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1772852314
Short name T469
Test name
Test status
Simulation time 413196418 ps
CPU time 16.5 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:18 PM PST 24
Peak memory 248988 kb
Host smart-62577896-8bbe-4055-a2c7-7b887d471ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
52314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1772852314
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.905764635
Short name T386
Test name
Test status
Simulation time 27206905100 ps
CPU time 1787.35 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 02:21:45 PM PST 24
Peak memory 281848 kb
Host smart-a7b9a757-9bfc-4900-ba53-15d85be799b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905764635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.905764635
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1465608290
Short name T58
Test name
Test status
Simulation time 56725504510 ps
CPU time 1506.08 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 02:17:06 PM PST 24
Peak memory 289880 kb
Host smart-a3787555-dd0f-43fa-9b10-7b70a96b0514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465608290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1465608290
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.667103065
Short name T464
Test name
Test status
Simulation time 297670337 ps
CPU time 26.38 seconds
Started Mar 07 01:52:00 PM PST 24
Finished Mar 07 01:52:28 PM PST 24
Peak memory 255472 kb
Host smart-538fbf45-6bed-428a-811e-60d6df0e9611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66710
3065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.667103065
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1089286263
Short name T516
Test name
Test status
Simulation time 147059580 ps
CPU time 12.88 seconds
Started Mar 07 01:51:57 PM PST 24
Finished Mar 07 01:52:10 PM PST 24
Peak memory 255816 kb
Host smart-cc01b86d-b544-44ca-8096-d4761f6d3534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10892
86263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1089286263
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3120588754
Short name T669
Test name
Test status
Simulation time 55619960162 ps
CPU time 1107.81 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 02:10:30 PM PST 24
Peak memory 270600 kb
Host smart-5d8ff2f8-4484-4b55-b2b3-2b79f7994cab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120588754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3120588754
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1952700676
Short name T559
Test name
Test status
Simulation time 100891810620 ps
CPU time 1480.17 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 02:16:49 PM PST 24
Peak memory 273660 kb
Host smart-f2bada1f-4fd2-4f30-b07d-1d743738a286
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952700676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1952700676
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.592111371
Short name T666
Test name
Test status
Simulation time 51575771460 ps
CPU time 541.55 seconds
Started Mar 07 01:51:59 PM PST 24
Finished Mar 07 02:01:01 PM PST 24
Peak memory 247680 kb
Host smart-7dd2b3b2-a083-4dc9-b6e9-8cf0054bf78e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592111371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.592111371
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2044368807
Short name T57
Test name
Test status
Simulation time 301175176 ps
CPU time 10.3 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:12 PM PST 24
Peak memory 249000 kb
Host smart-e16cb29a-d045-47f2-9868-18f76282872c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
68807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2044368807
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1296631087
Short name T389
Test name
Test status
Simulation time 1319278289 ps
CPU time 40.92 seconds
Started Mar 07 01:51:56 PM PST 24
Finished Mar 07 01:52:37 PM PST 24
Peak memory 255512 kb
Host smart-83eeb61c-940a-49ba-b001-d506bfeda4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12966
31087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1296631087
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2215432038
Short name T361
Test name
Test status
Simulation time 718979611 ps
CPU time 12.55 seconds
Started Mar 07 01:52:02 PM PST 24
Finished Mar 07 01:52:15 PM PST 24
Peak memory 254144 kb
Host smart-cd5e9cbe-c5e8-48f2-9574-1b23ac299a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22154
32038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2215432038
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2363616686
Short name T697
Test name
Test status
Simulation time 54161307 ps
CPU time 4.66 seconds
Started Mar 07 01:52:01 PM PST 24
Finished Mar 07 01:52:07 PM PST 24
Peak memory 240812 kb
Host smart-3a2f94f1-397a-4f2b-b759-6385fd4fabf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23636
16686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2363616686
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.4218256787
Short name T75
Test name
Test status
Simulation time 11394489655 ps
CPU time 1490.19 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 02:16:57 PM PST 24
Peak memory 289504 kb
Host smart-c622c58b-4532-4ad6-b905-ad8be9e45373
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218256787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.4218256787
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1843463207
Short name T281
Test name
Test status
Simulation time 12572345867 ps
CPU time 1383.36 seconds
Started Mar 07 01:52:09 PM PST 24
Finished Mar 07 02:15:13 PM PST 24
Peak memory 289544 kb
Host smart-7c4a7b5d-c825-43e5-9ed5-8d0dfbbb5374
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843463207 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1843463207
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.681496730
Short name T54
Test name
Test status
Simulation time 44559840846 ps
CPU time 1467.64 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 02:16:37 PM PST 24
Peak memory 273712 kb
Host smart-c31a918d-2dfb-4240-9dba-ca8255272791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681496730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.681496730
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.723882738
Short name T380
Test name
Test status
Simulation time 1137394151 ps
CPU time 106.32 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:53:55 PM PST 24
Peak memory 256464 kb
Host smart-c7e096c6-4829-4226-b718-238ec59775f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72388
2738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.723882738
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3257085570
Short name T193
Test name
Test status
Simulation time 244526552 ps
CPU time 19.87 seconds
Started Mar 07 01:52:15 PM PST 24
Finished Mar 07 01:52:36 PM PST 24
Peak memory 255472 kb
Host smart-beb6a910-aa9f-40de-9192-a2815b8e3060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
85570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3257085570
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.159452677
Short name T329
Test name
Test status
Simulation time 12228665690 ps
CPU time 1011.1 seconds
Started Mar 07 01:52:09 PM PST 24
Finished Mar 07 02:09:00 PM PST 24
Peak memory 271140 kb
Host smart-25d4d232-73f1-4082-8f8e-ea6033bd0c89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159452677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.159452677
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.818038987
Short name T653
Test name
Test status
Simulation time 183215550080 ps
CPU time 2918.07 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 02:40:45 PM PST 24
Peak memory 287196 kb
Host smart-3e3fd87d-15f9-4fc5-8ab6-86a5b8f7119f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818038987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.818038987
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3322011042
Short name T625
Test name
Test status
Simulation time 2556259386 ps
CPU time 108.72 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:53:58 PM PST 24
Peak memory 247948 kb
Host smart-5708ad66-f811-4322-bf0e-a10514ae7601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322011042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3322011042
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3067571197
Short name T482
Test name
Test status
Simulation time 485574962 ps
CPU time 19.52 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:52:29 PM PST 24
Peak memory 249124 kb
Host smart-1d8970b8-2575-4576-b81c-662324df9022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30675
71197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3067571197
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3284706192
Short name T360
Test name
Test status
Simulation time 448428566 ps
CPU time 9.52 seconds
Started Mar 07 01:52:06 PM PST 24
Finished Mar 07 01:52:16 PM PST 24
Peak memory 247288 kb
Host smart-3bc76119-d3fb-4516-bbef-8d6babc26521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32847
06192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3284706192
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.594496724
Short name T434
Test name
Test status
Simulation time 897696675 ps
CPU time 16.39 seconds
Started Mar 07 01:52:07 PM PST 24
Finished Mar 07 01:52:23 PM PST 24
Peak memory 248952 kb
Host smart-71bf7625-8c40-4365-ba7e-e10e41fc1d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59449
6724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.594496724
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1522421680
Short name T673
Test name
Test status
Simulation time 82115788 ps
CPU time 3.76 seconds
Started Mar 07 01:51:12 PM PST 24
Finished Mar 07 01:51:15 PM PST 24
Peak memory 249124 kb
Host smart-3f773be9-b7db-4cd7-b17f-14f54917b8cd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1522421680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1522421680
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2070867285
Short name T601
Test name
Test status
Simulation time 178107510939 ps
CPU time 2256.58 seconds
Started Mar 07 01:51:05 PM PST 24
Finished Mar 07 02:28:42 PM PST 24
Peak memory 284516 kb
Host smart-683bf24b-b9e7-45ab-acf0-d37a83fe9363
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070867285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2070867285
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3175659729
Short name T406
Test name
Test status
Simulation time 1511325975 ps
CPU time 33.58 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 01:51:41 PM PST 24
Peak memory 240864 kb
Host smart-aeacc203-e013-4273-9340-0c3ba49326a0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3175659729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3175659729
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3600694372
Short name T655
Test name
Test status
Simulation time 1190544234 ps
CPU time 64.9 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:52:21 PM PST 24
Peak memory 256480 kb
Host smart-7e4ce8e8-78bc-42c9-ac3a-cb28dfe5d389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36006
94372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3600694372
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.169118750
Short name T191
Test name
Test status
Simulation time 344975783 ps
CPU time 20.72 seconds
Started Mar 07 01:51:06 PM PST 24
Finished Mar 07 01:51:28 PM PST 24
Peak memory 255292 kb
Host smart-6a6c3b96-aba6-4494-9683-181b27247f1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16911
8750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.169118750
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2909185945
Short name T89
Test name
Test status
Simulation time 55774708013 ps
CPU time 1173.32 seconds
Started Mar 07 01:51:12 PM PST 24
Finished Mar 07 02:10:45 PM PST 24
Peak memory 270452 kb
Host smart-40871a91-5c22-42dc-b846-93493ec92b4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909185945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2909185945
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.995767092
Short name T549
Test name
Test status
Simulation time 103242326286 ps
CPU time 2857.74 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 02:38:54 PM PST 24
Peak memory 281836 kb
Host smart-4ac811ff-e214-4241-b136-a48c17cc7e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995767092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.995767092
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3250882629
Short name T313
Test name
Test status
Simulation time 15517324509 ps
CPU time 321.75 seconds
Started Mar 07 01:51:10 PM PST 24
Finished Mar 07 01:56:32 PM PST 24
Peak memory 246932 kb
Host smart-bec975d8-f7a0-4f93-8600-95278a2ef9ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250882629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3250882629
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.41515661
Short name T696
Test name
Test status
Simulation time 1090861624 ps
CPU time 38.14 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 256024 kb
Host smart-9dc3b977-4c68-4da2-82e2-12759b429097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41515
661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.41515661
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3501357926
Short name T397
Test name
Test status
Simulation time 532175143 ps
CPU time 20.64 seconds
Started Mar 07 01:51:12 PM PST 24
Finished Mar 07 01:51:33 PM PST 24
Peak memory 254900 kb
Host smart-87c24649-df02-404f-9199-5cdf9da86b7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35013
57926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3501357926
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3786897692
Short name T36
Test name
Test status
Simulation time 7830529710 ps
CPU time 23.31 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 01:51:33 PM PST 24
Peak memory 270012 kb
Host smart-67dbc427-faad-474b-ae45-7377bec79a76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3786897692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3786897692
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.596334200
Short name T635
Test name
Test status
Simulation time 59590762 ps
CPU time 3.99 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:51:19 PM PST 24
Peak memory 250728 kb
Host smart-939e021c-4605-4dcf-a4f2-8b8dcd2d5ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59633
4200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.596334200
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2877401778
Short name T522
Test name
Test status
Simulation time 627738753 ps
CPU time 37.62 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 01:51:47 PM PST 24
Peak memory 256084 kb
Host smart-f50ae40f-f0f6-4477-953e-247000291146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28774
01778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2877401778
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3757793038
Short name T189
Test name
Test status
Simulation time 162328239734 ps
CPU time 2578.84 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 02:35:16 PM PST 24
Peak memory 289868 kb
Host smart-653bdffb-0763-46f4-b374-d1ef8492e0a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757793038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3757793038
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.979291759
Short name T200
Test name
Test status
Simulation time 2037010666 ps
CPU time 164.92 seconds
Started Mar 07 01:52:09 PM PST 24
Finished Mar 07 01:54:55 PM PST 24
Peak memory 256476 kb
Host smart-e4fdb15b-3f07-43bb-a4a2-df0421e5d800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97929
1759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.979291759
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1412451335
Short name T523
Test name
Test status
Simulation time 1261407178 ps
CPU time 36.19 seconds
Started Mar 07 01:52:10 PM PST 24
Finished Mar 07 01:52:46 PM PST 24
Peak memory 248524 kb
Host smart-f6b72792-22ed-4067-9255-afb22be2a956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14124
51335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1412451335
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.2796503514
Short name T536
Test name
Test status
Simulation time 90652909885 ps
CPU time 2657.77 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 02:36:35 PM PST 24
Peak memory 289348 kb
Host smart-72322772-2c3b-47e7-a1aa-ef46bf60edcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796503514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.2796503514
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.779088978
Short name T124
Test name
Test status
Simulation time 176763257042 ps
CPU time 2240.25 seconds
Started Mar 07 01:52:22 PM PST 24
Finished Mar 07 02:29:43 PM PST 24
Peak memory 289244 kb
Host smart-59a3ec9f-59a1-4522-8078-4a682cc48823
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779088978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.779088978
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1357078210
Short name T677
Test name
Test status
Simulation time 35565030646 ps
CPU time 374.27 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 01:58:32 PM PST 24
Peak memory 248988 kb
Host smart-a486a7d5-9b5b-4a60-9728-2694557b7f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357078210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1357078210
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3287973877
Short name T431
Test name
Test status
Simulation time 698549075 ps
CPU time 11.95 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:52:21 PM PST 24
Peak memory 249008 kb
Host smart-cf1703f1-bb89-4f93-aaf0-7aa802b1a3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
73877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3287973877
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.178432429
Short name T97
Test name
Test status
Simulation time 303618598 ps
CPU time 23.68 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:52:33 PM PST 24
Peak memory 247408 kb
Host smart-c700fb47-fea6-4d6c-a078-b1ca7b88231c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17843
2429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.178432429
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.617485297
Short name T461
Test name
Test status
Simulation time 200739738 ps
CPU time 3 seconds
Started Mar 07 01:52:08 PM PST 24
Finished Mar 07 01:52:12 PM PST 24
Peak memory 238768 kb
Host smart-f0ed486b-388b-4cc8-8174-436e5ffa9ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61748
5297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.617485297
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.1263428477
Short name T233
Test name
Test status
Simulation time 763891039 ps
CPU time 44.11 seconds
Started Mar 07 01:52:07 PM PST 24
Finished Mar 07 01:52:51 PM PST 24
Peak memory 249016 kb
Host smart-f819a8a0-325c-4c7a-816a-5298e82a11e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12634
28477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.1263428477
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1498449084
Short name T506
Test name
Test status
Simulation time 73723990248 ps
CPU time 1011.85 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 02:09:09 PM PST 24
Peak memory 285784 kb
Host smart-b9e8c6d9-665e-4eb0-9c08-0fd0e31a12d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498449084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1498449084
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3741091931
Short name T560
Test name
Test status
Simulation time 14011941686 ps
CPU time 1601.46 seconds
Started Mar 07 01:52:21 PM PST 24
Finished Mar 07 02:19:03 PM PST 24
Peak memory 289848 kb
Host smart-4218c404-b8bd-4c9a-ae7b-38e63dd550b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741091931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3741091931
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.935897856
Short name T504
Test name
Test status
Simulation time 3091827993 ps
CPU time 40.71 seconds
Started Mar 07 01:52:18 PM PST 24
Finished Mar 07 01:52:58 PM PST 24
Peak memory 254840 kb
Host smart-07a146b5-1289-47e7-bae8-322502ad6229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93589
7856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.935897856
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.482659507
Short name T483
Test name
Test status
Simulation time 333432358 ps
CPU time 24.19 seconds
Started Mar 07 01:52:20 PM PST 24
Finished Mar 07 01:52:44 PM PST 24
Peak memory 254712 kb
Host smart-208215ba-8cd2-4a2d-bc1e-fae035ab5ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48265
9507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.482659507
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3838956888
Short name T315
Test name
Test status
Simulation time 54395379845 ps
CPU time 2832.07 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 02:39:29 PM PST 24
Peak memory 281808 kb
Host smart-2b231b81-8dbd-4e61-9622-a7507c62f7a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838956888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3838956888
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.4021627357
Short name T587
Test name
Test status
Simulation time 161440076307 ps
CPU time 3544.52 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 02:51:22 PM PST 24
Peak memory 289220 kb
Host smart-ce9277a2-2d2b-435b-b61d-15794f348183
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021627357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4021627357
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.4258121006
Short name T309
Test name
Test status
Simulation time 17426410180 ps
CPU time 715.51 seconds
Started Mar 07 01:52:18 PM PST 24
Finished Mar 07 02:04:13 PM PST 24
Peak memory 247676 kb
Host smart-f41d4985-4318-4e8f-b97f-3923d98d2da0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258121006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.4258121006
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3079198596
Short name T390
Test name
Test status
Simulation time 477014551 ps
CPU time 30.39 seconds
Started Mar 07 01:52:18 PM PST 24
Finished Mar 07 01:52:48 PM PST 24
Peak memory 249024 kb
Host smart-bde0a248-3702-4f4f-ab34-8df7227220fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30791
98596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3079198596
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2471888226
Short name T242
Test name
Test status
Simulation time 1814112272 ps
CPU time 31.21 seconds
Started Mar 07 01:52:19 PM PST 24
Finished Mar 07 01:52:50 PM PST 24
Peak memory 255464 kb
Host smart-b429efda-0338-4c10-827e-dfb9af985c11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24718
88226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2471888226
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3867021621
Short name T567
Test name
Test status
Simulation time 169897048 ps
CPU time 23.67 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 01:52:40 PM PST 24
Peak memory 254596 kb
Host smart-ba08c7b4-64f2-48c8-a797-221ecd7e7b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38670
21621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3867021621
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3000083288
Short name T524
Test name
Test status
Simulation time 363445222 ps
CPU time 46.93 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 01:53:04 PM PST 24
Peak memory 249060 kb
Host smart-68127dd9-d0bb-48e6-8b49-6c367088717b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
83288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3000083288
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2116669418
Short name T624
Test name
Test status
Simulation time 4148655107 ps
CPU time 55.59 seconds
Started Mar 07 01:52:18 PM PST 24
Finished Mar 07 01:53:13 PM PST 24
Peak memory 256264 kb
Host smart-20f44a19-446b-4b3c-9efa-0e2effcf3660
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116669418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2116669418
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3094863291
Short name T102
Test name
Test status
Simulation time 75394093053 ps
CPU time 2283.56 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 02:30:20 PM PST 24
Peak memory 273436 kb
Host smart-e55a292d-8713-4853-a5ac-3c96132b2834
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094863291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3094863291
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2945909523
Short name T350
Test name
Test status
Simulation time 9021817442 ps
CPU time 296.99 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 01:57:14 PM PST 24
Peak memory 256760 kb
Host smart-3eef33d5-cbde-4882-ba3e-523d1c46a8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29459
09523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2945909523
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2108193123
Short name T114
Test name
Test status
Simulation time 5237376746 ps
CPU time 75.2 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 01:53:32 PM PST 24
Peak memory 256564 kb
Host smart-b9771d35-2e7a-4f77-bc2b-a2f353d94d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21081
93123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2108193123
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1004875982
Short name T326
Test name
Test status
Simulation time 11231073009 ps
CPU time 1144.29 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 02:11:22 PM PST 24
Peak memory 273840 kb
Host smart-0aeee04e-61d4-4adf-8f37-0de8bbb82678
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004875982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1004875982
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2695802027
Short name T420
Test name
Test status
Simulation time 27658863672 ps
CPU time 1744.87 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 02:21:22 PM PST 24
Peak memory 272768 kb
Host smart-66505546-ef7b-4c90-8770-2c0fa7e1bf26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695802027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2695802027
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3469934302
Short name T540
Test name
Test status
Simulation time 8392418452 ps
CPU time 342.12 seconds
Started Mar 07 01:52:19 PM PST 24
Finished Mar 07 01:58:02 PM PST 24
Peak memory 247952 kb
Host smart-314f4469-f262-4b25-958f-7e264cfb2260
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469934302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3469934302
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3569557818
Short name T448
Test name
Test status
Simulation time 643016125 ps
CPU time 16.44 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 01:52:33 PM PST 24
Peak memory 254736 kb
Host smart-e610344e-8103-454b-9e03-6e3b0f60cac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35695
57818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3569557818
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4053097279
Short name T450
Test name
Test status
Simulation time 78490989 ps
CPU time 5.48 seconds
Started Mar 07 01:52:16 PM PST 24
Finished Mar 07 01:52:22 PM PST 24
Peak memory 238904 kb
Host smart-ab52998d-f913-4ebc-8359-f3c55feef06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
97279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4053097279
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.3485740693
Short name T620
Test name
Test status
Simulation time 710512879 ps
CPU time 26.19 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 01:52:43 PM PST 24
Peak memory 254632 kb
Host smart-22602b17-4da5-45e0-b8f6-cba422c4a90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34857
40693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.3485740693
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1564346806
Short name T8
Test name
Test status
Simulation time 417379879 ps
CPU time 9.7 seconds
Started Mar 07 01:52:17 PM PST 24
Finished Mar 07 01:52:27 PM PST 24
Peak memory 248904 kb
Host smart-e62ad205-9628-4684-86c2-b7039e23fd5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15643
46806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1564346806
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3540324323
Short name T105
Test name
Test status
Simulation time 68350707211 ps
CPU time 1650.73 seconds
Started Mar 07 01:52:19 PM PST 24
Finished Mar 07 02:19:50 PM PST 24
Peak memory 281824 kb
Host smart-5f1166d2-4f99-436a-9dd8-5b1188b5b9d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540324323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3540324323
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.3472403468
Short name T47
Test name
Test status
Simulation time 6340450263 ps
CPU time 118.66 seconds
Started Mar 07 01:52:24 PM PST 24
Finished Mar 07 01:54:23 PM PST 24
Peak memory 256708 kb
Host smart-4d0891ff-0efd-4d35-bca0-c1babd57f50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34724
03468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.3472403468
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.535897230
Short name T491
Test name
Test status
Simulation time 1014936168 ps
CPU time 20.34 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:52:47 PM PST 24
Peak memory 255132 kb
Host smart-50572faa-9c99-42f8-b19a-7c67c2d68154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53589
7230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.535897230
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2785991319
Short name T322
Test name
Test status
Simulation time 79353919605 ps
CPU time 1449.5 seconds
Started Mar 07 01:52:35 PM PST 24
Finished Mar 07 02:16:45 PM PST 24
Peak memory 273100 kb
Host smart-d91b6af4-3129-4063-9e78-96ba22a9bc49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785991319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2785991319
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2659795290
Short name T688
Test name
Test status
Simulation time 128379182212 ps
CPU time 2135.36 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 02:28:01 PM PST 24
Peak memory 289436 kb
Host smart-4e3bf0eb-11ff-4842-aac5-a2ccb2014ae1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659795290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2659795290
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1104460165
Short name T297
Test name
Test status
Simulation time 31716115936 ps
CPU time 389.96 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 01:58:55 PM PST 24
Peak memory 247648 kb
Host smart-93b3010d-ccb1-4ea0-8dd9-99a81d875796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104460165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1104460165
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1361812536
Short name T520
Test name
Test status
Simulation time 3932990493 ps
CPU time 48.14 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:53:16 PM PST 24
Peak memory 256068 kb
Host smart-77635f6f-6a34-4119-bb93-7c8a8c48f4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
12536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1361812536
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3118354078
Short name T222
Test name
Test status
Simulation time 397735080 ps
CPU time 21.29 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 01:52:47 PM PST 24
Peak memory 255668 kb
Host smart-32e1ebe3-68bd-432f-8b56-03f089ccb7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31183
54078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3118354078
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.298090172
Short name T682
Test name
Test status
Simulation time 74540330 ps
CPU time 8.71 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 01:52:37 PM PST 24
Peak memory 254076 kb
Host smart-f5128144-e8cb-4b7e-930d-bb91bd6e77bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
0172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.298090172
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2930088400
Short name T615
Test name
Test status
Simulation time 159622817 ps
CPU time 20.58 seconds
Started Mar 07 01:52:18 PM PST 24
Finished Mar 07 01:52:39 PM PST 24
Peak memory 255668 kb
Host smart-675e0271-f7f9-470c-a0af-1ba51e1c26cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
88400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2930088400
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2745034295
Short name T49
Test name
Test status
Simulation time 18048046627 ps
CPU time 1206.28 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 02:12:33 PM PST 24
Peak memory 286940 kb
Host smart-0f2ceb14-8f5b-4f84-a711-1d0ca0043a9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745034295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2745034295
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2332111251
Short name T658
Test name
Test status
Simulation time 285839264431 ps
CPU time 2808.35 seconds
Started Mar 07 01:52:35 PM PST 24
Finished Mar 07 02:39:24 PM PST 24
Peak memory 289444 kb
Host smart-92bf518f-56b9-4bfc-bf21-f7d4a8c11347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332111251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2332111251
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.201961163
Short name T501
Test name
Test status
Simulation time 3294871498 ps
CPU time 192.29 seconds
Started Mar 07 01:52:24 PM PST 24
Finished Mar 07 01:55:37 PM PST 24
Peak memory 256708 kb
Host smart-a70cf2eb-dd3a-43a1-b8fd-3f7d2d807a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20196
1163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.201961163
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.902785054
Short name T39
Test name
Test status
Simulation time 87612542 ps
CPU time 7.28 seconds
Started Mar 07 01:52:23 PM PST 24
Finished Mar 07 01:52:31 PM PST 24
Peak memory 240552 kb
Host smart-bc5a51af-6600-4a25-8cff-b48642293816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90278
5054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.902785054
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.435740985
Short name T323
Test name
Test status
Simulation time 31219458222 ps
CPU time 762.42 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 02:05:11 PM PST 24
Peak memory 265452 kb
Host smart-116893fa-0108-43fa-9bc7-cf4a186ec3b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435740985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.435740985
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.909087786
Short name T661
Test name
Test status
Simulation time 64837916519 ps
CPU time 1759.94 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 02:21:48 PM PST 24
Peak memory 273632 kb
Host smart-3a7a15ca-9374-4c8a-bd15-560525d0ad40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909087786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.909087786
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3522765521
Short name T295
Test name
Test status
Simulation time 11317706729 ps
CPU time 479.95 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 02:00:26 PM PST 24
Peak memory 247672 kb
Host smart-056f8e0e-2275-4ca5-8e50-8e6393747867
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522765521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3522765521
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1859127463
Short name T597
Test name
Test status
Simulation time 366988799 ps
CPU time 23.52 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 01:52:50 PM PST 24
Peak memory 254680 kb
Host smart-faed1b2a-a72c-4439-8afd-e2c7da6ad19d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
27463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1859127463
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.50314205
Short name T428
Test name
Test status
Simulation time 82620620 ps
CPU time 3.7 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:52:31 PM PST 24
Peak memory 239048 kb
Host smart-d9322d98-abaa-49f3-b6f2-74861ec7ac09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50314
205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.50314205
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1174055141
Short name T529
Test name
Test status
Simulation time 595958863 ps
CPU time 38.24 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:53:06 PM PST 24
Peak memory 247440 kb
Host smart-4be0d385-ed5c-45e3-9a48-01d0a8c5ff81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11740
55141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1174055141
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.4250666682
Short name T527
Test name
Test status
Simulation time 1752792348 ps
CPU time 56.8 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 01:53:23 PM PST 24
Peak memory 249132 kb
Host smart-264e3b4d-931f-468b-92dc-475c39397466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42506
66682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.4250666682
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.854673834
Short name T577
Test name
Test status
Simulation time 51640868734 ps
CPU time 3142.08 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 02:44:48 PM PST 24
Peak memory 289124 kb
Host smart-58dc035e-0580-4984-8ae2-79ddaf96d67a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854673834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.854673834
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.4049532095
Short name T561
Test name
Test status
Simulation time 69630676335 ps
CPU time 2178.7 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 02:28:44 PM PST 24
Peak memory 289784 kb
Host smart-f40c54da-0829-4333-b32f-ea0a566112eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049532095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.4049532095
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2925362001
Short name T581
Test name
Test status
Simulation time 1551933832 ps
CPU time 89.29 seconds
Started Mar 07 01:52:29 PM PST 24
Finished Mar 07 01:53:59 PM PST 24
Peak memory 248440 kb
Host smart-0d523c31-2485-444f-92b3-5e4b7f28d13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29253
62001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2925362001
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3476965700
Short name T668
Test name
Test status
Simulation time 1016031216 ps
CPU time 51.81 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:53:19 PM PST 24
Peak memory 255880 kb
Host smart-ddc727c9-0a9c-4328-8123-391117029a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34769
65700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3476965700
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3600863259
Short name T433
Test name
Test status
Simulation time 8048301111 ps
CPU time 705.57 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 02:04:13 PM PST 24
Peak memory 272768 kb
Host smart-3dc76721-87f3-4151-b0d4-5c23cbb76124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600863259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3600863259
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3290874227
Short name T106
Test name
Test status
Simulation time 14011250601 ps
CPU time 1306.35 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 02:14:15 PM PST 24
Peak memory 282668 kb
Host smart-2dad5bf7-aa77-4a77-ac66-02896af17cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290874227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3290874227
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4170327777
Short name T293
Test name
Test status
Simulation time 22828796055 ps
CPU time 249.87 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 01:56:38 PM PST 24
Peak memory 247940 kb
Host smart-962b8c00-3bbf-4481-9dfe-e98ac7ef531d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170327777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4170327777
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.430655586
Short name T30
Test name
Test status
Simulation time 616836341 ps
CPU time 22.24 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 01:52:48 PM PST 24
Peak memory 257076 kb
Host smart-94da587b-af45-4c49-a7c5-f80985d05898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43065
5586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.430655586
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2520439347
Short name T526
Test name
Test status
Simulation time 865377658 ps
CPU time 46.73 seconds
Started Mar 07 01:52:29 PM PST 24
Finished Mar 07 01:53:16 PM PST 24
Peak memory 255640 kb
Host smart-ccc67230-6191-4378-9686-e8f16e6efd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25204
39347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2520439347
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4139723920
Short name T632
Test name
Test status
Simulation time 2057629373 ps
CPU time 38.16 seconds
Started Mar 07 01:52:29 PM PST 24
Finished Mar 07 01:53:08 PM PST 24
Peak memory 255644 kb
Host smart-02817b04-37f4-4410-aeac-0877135b62d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41397
23920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4139723920
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3888891159
Short name T474
Test name
Test status
Simulation time 1359246802 ps
CPU time 34.01 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 01:52:59 PM PST 24
Peak memory 255516 kb
Host smart-706947d3-cbd5-4d1f-9b90-75590e981a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888
91159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3888891159
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.570420030
Short name T270
Test name
Test status
Simulation time 30051171452 ps
CPU time 1798.12 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 02:22:24 PM PST 24
Peak memory 284664 kb
Host smart-7c5c847a-01d4-426d-bbd0-c2704ccb4eec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570420030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.570420030
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3329249026
Short name T241
Test name
Test status
Simulation time 37028344646 ps
CPU time 2260.19 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 02:30:07 PM PST 24
Peak memory 289032 kb
Host smart-598a6a94-cf80-46a9-8a2d-2f79a5cc25bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329249026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3329249026
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3036461798
Short name T48
Test name
Test status
Simulation time 869605316 ps
CPU time 73.45 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 01:53:42 PM PST 24
Peak memory 256636 kb
Host smart-97bb8754-612f-4075-9d71-aba8f1184a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30364
61798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3036461798
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2237217967
Short name T578
Test name
Test status
Simulation time 3746194652 ps
CPU time 38.96 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 01:53:05 PM PST 24
Peak memory 255484 kb
Host smart-55400244-3acc-4450-ba92-31b1ca096e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
17967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2237217967
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3989019545
Short name T319
Test name
Test status
Simulation time 29723259555 ps
CPU time 1814.62 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 02:22:42 PM PST 24
Peak memory 273280 kb
Host smart-1d9e1d22-1654-45ca-8466-acabb09a7ef7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989019545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3989019545
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.449987628
Short name T500
Test name
Test status
Simulation time 101772969107 ps
CPU time 1225.66 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 02:12:54 PM PST 24
Peak memory 286060 kb
Host smart-7740de0d-24d0-4f76-b7eb-ebba38aa8a0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449987628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.449987628
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3023293274
Short name T621
Test name
Test status
Simulation time 855096998 ps
CPU time 33.17 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 01:53:02 PM PST 24
Peak memory 249068 kb
Host smart-07eb6d10-4be5-48ff-b464-b833253ff3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30232
93274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3023293274
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3630380778
Short name T593
Test name
Test status
Simulation time 1448365683 ps
CPU time 25.88 seconds
Started Mar 07 01:52:25 PM PST 24
Finished Mar 07 01:52:51 PM PST 24
Peak memory 254824 kb
Host smart-9010ea88-a9f0-410e-89f7-f69c1c6041c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36303
80778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3630380778
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3360875036
Short name T375
Test name
Test status
Simulation time 97885619 ps
CPU time 11.41 seconds
Started Mar 07 01:52:27 PM PST 24
Finished Mar 07 01:52:39 PM PST 24
Peak memory 248980 kb
Host smart-40ed2819-2550-4c5e-8eb4-b3b28626d472
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33608
75036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3360875036
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1608247597
Short name T364
Test name
Test status
Simulation time 196588535 ps
CPU time 12.06 seconds
Started Mar 07 01:52:36 PM PST 24
Finished Mar 07 01:52:48 PM PST 24
Peak memory 249000 kb
Host smart-b0270d1b-488d-4278-80a4-ebeefe12cafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16082
47597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1608247597
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3097305454
Short name T629
Test name
Test status
Simulation time 9905449588 ps
CPU time 726.54 seconds
Started Mar 07 01:52:36 PM PST 24
Finished Mar 07 02:04:43 PM PST 24
Peak memory 265484 kb
Host smart-cdd8c163-3f7d-413d-8000-a2e837436243
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097305454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3097305454
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.209407368
Short name T525
Test name
Test status
Simulation time 3433287020 ps
CPU time 63.46 seconds
Started Mar 07 01:52:36 PM PST 24
Finished Mar 07 01:53:39 PM PST 24
Peak memory 256396 kb
Host smart-e5335972-be6f-4570-8910-c3fae3959c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20940
7368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.209407368
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.304789016
Short name T481
Test name
Test status
Simulation time 227906123 ps
CPU time 9.76 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:52:48 PM PST 24
Peak memory 250624 kb
Host smart-0035c67b-3a3d-4113-8c6e-3c478647c5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30478
9016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.304789016
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2054730552
Short name T262
Test name
Test status
Simulation time 27895235559 ps
CPU time 1186.35 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 02:12:25 PM PST 24
Peak memory 265520 kb
Host smart-11953c2e-ff6b-4de6-a610-844f2de0cfe1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054730552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2054730552
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3271705302
Short name T348
Test name
Test status
Simulation time 88559229697 ps
CPU time 1316.24 seconds
Started Mar 07 01:52:36 PM PST 24
Finished Mar 07 02:14:33 PM PST 24
Peak memory 265460 kb
Host smart-2cf0ae74-51b5-4990-95ba-1a8200b83fc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271705302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3271705302
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2077316938
Short name T659
Test name
Test status
Simulation time 12053765415 ps
CPU time 267.76 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:57:06 PM PST 24
Peak memory 247620 kb
Host smart-d5f0172c-f364-4f89-b217-4ccf4ea910d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077316938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2077316938
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3451619725
Short name T544
Test name
Test status
Simulation time 958303345 ps
CPU time 56.22 seconds
Started Mar 07 01:52:26 PM PST 24
Finished Mar 07 01:53:23 PM PST 24
Peak memory 248908 kb
Host smart-b9572cd9-b02b-4731-80cc-a4db8f2e8ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
19725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3451619725
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3963700776
Short name T445
Test name
Test status
Simulation time 2512121051 ps
CPU time 35.71 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 01:53:16 PM PST 24
Peak memory 255104 kb
Host smart-2d5e594c-b083-4dfe-b74b-e20dc4da0b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39637
00776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3963700776
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.217439663
Short name T249
Test name
Test status
Simulation time 3426172264 ps
CPU time 18.19 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 01:52:58 PM PST 24
Peak memory 247480 kb
Host smart-0f975f6e-5eec-427a-863f-98829ee6e69d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21743
9663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.217439663
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.283142428
Short name T410
Test name
Test status
Simulation time 3053043595 ps
CPU time 46.67 seconds
Started Mar 07 01:52:28 PM PST 24
Finished Mar 07 01:53:15 PM PST 24
Peak memory 249076 kb
Host smart-c124d827-8990-46a6-9408-d00f8068b977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
2428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.283142428
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.719124440
Short name T55
Test name
Test status
Simulation time 47986902694 ps
CPU time 1127.53 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 02:11:26 PM PST 24
Peak memory 271672 kb
Host smart-12d6b86a-b6b0-46e3-9ce0-9dc9f1d894f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719124440 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.719124440
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2974344555
Short name T528
Test name
Test status
Simulation time 38608634963 ps
CPU time 1241.1 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 02:13:21 PM PST 24
Peak memory 272260 kb
Host smart-579c64ed-0f21-4d5c-b82a-34821839e781
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974344555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2974344555
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3610935669
Short name T488
Test name
Test status
Simulation time 2492508444 ps
CPU time 70.76 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 01:53:51 PM PST 24
Peak memory 256716 kb
Host smart-8b41223c-68e4-43a4-b333-9fe90dff0a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
35669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3610935669
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.2362639994
Short name T693
Test name
Test status
Simulation time 409674876 ps
CPU time 36.6 seconds
Started Mar 07 01:52:37 PM PST 24
Finished Mar 07 01:53:14 PM PST 24
Peak memory 255280 kb
Host smart-bf165784-cfbc-405f-b55e-5b00d9f5890b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23626
39994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.2362639994
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2838378442
Short name T543
Test name
Test status
Simulation time 47289611656 ps
CPU time 956.69 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 02:08:37 PM PST 24
Peak memory 273588 kb
Host smart-a3056b97-8c0b-4fb2-be42-5981868d5822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838378442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2838378442
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1591094365
Short name T357
Test name
Test status
Simulation time 94347571604 ps
CPU time 1698.49 seconds
Started Mar 07 01:52:37 PM PST 24
Finished Mar 07 02:20:56 PM PST 24
Peak memory 272712 kb
Host smart-f5fea629-4152-4ae1-9549-5349f83d5816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591094365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1591094365
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1121627414
Short name T290
Test name
Test status
Simulation time 7581803265 ps
CPU time 307.86 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 01:57:47 PM PST 24
Peak memory 246880 kb
Host smart-0a8e76f4-cb2e-4e8d-8c9b-594d154a5dd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121627414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1121627414
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.4181459766
Short name T467
Test name
Test status
Simulation time 1265453101 ps
CPU time 17.95 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 01:52:57 PM PST 24
Peak memory 249100 kb
Host smart-9728f71e-93d8-45e1-8ee7-23635f7cef48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
59766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.4181459766
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3344740988
Short name T695
Test name
Test status
Simulation time 281484765 ps
CPU time 30.07 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:53:08 PM PST 24
Peak memory 256308 kb
Host smart-fcd038f8-47dd-4ddc-a9f0-5486aae3d85b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33447
40988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3344740988
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3496027224
Short name T457
Test name
Test status
Simulation time 700060795 ps
CPU time 30.42 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:53:08 PM PST 24
Peak memory 249012 kb
Host smart-aeb609fb-0981-43ad-9452-c82b088a3936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34960
27224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3496027224
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.973234173
Short name T255
Test name
Test status
Simulation time 9764925635 ps
CPU time 458.92 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 02:00:18 PM PST 24
Peak memory 265424 kb
Host smart-d483cb56-7dd4-4d6b-9839-8c582122de30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973234173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.973234173
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.66673493
Short name T616
Test name
Test status
Simulation time 79793957856 ps
CPU time 3182.68 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 02:45:42 PM PST 24
Peak memory 321924 kb
Host smart-1317ee7d-51f6-4e94-be75-23a8617d8988
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66673493 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.66673493
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.867847790
Short name T259
Test name
Test status
Simulation time 124406077937 ps
CPU time 2079.42 seconds
Started Mar 07 01:52:43 PM PST 24
Finished Mar 07 02:27:23 PM PST 24
Peak memory 284852 kb
Host smart-5c2838d5-3c54-45a5-9692-d0030250bc92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867847790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.867847790
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1933358613
Short name T356
Test name
Test status
Simulation time 4913457371 ps
CPU time 99.77 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:54:19 PM PST 24
Peak memory 256844 kb
Host smart-f9be04a8-0c32-48a2-bfd2-afdccefff0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19333
58613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1933358613
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3290857127
Short name T591
Test name
Test status
Simulation time 3337898257 ps
CPU time 21.8 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 01:53:01 PM PST 24
Peak memory 255452 kb
Host smart-45071558-814a-4f7b-bb35-81e32a064b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32908
57127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3290857127
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2709564693
Short name T324
Test name
Test status
Simulation time 11631603002 ps
CPU time 750.39 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 02:05:11 PM PST 24
Peak memory 273400 kb
Host smart-1994cc8d-d216-4719-8dea-585d2136bf2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709564693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2709564693
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1730463116
Short name T96
Test name
Test status
Simulation time 125712662414 ps
CPU time 1707.82 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 02:21:07 PM PST 24
Peak memory 273584 kb
Host smart-9235ce52-2488-4f86-8f46-3647b4d515a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730463116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1730463116
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2693473570
Short name T479
Test name
Test status
Simulation time 197890383 ps
CPU time 23.13 seconds
Started Mar 07 01:52:39 PM PST 24
Finished Mar 07 01:53:02 PM PST 24
Peak memory 248984 kb
Host smart-4065b3c1-0d5f-4bb9-a3ae-a0459a1f7ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26934
73570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2693473570
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4136842848
Short name T642
Test name
Test status
Simulation time 409208648 ps
CPU time 10.82 seconds
Started Mar 07 01:52:40 PM PST 24
Finished Mar 07 01:52:51 PM PST 24
Peak memory 254728 kb
Host smart-bc4bd171-c744-4cdf-8b98-73f3d336a2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41368
42848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4136842848
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.222398168
Short name T663
Test name
Test status
Simulation time 2067438594 ps
CPU time 30.8 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:53:09 PM PST 24
Peak memory 254860 kb
Host smart-349c216a-683d-4432-8548-27efe58f8cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22239
8168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.222398168
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.490778466
Short name T487
Test name
Test status
Simulation time 820666630 ps
CPU time 32.62 seconds
Started Mar 07 01:52:38 PM PST 24
Finished Mar 07 01:53:11 PM PST 24
Peak memory 249100 kb
Host smart-21d03342-2e19-45a5-99ff-9fe9d7acc3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49077
8466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.490778466
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.3194013156
Short name T88
Test name
Test status
Simulation time 6485380848 ps
CPU time 827.64 seconds
Started Mar 07 01:52:45 PM PST 24
Finished Mar 07 02:06:33 PM PST 24
Peak memory 273196 kb
Host smart-8d7a18a5-6b27-43ff-98a3-c28ff3b2ee40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194013156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.3194013156
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1427515680
Short name T211
Test name
Test status
Simulation time 137710341 ps
CPU time 3.67 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:24 PM PST 24
Peak memory 249152 kb
Host smart-70cd3f24-5fb2-46b3-ba6d-2531d00a31bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1427515680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1427515680
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2950826805
Short name T355
Test name
Test status
Simulation time 33949399719 ps
CPU time 1907.9 seconds
Started Mar 07 01:51:08 PM PST 24
Finished Mar 07 02:22:57 PM PST 24
Peak memory 289360 kb
Host smart-c9f5c0d7-06a0-49be-b7d0-faa16d45050f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950826805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2950826805
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2746661105
Short name T521
Test name
Test status
Simulation time 673349471 ps
CPU time 8.53 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:51:25 PM PST 24
Peak memory 240808 kb
Host smart-810c197f-f01a-4dbc-9fb2-40df22a6ced8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2746661105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2746661105
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1575952556
Short name T7
Test name
Test status
Simulation time 501146581 ps
CPU time 31.26 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 255876 kb
Host smart-e4f37b1e-4599-4b24-ba3a-b132abd0a2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15759
52556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1575952556
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2143700009
Short name T28
Test name
Test status
Simulation time 2419348368 ps
CPU time 35.22 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:51:44 PM PST 24
Peak memory 254860 kb
Host smart-22cf8e22-50cd-4d86-9b8c-6895b4d5a8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21437
00009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2143700009
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.1920010220
Short name T256
Test name
Test status
Simulation time 38484392637 ps
CPU time 1530.02 seconds
Started Mar 07 01:51:13 PM PST 24
Finished Mar 07 02:16:43 PM PST 24
Peak memory 273604 kb
Host smart-2173a9ae-5d5a-43a9-ae7f-578e625b570c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920010220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.1920010220
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.178467206
Short name T372
Test name
Test status
Simulation time 87055989441 ps
CPU time 2950.8 seconds
Started Mar 07 01:51:09 PM PST 24
Finished Mar 07 02:40:20 PM PST 24
Peak memory 289208 kb
Host smart-cc0d1e1d-4bdc-4548-8cdd-2c52539f6195
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178467206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.178467206
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4287839039
Short name T303
Test name
Test status
Simulation time 21170772824 ps
CPU time 454.31 seconds
Started Mar 07 01:51:07 PM PST 24
Finished Mar 07 01:58:43 PM PST 24
Peak memory 247892 kb
Host smart-bdd8c40c-53b7-4e97-a9e4-5b9c76a0b20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287839039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4287839039
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3492707482
Short name T240
Test name
Test status
Simulation time 823277071 ps
CPU time 18.07 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 249000 kb
Host smart-200a02a6-c2a7-4791-a964-c69abea56d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34927
07482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3492707482
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2229377323
Short name T359
Test name
Test status
Simulation time 387423384 ps
CPU time 35.67 seconds
Started Mar 07 01:51:11 PM PST 24
Finished Mar 07 01:51:47 PM PST 24
Peak memory 256636 kb
Host smart-4d7a7514-f731-43ba-8ada-e754f864f1e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22293
77323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2229377323
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.31681322
Short name T11
Test name
Test status
Simulation time 3166637838 ps
CPU time 23.82 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:45 PM PST 24
Peak memory 270480 kb
Host smart-ab83af9b-ae81-43cb-a0f8-15b54c3402ca
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=31681322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.31681322
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3763673269
Short name T279
Test name
Test status
Simulation time 2963891324 ps
CPU time 33.9 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:51:50 PM PST 24
Peak memory 255400 kb
Host smart-9ff76ba8-98c3-4266-a334-940c6604a9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37636
73269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3763673269
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.643874247
Short name T519
Test name
Test status
Simulation time 545486072 ps
CPU time 9.82 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 01:51:24 PM PST 24
Peak memory 254192 kb
Host smart-9bcec27b-9737-4ccf-8f30-bc84fe62331d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64387
4247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.643874247
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1626338726
Short name T6
Test name
Test status
Simulation time 55657361767 ps
CPU time 1302.85 seconds
Started Mar 07 01:51:27 PM PST 24
Finished Mar 07 02:13:10 PM PST 24
Peak memory 287436 kb
Host smart-d65d0de8-6e1a-4e73-835f-9d58893f974c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626338726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1626338726
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2351603092
Short name T93
Test name
Test status
Simulation time 11616563551 ps
CPU time 1353.54 seconds
Started Mar 07 01:52:46 PM PST 24
Finished Mar 07 02:15:20 PM PST 24
Peak memory 289832 kb
Host smart-48bd29b8-2d9f-4728-a18b-95e1b3b4da85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351603092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2351603092
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1120512984
Short name T239
Test name
Test status
Simulation time 15105657002 ps
CPU time 213.75 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:56:22 PM PST 24
Peak memory 256556 kb
Host smart-c6059b5d-9762-4861-a4a8-72a94620a0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11205
12984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1120512984
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1923726746
Short name T641
Test name
Test status
Simulation time 3955362859 ps
CPU time 52.65 seconds
Started Mar 07 01:52:46 PM PST 24
Finished Mar 07 01:53:38 PM PST 24
Peak memory 256596 kb
Host smart-5deae78b-6ba3-43dc-a6dd-bd3251789d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19237
26746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1923726746
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2241565437
Short name T217
Test name
Test status
Simulation time 17498944879 ps
CPU time 1299.25 seconds
Started Mar 07 01:52:49 PM PST 24
Finished Mar 07 02:14:29 PM PST 24
Peak memory 286860 kb
Host smart-8a2ecd00-4f57-4e34-893c-f22c7e76cd7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241565437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2241565437
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.695875120
Short name T414
Test name
Test status
Simulation time 14446067202 ps
CPU time 1415.05 seconds
Started Mar 07 01:52:47 PM PST 24
Finished Mar 07 02:16:22 PM PST 24
Peak memory 289492 kb
Host smart-e140c41d-d275-4b62-898f-5b7dba13fea9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695875120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.695875120
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.912341258
Short name T698
Test name
Test status
Simulation time 2833821504 ps
CPU time 119.93 seconds
Started Mar 07 01:52:46 PM PST 24
Finished Mar 07 01:54:46 PM PST 24
Peak memory 247904 kb
Host smart-c51f282a-aa25-4715-8e4c-3eb4321c57ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912341258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.912341258
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.549631489
Short name T619
Test name
Test status
Simulation time 4125829088 ps
CPU time 64.1 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:53:52 PM PST 24
Peak memory 257260 kb
Host smart-27f5ea10-1443-4675-943e-b3835e8d8f57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54963
1489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.549631489
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1033266710
Short name T64
Test name
Test status
Simulation time 1373746514 ps
CPU time 40.78 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:53:29 PM PST 24
Peak memory 255432 kb
Host smart-c2748e59-e76a-4558-8796-692e4fa87c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10332
66710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1033266710
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1774925905
Short name T580
Test name
Test status
Simulation time 184187563 ps
CPU time 18.38 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:53:07 PM PST 24
Peak memory 255612 kb
Host smart-bb14bbd6-b1c3-466a-9a93-f1d413df268e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17749
25905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1774925905
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3976898382
Short name T440
Test name
Test status
Simulation time 574333069 ps
CPU time 4.12 seconds
Started Mar 07 01:52:49 PM PST 24
Finished Mar 07 01:52:53 PM PST 24
Peak memory 240748 kb
Host smart-dd3d72b1-25f3-464e-a227-b4e2402abecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39768
98382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3976898382
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.4017881174
Short name T236
Test name
Test status
Simulation time 5116965004 ps
CPU time 51.86 seconds
Started Mar 07 01:52:47 PM PST 24
Finished Mar 07 01:53:39 PM PST 24
Peak memory 247444 kb
Host smart-d1935691-73e0-48d3-9441-ec3ae30efd55
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017881174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.4017881174
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.1352893092
Short name T16
Test name
Test status
Simulation time 65775209447 ps
CPU time 3511.74 seconds
Started Mar 07 01:52:47 PM PST 24
Finished Mar 07 02:51:19 PM PST 24
Peak memory 287668 kb
Host smart-ac1b99d2-4ee2-4349-becf-b2d577458611
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352893092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.1352893092
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2164704410
Short name T588
Test name
Test status
Simulation time 852200068 ps
CPU time 6.72 seconds
Started Mar 07 01:52:45 PM PST 24
Finished Mar 07 01:52:52 PM PST 24
Peak memory 248228 kb
Host smart-808f5a9f-5d3d-4b27-91f3-5bc1ff3e0605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21647
04410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2164704410
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3216506639
Short name T269
Test name
Test status
Simulation time 3206285564 ps
CPU time 52.83 seconds
Started Mar 07 01:52:47 PM PST 24
Finished Mar 07 01:53:40 PM PST 24
Peak memory 255560 kb
Host smart-0bcf47e6-4f54-4aab-b040-05adb5cdfd7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165
06639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3216506639
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1365704162
Short name T453
Test name
Test status
Simulation time 24049427975 ps
CPU time 1172.25 seconds
Started Mar 07 01:52:45 PM PST 24
Finished Mar 07 02:12:18 PM PST 24
Peak memory 265028 kb
Host smart-bbf744ed-ec5b-48b7-93d2-002e00a55432
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365704162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1365704162
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.391978387
Short name T652
Test name
Test status
Simulation time 7510592613 ps
CPU time 312.19 seconds
Started Mar 07 01:52:47 PM PST 24
Finished Mar 07 01:57:59 PM PST 24
Peak memory 247988 kb
Host smart-4a74276f-a33f-4755-be11-18915f345de3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391978387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.391978387
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.3710642379
Short name T381
Test name
Test status
Simulation time 365384288 ps
CPU time 8.84 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:52:57 PM PST 24
Peak memory 253516 kb
Host smart-62d42d3a-4ec1-4f42-8f5b-49f0bbe53704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37106
42379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.3710642379
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1632407014
Short name T505
Test name
Test status
Simulation time 764176863 ps
CPU time 43.91 seconds
Started Mar 07 01:52:50 PM PST 24
Finished Mar 07 01:53:34 PM PST 24
Peak memory 247520 kb
Host smart-8bd796bd-36a2-4f0e-a6fd-d2790ccdfaa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16324
07014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1632407014
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1925214131
Short name T237
Test name
Test status
Simulation time 918729804 ps
CPU time 19.43 seconds
Started Mar 07 01:52:46 PM PST 24
Finished Mar 07 01:53:05 PM PST 24
Peak memory 253792 kb
Host smart-bde12ad1-7a97-4f96-8818-be0005990cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19252
14131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1925214131
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3414779639
Short name T572
Test name
Test status
Simulation time 405107670 ps
CPU time 25.42 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:53:13 PM PST 24
Peak memory 248916 kb
Host smart-2dc18d5e-fa12-4e4d-8899-49b8dc705120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34147
79639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3414779639
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.342557397
Short name T243
Test name
Test status
Simulation time 261491697156 ps
CPU time 2084.55 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 02:27:33 PM PST 24
Peak memory 282064 kb
Host smart-7ae7af4f-cc8e-4db1-9b9b-1c1765a56987
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342557397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.342557397
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3797729308
Short name T226
Test name
Test status
Simulation time 56519226085 ps
CPU time 3797.73 seconds
Started Mar 07 01:52:45 PM PST 24
Finished Mar 07 02:56:03 PM PST 24
Peak memory 297996 kb
Host smart-498367a4-d6ca-4afd-bc52-e21dc8b14fe0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797729308 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3797729308
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.73517292
Short name T394
Test name
Test status
Simulation time 57380789433 ps
CPU time 1401.69 seconds
Started Mar 07 01:52:56 PM PST 24
Finished Mar 07 02:16:18 PM PST 24
Peak memory 289112 kb
Host smart-1e3e3793-be6c-4612-8716-5dd2bb43e3ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73517292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.73517292
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3923123988
Short name T432
Test name
Test status
Simulation time 22675211830 ps
CPU time 223.89 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:56:39 PM PST 24
Peak memory 256560 kb
Host smart-2b5f78fd-b1c3-4d9f-81e7-d6999c34df17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39231
23988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3923123988
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.715955776
Short name T551
Test name
Test status
Simulation time 1673233097 ps
CPU time 20.39 seconds
Started Mar 07 01:53:01 PM PST 24
Finished Mar 07 01:53:21 PM PST 24
Peak memory 254364 kb
Host smart-23151e6e-8549-46a7-a5da-96a835c4b502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71595
5776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.715955776
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1633126353
Short name T576
Test name
Test status
Simulation time 38902556308 ps
CPU time 2425.88 seconds
Started Mar 07 01:52:56 PM PST 24
Finished Mar 07 02:33:23 PM PST 24
Peak memory 273220 kb
Host smart-c6499605-bcc4-4079-9cfa-6af9399ca6de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633126353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1633126353
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4081730797
Short name T100
Test name
Test status
Simulation time 195877851482 ps
CPU time 2863.25 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 02:40:39 PM PST 24
Peak memory 289472 kb
Host smart-07209cd1-74c1-46a1-8f71-d0275ab65d27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081730797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4081730797
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2731057772
Short name T460
Test name
Test status
Simulation time 9407743693 ps
CPU time 104.76 seconds
Started Mar 07 01:52:54 PM PST 24
Finished Mar 07 01:54:39 PM PST 24
Peak memory 247892 kb
Host smart-d4fadd9b-c193-4946-a8de-a69fd7fe5642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731057772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2731057772
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.744583275
Short name T418
Test name
Test status
Simulation time 270536090 ps
CPU time 15.8 seconds
Started Mar 07 01:52:54 PM PST 24
Finished Mar 07 01:53:10 PM PST 24
Peak memory 248904 kb
Host smart-39b40ff2-e772-439c-a277-f13b3f479236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74458
3275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.744583275
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.438438779
Short name T229
Test name
Test status
Simulation time 1681661576 ps
CPU time 43.23 seconds
Started Mar 07 01:52:54 PM PST 24
Finished Mar 07 01:53:37 PM PST 24
Peak memory 247384 kb
Host smart-090cde06-6374-4dd9-91cd-84eba33d7afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43843
8779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.438438779
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.708654610
Short name T216
Test name
Test status
Simulation time 125940738 ps
CPU time 14.22 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:53:10 PM PST 24
Peak memory 249008 kb
Host smart-3c36a136-fa0c-4ac9-afbf-abe9cc5c976d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70865
4610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.708654610
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2181360563
Short name T512
Test name
Test status
Simulation time 4942680039 ps
CPU time 31.99 seconds
Started Mar 07 01:52:48 PM PST 24
Finished Mar 07 01:53:20 PM PST 24
Peak memory 249272 kb
Host smart-4c8e4ff9-f42b-41b7-851c-2aa090e7acc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21813
60563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2181360563
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1756583404
Short name T502
Test name
Test status
Simulation time 181189809090 ps
CPU time 2093.9 seconds
Started Mar 07 01:52:53 PM PST 24
Finished Mar 07 02:27:47 PM PST 24
Peak memory 289384 kb
Host smart-4f512212-7531-4fa0-a96e-1ed0391bbe68
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756583404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1756583404
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1394948056
Short name T353
Test name
Test status
Simulation time 54761682493 ps
CPU time 2055.9 seconds
Started Mar 07 01:52:54 PM PST 24
Finished Mar 07 02:27:10 PM PST 24
Peak memory 285932 kb
Host smart-a2993771-b7fc-441c-b032-bcef6c57b448
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394948056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1394948056
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.1214845338
Short name T485
Test name
Test status
Simulation time 3429872397 ps
CPU time 179.84 seconds
Started Mar 07 01:52:59 PM PST 24
Finished Mar 07 01:55:59 PM PST 24
Peak memory 250088 kb
Host smart-a5ff723e-b83a-4eb8-adfa-58b8aecd69c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12148
45338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.1214845338
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3314613569
Short name T539
Test name
Test status
Simulation time 3424991178 ps
CPU time 47.99 seconds
Started Mar 07 01:53:00 PM PST 24
Finished Mar 07 01:53:48 PM PST 24
Peak memory 255556 kb
Host smart-cbbf3f9b-6061-42cf-a72a-97a511e44ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33146
13569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3314613569
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3564180056
Short name T571
Test name
Test status
Simulation time 36005530960 ps
CPU time 2069.72 seconds
Started Mar 07 01:52:52 PM PST 24
Finished Mar 07 02:27:22 PM PST 24
Peak memory 285608 kb
Host smart-e5d2c0ca-7dff-477d-9c5c-b441fc9b8935
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564180056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3564180056
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1205814189
Short name T398
Test name
Test status
Simulation time 114311193233 ps
CPU time 1354.26 seconds
Started Mar 07 01:52:57 PM PST 24
Finished Mar 07 02:15:32 PM PST 24
Peak memory 272396 kb
Host smart-ba6edca9-fdea-4bb0-9fba-74f21934ac7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205814189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1205814189
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3319897756
Short name T573
Test name
Test status
Simulation time 12099049979 ps
CPU time 490.18 seconds
Started Mar 07 01:52:52 PM PST 24
Finished Mar 07 02:01:03 PM PST 24
Peak memory 247836 kb
Host smart-5a262811-4895-465f-a7a7-cffb40678a28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319897756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3319897756
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2933087954
Short name T466
Test name
Test status
Simulation time 75710804 ps
CPU time 9.23 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:53:04 PM PST 24
Peak memory 249060 kb
Host smart-432145ed-738c-4583-8c7d-82ef31f755df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29330
87954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2933087954
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3538656510
Short name T415
Test name
Test status
Simulation time 254485536 ps
CPU time 35.87 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:53:31 PM PST 24
Peak memory 256392 kb
Host smart-3f132160-d072-4df8-8fc3-d0090aedcb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35386
56510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3538656510
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.693186231
Short name T227
Test name
Test status
Simulation time 1688110838 ps
CPU time 21.71 seconds
Started Mar 07 01:52:54 PM PST 24
Finished Mar 07 01:53:16 PM PST 24
Peak memory 254784 kb
Host smart-8a1c99c2-dcc3-4aa9-a779-6a18c6f24bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69318
6231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.693186231
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.960913831
Short name T657
Test name
Test status
Simulation time 3382141751 ps
CPU time 50.77 seconds
Started Mar 07 01:52:56 PM PST 24
Finished Mar 07 01:53:47 PM PST 24
Peak memory 248648 kb
Host smart-f771a98f-313a-4499-a640-c0654acd3520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96091
3831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.960913831
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1087171870
Short name T425
Test name
Test status
Simulation time 325934852932 ps
CPU time 1552.63 seconds
Started Mar 07 01:52:56 PM PST 24
Finished Mar 07 02:18:49 PM PST 24
Peak memory 288848 kb
Host smart-6f75a045-7ffd-4742-83d3-005b41653426
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087171870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1087171870
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.2268994648
Short name T369
Test name
Test status
Simulation time 150543978204 ps
CPU time 2742.54 seconds
Started Mar 07 01:53:10 PM PST 24
Finished Mar 07 02:38:52 PM PST 24
Peak memory 289972 kb
Host smart-52d8a47b-afe2-42ac-ac03-d1971a5d5d63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268994648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.2268994648
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3748482143
Short name T609
Test name
Test status
Simulation time 2426216287 ps
CPU time 50.35 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 01:53:54 PM PST 24
Peak memory 256304 kb
Host smart-cad9dbc9-1ca8-41a4-8718-daede92671d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484
82143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3748482143
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2875179752
Short name T480
Test name
Test status
Simulation time 19941954 ps
CPU time 3.51 seconds
Started Mar 07 01:52:56 PM PST 24
Finished Mar 07 01:52:59 PM PST 24
Peak memory 239048 kb
Host smart-48092fdc-f7b0-44cc-81e5-26621d4eb246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
79752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2875179752
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.4022837566
Short name T316
Test name
Test status
Simulation time 13068418489 ps
CPU time 818.54 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 02:06:43 PM PST 24
Peak memory 272944 kb
Host smart-a179ae98-5721-4963-ab74-0faf05106b14
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022837566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.4022837566
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4209197816
Short name T25
Test name
Test status
Simulation time 70906408314 ps
CPU time 897.26 seconds
Started Mar 07 01:53:10 PM PST 24
Finished Mar 07 02:08:08 PM PST 24
Peak memory 272992 kb
Host smart-80e11de8-3eba-44de-bee5-cba35b7c24c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209197816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4209197816
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.575749403
Short name T299
Test name
Test status
Simulation time 6931923398 ps
CPU time 287.41 seconds
Started Mar 07 01:53:05 PM PST 24
Finished Mar 07 01:57:53 PM PST 24
Peak memory 248840 kb
Host smart-441fe179-6300-4870-9de9-0c9877e2e2c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575749403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.575749403
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.889357452
Short name T377
Test name
Test status
Simulation time 119665906 ps
CPU time 14.8 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:53:10 PM PST 24
Peak memory 248964 kb
Host smart-79a6d49f-41bf-4134-ba2b-7f1189657699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88935
7452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.889357452
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2557782214
Short name T441
Test name
Test status
Simulation time 2203132956 ps
CPU time 37.92 seconds
Started Mar 07 01:52:55 PM PST 24
Finished Mar 07 01:53:34 PM PST 24
Peak memory 247440 kb
Host smart-0ae39161-c296-4caa-bcb1-67fc49d849c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25577
82214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2557782214
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1582414022
Short name T74
Test name
Test status
Simulation time 440015934 ps
CPU time 25.78 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 01:53:30 PM PST 24
Peak memory 255248 kb
Host smart-1ec510e4-75ff-4ffb-9431-e11063b386eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
14022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1582414022
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.2166075628
Short name T444
Test name
Test status
Simulation time 652569195 ps
CPU time 23.64 seconds
Started Mar 07 01:53:00 PM PST 24
Finished Mar 07 01:53:24 PM PST 24
Peak memory 248976 kb
Host smart-90c76449-e1fc-4001-a3a6-f459f782a167
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21660
75628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.2166075628
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4077314731
Short name T636
Test name
Test status
Simulation time 37014814407 ps
CPU time 2247.18 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 02:30:31 PM PST 24
Peak memory 273604 kb
Host smart-635db638-1690-4ca3-a3e9-f689bb5e14ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077314731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4077314731
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2415794818
Short name T403
Test name
Test status
Simulation time 30960114774 ps
CPU time 706.92 seconds
Started Mar 07 01:53:10 PM PST 24
Finished Mar 07 02:04:57 PM PST 24
Peak memory 272404 kb
Host smart-d19541f8-f50f-45c8-869f-65bf2f722da8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415794818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2415794818
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3695142348
Short name T40
Test name
Test status
Simulation time 2386496321 ps
CPU time 150.93 seconds
Started Mar 07 01:53:04 PM PST 24
Finished Mar 07 01:55:36 PM PST 24
Peak memory 256604 kb
Host smart-8b3ae4dc-10e7-400b-b413-4d5518d73f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36951
42348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3695142348
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.48066301
Short name T276
Test name
Test status
Simulation time 836584803 ps
CPU time 50.88 seconds
Started Mar 07 01:53:06 PM PST 24
Finished Mar 07 01:53:57 PM PST 24
Peak memory 255496 kb
Host smart-62b27c68-c90e-4dae-99b5-d4253300820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48066
301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.48066301
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1621988313
Short name T476
Test name
Test status
Simulation time 13272127465 ps
CPU time 953.21 seconds
Started Mar 07 01:53:05 PM PST 24
Finished Mar 07 02:08:59 PM PST 24
Peak memory 283620 kb
Host smart-c19995a3-0c8a-422e-ae29-6e81fe65163e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621988313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1621988313
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1450316380
Short name T532
Test name
Test status
Simulation time 26426854589 ps
CPU time 1690.55 seconds
Started Mar 07 01:53:13 PM PST 24
Finished Mar 07 02:21:24 PM PST 24
Peak memory 273292 kb
Host smart-7245a6ee-5e7b-4701-9216-c148779fda49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450316380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1450316380
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.705743039
Short name T300
Test name
Test status
Simulation time 13468393332 ps
CPU time 143.48 seconds
Started Mar 07 01:53:08 PM PST 24
Finished Mar 07 01:55:32 PM PST 24
Peak memory 249032 kb
Host smart-4386d30b-4e2f-4ce2-a7f8-76b10bd0b622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705743039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.705743039
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3427665998
Short name T447
Test name
Test status
Simulation time 2498257342 ps
CPU time 73.77 seconds
Started Mar 07 01:53:05 PM PST 24
Finished Mar 07 01:54:19 PM PST 24
Peak memory 256140 kb
Host smart-fe8b663b-f5db-40d6-8bad-04f860e570b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34276
65998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3427665998
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1364498929
Short name T495
Test name
Test status
Simulation time 906469239 ps
CPU time 45.37 seconds
Started Mar 07 01:53:03 PM PST 24
Finished Mar 07 01:53:48 PM PST 24
Peak memory 254512 kb
Host smart-3866406a-e760-4d0f-9d6b-70860807bc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13644
98929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1364498929
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3652795578
Short name T376
Test name
Test status
Simulation time 1595632055 ps
CPU time 21.9 seconds
Started Mar 07 01:53:10 PM PST 24
Finished Mar 07 01:53:32 PM PST 24
Peak memory 249016 kb
Host smart-f632d6dd-8587-46ed-a011-77f114f5fe3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
95578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3652795578
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3596734770
Short name T52
Test name
Test status
Simulation time 55371659571 ps
CPU time 3503.92 seconds
Started Mar 07 01:53:16 PM PST 24
Finished Mar 07 02:51:40 PM PST 24
Peak memory 306220 kb
Host smart-79fc8b6c-adde-4eb5-9bf4-8a69c479a131
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596734770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3596734770
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.676767766
Short name T277
Test name
Test status
Simulation time 920157814576 ps
CPU time 7348.87 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 03:55:44 PM PST 24
Peak memory 354996 kb
Host smart-6ae1bd48-804e-49aa-9580-8f2adc32dabd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676767766 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.676767766
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3570896223
Short name T17
Test name
Test status
Simulation time 133017685257 ps
CPU time 2005.88 seconds
Started Mar 07 01:53:16 PM PST 24
Finished Mar 07 02:26:43 PM PST 24
Peak memory 273608 kb
Host smart-b3993bbd-d1e5-4197-b707-c9eadc396ecd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570896223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3570896223
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2448089812
Short name T409
Test name
Test status
Simulation time 2821611718 ps
CPU time 59.88 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 01:54:14 PM PST 24
Peak memory 249128 kb
Host smart-469043f0-9e4c-42fd-b47f-b0d99a2a8219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24480
89812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2448089812
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.831818872
Short name T275
Test name
Test status
Simulation time 3309445889 ps
CPU time 30.62 seconds
Started Mar 07 01:53:17 PM PST 24
Finished Mar 07 01:53:48 PM PST 24
Peak memory 255512 kb
Host smart-58b8db43-ce60-4c01-89f1-8f8557ae012b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83181
8872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.831818872
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.917789253
Short name T676
Test name
Test status
Simulation time 17518147726 ps
CPU time 1717.4 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 02:21:52 PM PST 24
Peak memory 281808 kb
Host smart-b51df51b-da06-48d7-aedf-16d52b308b5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917789253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.917789253
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3446623141
Short name T122
Test name
Test status
Simulation time 88293440770 ps
CPU time 1411.28 seconds
Started Mar 07 01:53:21 PM PST 24
Finished Mar 07 02:16:52 PM PST 24
Peak memory 273064 kb
Host smart-e62bb278-8a16-4f63-be96-516eae72f39c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446623141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3446623141
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.2155055089
Short name T292
Test name
Test status
Simulation time 24421043449 ps
CPU time 516.39 seconds
Started Mar 07 01:53:16 PM PST 24
Finished Mar 07 02:01:52 PM PST 24
Peak memory 247864 kb
Host smart-f04142fe-cff0-4fc7-80d1-a2fcf25dabd7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155055089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2155055089
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1453619922
Short name T374
Test name
Test status
Simulation time 429462047 ps
CPU time 35.27 seconds
Started Mar 07 01:53:13 PM PST 24
Finished Mar 07 01:53:48 PM PST 24
Peak memory 255940 kb
Host smart-6450c33b-8120-43d3-9aeb-5bd96c800216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
19922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1453619922
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2888849967
Short name T614
Test name
Test status
Simulation time 509849446 ps
CPU time 19.09 seconds
Started Mar 07 01:53:16 PM PST 24
Finished Mar 07 01:53:35 PM PST 24
Peak memory 255196 kb
Host smart-1511ea1a-7d2c-4e3d-ae67-6ebec09a0eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28888
49967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2888849967
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3670230090
Short name T278
Test name
Test status
Simulation time 495191072 ps
CPU time 10.45 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 01:53:24 PM PST 24
Peak memory 251100 kb
Host smart-dc499ac7-d09e-4a9c-8216-950d31f14a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36702
30090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3670230090
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1377107410
Short name T201
Test name
Test status
Simulation time 487727321 ps
CPU time 12.1 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 01:53:26 PM PST 24
Peak memory 257172 kb
Host smart-b09b6fe3-b1dc-46b1-b104-725d7dcdfce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13771
07410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1377107410
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1923528448
Short name T471
Test name
Test status
Simulation time 10853056408 ps
CPU time 276.39 seconds
Started Mar 07 01:53:14 PM PST 24
Finished Mar 07 01:57:51 PM PST 24
Peak memory 257220 kb
Host smart-d29bf43d-1bd0-4dbd-87ea-510d8bf83340
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923528448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1923528448
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.2535644168
Short name T81
Test name
Test status
Simulation time 9908203850 ps
CPU time 670.37 seconds
Started Mar 07 01:53:15 PM PST 24
Finished Mar 07 02:04:25 PM PST 24
Peak memory 273664 kb
Host smart-66272a24-f223-4acf-af44-bf52566c002a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535644168 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.2535644168
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3239978603
Short name T43
Test name
Test status
Simulation time 20482053721 ps
CPU time 1478.29 seconds
Started Mar 07 01:53:25 PM PST 24
Finished Mar 07 02:18:03 PM PST 24
Peak memory 273584 kb
Host smart-f145e81a-855b-4064-8311-ea9306757411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239978603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3239978603
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.863952782
Short name T411
Test name
Test status
Simulation time 4673074084 ps
CPU time 99.32 seconds
Started Mar 07 01:53:16 PM PST 24
Finished Mar 07 01:54:55 PM PST 24
Peak memory 250028 kb
Host smart-eb1c4613-911b-461a-a283-113d96114507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86395
2782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.863952782
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.844313302
Short name T586
Test name
Test status
Simulation time 1114923795 ps
CPU time 31.98 seconds
Started Mar 07 01:53:20 PM PST 24
Finished Mar 07 01:53:53 PM PST 24
Peak memory 255308 kb
Host smart-bcf44494-305a-49d4-9da3-38cdac2ad2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84431
3302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.844313302
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2270301066
Short name T623
Test name
Test status
Simulation time 33976123178 ps
CPU time 1418.3 seconds
Started Mar 07 01:53:26 PM PST 24
Finished Mar 07 02:17:05 PM PST 24
Peak memory 286680 kb
Host smart-914bd65d-1ae6-4b05-bb7f-6bd419f5c0bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270301066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2270301066
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2992007057
Short name T35
Test name
Test status
Simulation time 190965869847 ps
CPU time 2913.23 seconds
Started Mar 07 01:53:26 PM PST 24
Finished Mar 07 02:42:00 PM PST 24
Peak memory 289416 kb
Host smart-dacfaf26-6e1d-4de6-afca-1f7c5530c35b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992007057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2992007057
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3662091556
Short name T498
Test name
Test status
Simulation time 10848743670 ps
CPU time 312.75 seconds
Started Mar 07 01:53:24 PM PST 24
Finished Mar 07 01:58:37 PM PST 24
Peak memory 247952 kb
Host smart-66650bec-b89c-40b1-bd2f-77a82cdc9be2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662091556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3662091556
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1265337032
Short name T660
Test name
Test status
Simulation time 546265134 ps
CPU time 17.07 seconds
Started Mar 07 01:53:13 PM PST 24
Finished Mar 07 01:53:30 PM PST 24
Peak memory 248988 kb
Host smart-4dbb2ef6-4f71-4a84-bc83-8a8775822838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12653
37032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1265337032
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.32682294
Short name T455
Test name
Test status
Simulation time 625413895 ps
CPU time 33.03 seconds
Started Mar 07 01:53:13 PM PST 24
Finished Mar 07 01:53:46 PM PST 24
Peak memory 255196 kb
Host smart-e9055ed6-0008-4f1f-b217-9adb9676e2e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32682
294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.32682294
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.1980203530
Short name T91
Test name
Test status
Simulation time 690853628 ps
CPU time 43.75 seconds
Started Mar 07 01:53:32 PM PST 24
Finished Mar 07 01:54:15 PM PST 24
Peak memory 255760 kb
Host smart-e9f81ea8-36f8-44dd-98bf-335cf2935cd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19802
03530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.1980203530
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3459045072
Short name T400
Test name
Test status
Simulation time 568896103 ps
CPU time 7.97 seconds
Started Mar 07 01:53:13 PM PST 24
Finished Mar 07 01:53:21 PM PST 24
Peak memory 249008 kb
Host smart-33d79971-7bd1-4413-be3d-653a12e20099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34590
45072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3459045072
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3669691259
Short name T271
Test name
Test status
Simulation time 74460340537 ps
CPU time 2491.39 seconds
Started Mar 07 01:53:23 PM PST 24
Finished Mar 07 02:34:55 PM PST 24
Peak memory 289736 kb
Host smart-030a7a02-eeda-41b9-bf6a-28d17bbe4304
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669691259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3669691259
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3168468494
Short name T630
Test name
Test status
Simulation time 55214600167 ps
CPU time 2772.98 seconds
Started Mar 07 01:53:23 PM PST 24
Finished Mar 07 02:39:37 PM PST 24
Peak memory 289252 kb
Host smart-2fe3eade-78c1-4ed8-a559-0a4310d848f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168468494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3168468494
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.3295735424
Short name T533
Test name
Test status
Simulation time 3390411160 ps
CPU time 76.56 seconds
Started Mar 07 01:53:25 PM PST 24
Finished Mar 07 01:54:42 PM PST 24
Peak memory 257232 kb
Host smart-14430cb0-c3b4-4bd8-ad86-55167de2b55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32957
35424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.3295735424
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1293004665
Short name T421
Test name
Test status
Simulation time 3371493659 ps
CPU time 51.36 seconds
Started Mar 07 01:53:24 PM PST 24
Finished Mar 07 01:54:15 PM PST 24
Peak memory 255164 kb
Host smart-75ada4d1-ee5e-4ea9-a73c-5c7f7fdaea9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
04665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1293004665
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.188007042
Short name T473
Test name
Test status
Simulation time 7779623525 ps
CPU time 609.91 seconds
Started Mar 07 01:53:26 PM PST 24
Finished Mar 07 02:03:36 PM PST 24
Peak memory 266464 kb
Host smart-9156deb5-ac10-4115-be5a-01dcdbcf7e83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188007042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.188007042
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3977657901
Short name T296
Test name
Test status
Simulation time 16942256870 ps
CPU time 504.6 seconds
Started Mar 07 01:53:25 PM PST 24
Finished Mar 07 02:01:50 PM PST 24
Peak memory 247944 kb
Host smart-d7a48eb9-2328-4043-ab60-94c7bcba17fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977657901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3977657901
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1717032566
Short name T639
Test name
Test status
Simulation time 299047083 ps
CPU time 34.01 seconds
Started Mar 07 01:53:25 PM PST 24
Finished Mar 07 01:53:59 PM PST 24
Peak memory 248976 kb
Host smart-ce2cbdfb-c638-489b-a98b-7abbe1a625a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17170
32566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1717032566
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.211658879
Short name T392
Test name
Test status
Simulation time 90393082 ps
CPU time 9.65 seconds
Started Mar 07 01:53:26 PM PST 24
Finished Mar 07 01:53:36 PM PST 24
Peak memory 252968 kb
Host smart-55a57207-94c0-492b-bd1f-13ca2cdf7ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21165
8879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.211658879
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2774277685
Short name T51
Test name
Test status
Simulation time 91740908 ps
CPU time 11.94 seconds
Started Mar 07 01:53:24 PM PST 24
Finished Mar 07 01:53:36 PM PST 24
Peak memory 247100 kb
Host smart-2a040cae-c8d1-483e-a2fb-fc8fd03ca218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27742
77685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2774277685
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2903292550
Short name T692
Test name
Test status
Simulation time 1494978843 ps
CPU time 28.61 seconds
Started Mar 07 01:53:24 PM PST 24
Finished Mar 07 01:53:53 PM PST 24
Peak memory 248912 kb
Host smart-9842bb45-6296-4692-9257-83133c30a0bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29032
92550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2903292550
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1144738483
Short name T344
Test name
Test status
Simulation time 27756291421 ps
CPU time 386.05 seconds
Started Mar 07 01:53:45 PM PST 24
Finished Mar 07 02:00:12 PM PST 24
Peak memory 257240 kb
Host smart-914e799b-5292-4e33-9d33-47caa1f3cfe5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144738483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1144738483
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3337088819
Short name T570
Test name
Test status
Simulation time 31878535643 ps
CPU time 2000.06 seconds
Started Mar 07 01:53:34 PM PST 24
Finished Mar 07 02:26:54 PM PST 24
Peak memory 273616 kb
Host smart-8565c9a6-e6ea-46ff-a788-f1b0ad35a6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337088819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3337088819
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.962800706
Short name T566
Test name
Test status
Simulation time 2311451271 ps
CPU time 137.02 seconds
Started Mar 07 01:53:33 PM PST 24
Finished Mar 07 01:55:51 PM PST 24
Peak memory 248680 kb
Host smart-230a92d2-9a9d-4ddf-8376-65032071a764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96280
0706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.962800706
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1324617931
Short name T634
Test name
Test status
Simulation time 461812608 ps
CPU time 31.96 seconds
Started Mar 07 01:53:46 PM PST 24
Finished Mar 07 01:54:18 PM PST 24
Peak memory 255448 kb
Host smart-592b6f2a-2844-480a-83f5-be28c7b0604d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13246
17931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1324617931
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3616145185
Short name T321
Test name
Test status
Simulation time 138245044068 ps
CPU time 2027.85 seconds
Started Mar 07 01:53:34 PM PST 24
Finished Mar 07 02:27:23 PM PST 24
Peak memory 273028 kb
Host smart-1229f35d-19d5-4e21-b452-6cca2e4c7496
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616145185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3616145185
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.4129804877
Short name T254
Test name
Test status
Simulation time 437749587303 ps
CPU time 2436.89 seconds
Started Mar 07 01:53:32 PM PST 24
Finished Mar 07 02:34:10 PM PST 24
Peak memory 282876 kb
Host smart-a5901844-5c24-4d39-a330-98de0bb31803
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129804877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.4129804877
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1858521919
Short name T306
Test name
Test status
Simulation time 19245225874 ps
CPU time 332.55 seconds
Started Mar 07 01:53:33 PM PST 24
Finished Mar 07 01:59:06 PM PST 24
Peak memory 247956 kb
Host smart-0fae89d8-922b-4545-8cbf-1bc17e7b8986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858521919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1858521919
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1303666911
Short name T600
Test name
Test status
Simulation time 883571686 ps
CPU time 22.15 seconds
Started Mar 07 01:53:34 PM PST 24
Finished Mar 07 01:53:56 PM PST 24
Peak memory 249028 kb
Host smart-90992b31-5985-4189-b2e3-3fc617c94a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13036
66911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1303666911
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1917986907
Short name T347
Test name
Test status
Simulation time 1126356306 ps
CPU time 29.53 seconds
Started Mar 07 01:53:32 PM PST 24
Finished Mar 07 01:54:01 PM PST 24
Peak memory 247624 kb
Host smart-dcea4f0b-da89-4671-990b-6450ee1acc55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19179
86907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1917986907
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1706231344
Short name T436
Test name
Test status
Simulation time 181458202 ps
CPU time 8.33 seconds
Started Mar 07 01:53:46 PM PST 24
Finished Mar 07 01:53:55 PM PST 24
Peak memory 252688 kb
Host smart-58628592-434d-490a-8216-23a9822fd986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17062
31344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1706231344
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2235471986
Short name T465
Test name
Test status
Simulation time 4535881165 ps
CPU time 44.81 seconds
Started Mar 07 01:53:46 PM PST 24
Finished Mar 07 01:54:31 PM PST 24
Peak memory 249052 kb
Host smart-f38c5abf-cb31-44d5-9ded-a9dcb505c6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22354
71986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2235471986
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1545902319
Short name T395
Test name
Test status
Simulation time 29295672649 ps
CPU time 1315.02 seconds
Started Mar 07 01:53:46 PM PST 24
Finished Mar 07 02:15:42 PM PST 24
Peak memory 290008 kb
Host smart-c280ea14-9a04-48f5-99f2-a138b9ebc360
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545902319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1545902319
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.4184677674
Short name T214
Test name
Test status
Simulation time 16092054 ps
CPU time 2.93 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:51:27 PM PST 24
Peak memory 249168 kb
Host smart-66cd90fc-43e7-4a2a-a8fd-f0056fce348e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4184677674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.4184677674
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2095468212
Short name T583
Test name
Test status
Simulation time 63558118038 ps
CPU time 2341.19 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 02:30:22 PM PST 24
Peak memory 289352 kb
Host smart-347c58c3-48ba-45b8-8824-09663dc62078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095468212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2095468212
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.4269692895
Short name T484
Test name
Test status
Simulation time 1089711647 ps
CPU time 15.06 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:51:41 PM PST 24
Peak memory 248852 kb
Host smart-86378938-6f79-4325-aeba-55bda4149af3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4269692895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.4269692895
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2250085788
Short name T497
Test name
Test status
Simulation time 4116039790 ps
CPU time 224.41 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:55:01 PM PST 24
Peak memory 256640 kb
Host smart-dfac4664-0937-4f04-98d0-565bea7f2b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22500
85788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2250085788
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2322795888
Short name T679
Test name
Test status
Simulation time 9912766911 ps
CPU time 38.96 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:52:01 PM PST 24
Peak memory 248740 kb
Host smart-d937d6cd-6394-4307-b359-f90ffb8e9e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23227
95888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2322795888
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2017613694
Short name T553
Test name
Test status
Simulation time 59336529126 ps
CPU time 2126.31 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 02:26:46 PM PST 24
Peak memory 289932 kb
Host smart-36a16f4b-330c-4b97-bf29-3d6398dbda20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017613694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2017613694
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.2443721655
Short name T80
Test name
Test status
Simulation time 1246670280 ps
CPU time 22.44 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:44 PM PST 24
Peak memory 255404 kb
Host smart-8f59779e-3b69-4926-ba5b-d8f7de915901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24437
21655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.2443721655
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3350614845
Short name T367
Test name
Test status
Simulation time 1421498509 ps
CPU time 23.23 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 255056 kb
Host smart-58976df1-e0b8-487f-b090-7ed8bbbcf60b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33506
14845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3350614845
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2645880581
Short name T32
Test name
Test status
Simulation time 3265827626 ps
CPU time 63.48 seconds
Started Mar 07 01:51:16 PM PST 24
Finished Mar 07 01:52:19 PM PST 24
Peak memory 255360 kb
Host smart-dd47d28b-6661-4e12-9071-c74b92d548c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
80581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2645880581
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2275945249
Short name T565
Test name
Test status
Simulation time 618829326 ps
CPU time 35.69 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:56 PM PST 24
Peak memory 256068 kb
Host smart-cda253b2-5678-4197-9594-816333cd71ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22759
45249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2275945249
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3789991804
Short name T248
Test name
Test status
Simulation time 16503724455 ps
CPU time 898.4 seconds
Started Mar 07 01:51:28 PM PST 24
Finished Mar 07 02:06:27 PM PST 24
Peak memory 265420 kb
Host smart-2aa0a493-dac6-40b1-b6f2-515c6a6adfcc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789991804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3789991804
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2005553932
Short name T209
Test name
Test status
Simulation time 37200961 ps
CPU time 2.17 seconds
Started Mar 07 01:51:18 PM PST 24
Finished Mar 07 01:51:21 PM PST 24
Peak memory 249072 kb
Host smart-2a0f1911-f41d-4c08-bac6-93361ded4859
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2005553932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2005553932
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1306852205
Short name T109
Test name
Test status
Simulation time 15255114787 ps
CPU time 661.32 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 02:02:24 PM PST 24
Peak memory 266432 kb
Host smart-811b1ce1-3dda-44c1-9f13-3721b846982f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306852205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1306852205
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2425655393
Short name T644
Test name
Test status
Simulation time 1084891060 ps
CPU time 42.93 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:52:08 PM PST 24
Peak memory 248616 kb
Host smart-e223cf37-da4d-4a82-b3e0-698090212ca3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2425655393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2425655393
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.437795036
Short name T228
Test name
Test status
Simulation time 12351472821 ps
CPU time 362.39 seconds
Started Mar 07 01:51:14 PM PST 24
Finished Mar 07 01:57:17 PM PST 24
Peak memory 257244 kb
Host smart-f4321a02-7cdf-42b6-963f-1bef7c7694a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43779
5036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.437795036
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1638197702
Short name T274
Test name
Test status
Simulation time 355006122 ps
CPU time 31.1 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 255208 kb
Host smart-1860c97f-76bf-44a8-9bfc-128070783770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16381
97702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1638197702
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3178351300
Short name T327
Test name
Test status
Simulation time 11887928088 ps
CPU time 963.24 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 02:07:24 PM PST 24
Peak memory 273296 kb
Host smart-b4d9931c-8f4e-4e7d-8f28-73180103b27e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178351300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3178351300
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2961596325
Short name T689
Test name
Test status
Simulation time 175557817996 ps
CPU time 2813.11 seconds
Started Mar 07 01:51:17 PM PST 24
Finished Mar 07 02:38:11 PM PST 24
Peak memory 289136 kb
Host smart-c3789aaa-a943-474f-9b89-112459a8ff9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961596325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2961596325
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.914065145
Short name T310
Test name
Test status
Simulation time 13738138908 ps
CPU time 573.28 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 02:00:58 PM PST 24
Peak memory 246788 kb
Host smart-734097c3-b6e3-49fd-8ca8-4c865cb77faa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914065145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.914065145
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2629897854
Short name T637
Test name
Test status
Simulation time 293639993 ps
CPU time 31.53 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:51:53 PM PST 24
Peak memory 248960 kb
Host smart-9213811c-052e-4a38-9432-8cfc49ee9ac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26298
97854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2629897854
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3244654672
Short name T452
Test name
Test status
Simulation time 1367973804 ps
CPU time 69.53 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:52:28 PM PST 24
Peak memory 256612 kb
Host smart-cdbdd6fe-f2c6-4be3-8cc6-4065c7d61366
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32446
54672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3244654672
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4112713983
Short name T613
Test name
Test status
Simulation time 311854765 ps
CPU time 15.03 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:51:37 PM PST 24
Peak memory 255400 kb
Host smart-c187741e-2476-436a-86b9-a62df853f61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41127
13983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4112713983
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2931567912
Short name T362
Test name
Test status
Simulation time 1148754094 ps
CPU time 26.91 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:51:52 PM PST 24
Peak memory 248900 kb
Host smart-44183dc3-558b-421f-97a3-e045efe52b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
67912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2931567912
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.1500012567
Short name T210
Test name
Test status
Simulation time 29816081 ps
CPU time 3.17 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:22 PM PST 24
Peak memory 249160 kb
Host smart-6eedc23c-69fe-48a0-a6bb-771927e64a04
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1500012567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.1500012567
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.683719355
Short name T413
Test name
Test status
Simulation time 33230934982 ps
CPU time 1992.86 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 02:24:39 PM PST 24
Peak memory 273220 kb
Host smart-033c588e-b5ed-4d34-9109-3c0e1c8193b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683719355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.683719355
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2758114211
Short name T670
Test name
Test status
Simulation time 1222851977 ps
CPU time 53.74 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:52:09 PM PST 24
Peak memory 248976 kb
Host smart-ac39702d-f887-427d-bd03-c1609dcb85e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2758114211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2758114211
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2241115524
Short name T515
Test name
Test status
Simulation time 36425544845 ps
CPU time 347.95 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:57:08 PM PST 24
Peak memory 257200 kb
Host smart-a78257e7-f934-41aa-b472-1514e3b81826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22411
15524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2241115524
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1931203667
Short name T115
Test name
Test status
Simulation time 418593207 ps
CPU time 26.13 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:46 PM PST 24
Peak memory 255416 kb
Host smart-181a95ea-6930-4b6b-b577-2f92aa2ed09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
03667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1931203667
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.914916700
Short name T286
Test name
Test status
Simulation time 49234505421 ps
CPU time 1417.45 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 02:14:57 PM PST 24
Peak memory 265404 kb
Host smart-3eac1882-ce38-4732-9af1-c73567eb7cdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914916700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.914916700
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3148325594
Short name T393
Test name
Test status
Simulation time 29611292495 ps
CPU time 1667.96 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 02:19:12 PM PST 24
Peak memory 273300 kb
Host smart-48d30972-19e6-46d1-a627-083a03c8b6e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148325594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3148325594
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1849590000
Short name T190
Test name
Test status
Simulation time 2626265453 ps
CPU time 113.92 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 01:53:15 PM PST 24
Peak memory 247852 kb
Host smart-9f0c8ede-431f-4fc7-b1b3-dfda71c396d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849590000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1849590000
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3980394179
Short name T442
Test name
Test status
Simulation time 62719291 ps
CPU time 2.93 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:51:18 PM PST 24
Peak memory 240796 kb
Host smart-cbe417a8-a99b-4480-a6ce-43d9ef6a8034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39803
94179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3980394179
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.601263068
Short name T617
Test name
Test status
Simulation time 1397856662 ps
CPU time 50.96 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:52:11 PM PST 24
Peak memory 255580 kb
Host smart-274f3ac1-7056-4b8d-bba1-2e7f4b559d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60126
3068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.601263068
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3568768273
Short name T349
Test name
Test status
Simulation time 792226570 ps
CPU time 15.25 seconds
Started Mar 07 01:51:18 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 254136 kb
Host smart-bbeb1b58-7c47-4e3a-ac69-6a28491b215d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35687
68273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3568768273
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3328357773
Short name T686
Test name
Test status
Simulation time 342026343 ps
CPU time 10.91 seconds
Started Mar 07 01:51:23 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 248904 kb
Host smart-43a5c019-22d7-4527-8caf-9326d55d8d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33283
57773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3328357773
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.954290938
Short name T503
Test name
Test status
Simulation time 52273382856 ps
CPU time 1882.07 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 02:22:44 PM PST 24
Peak memory 303940 kb
Host smart-c32f97a1-3094-4986-bce5-d2c25143f6f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954290938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.954290938
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3394389130
Short name T246
Test name
Test status
Simulation time 33772608001 ps
CPU time 2666.42 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 02:35:46 PM PST 24
Peak memory 305804 kb
Host smart-0e4ba813-7a11-480f-aa52-6884823be4b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394389130 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3394389130
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3797272175
Short name T215
Test name
Test status
Simulation time 42532752 ps
CPU time 3.49 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:51:25 PM PST 24
Peak memory 249180 kb
Host smart-29fde86b-1c9c-49f6-ad3e-c3cd6feb99e6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3797272175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3797272175
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1821539071
Short name T582
Test name
Test status
Simulation time 54901601624 ps
CPU time 1586.97 seconds
Started Mar 07 01:51:18 PM PST 24
Finished Mar 07 02:17:46 PM PST 24
Peak memory 282660 kb
Host smart-9f6f6740-d05b-4d8e-b825-5feb2d0bb3c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821539071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1821539071
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1691042574
Short name T627
Test name
Test status
Simulation time 647963277 ps
CPU time 26.4 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:46 PM PST 24
Peak memory 240772 kb
Host smart-ce1170a8-b3d1-4319-8610-79b32465aeec
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1691042574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1691042574
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3432832256
Short name T366
Test name
Test status
Simulation time 2704465174 ps
CPU time 87.36 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:52:50 PM PST 24
Peak memory 249032 kb
Host smart-1436392e-8ba1-48fe-92ca-e551455a7ba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34328
32256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3432832256
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.359066096
Short name T427
Test name
Test status
Simulation time 1065776919 ps
CPU time 53.54 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:52:13 PM PST 24
Peak memory 254796 kb
Host smart-cac56b7a-325c-4f03-a00b-7774223f93e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
6096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.359066096
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.267224866
Short name T317
Test name
Test status
Simulation time 75732585308 ps
CPU time 2367.37 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 02:30:46 PM PST 24
Peak memory 286424 kb
Host smart-3ed6f63a-fb3d-4df6-891b-2b3d4828eaf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267224866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.267224866
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.876885489
Short name T531
Test name
Test status
Simulation time 80177623197 ps
CPU time 1285.14 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 02:12:45 PM PST 24
Peak memory 272428 kb
Host smart-555616b6-448a-4ab9-90b7-6004b273670d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876885489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.876885489
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.861072170
Short name T555
Test name
Test status
Simulation time 21063124375 ps
CPU time 112.04 seconds
Started Mar 07 01:51:22 PM PST 24
Finished Mar 07 01:53:14 PM PST 24
Peak memory 247160 kb
Host smart-421622cc-12af-4a09-b216-320d27dc52a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861072170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.861072170
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.1325436517
Short name T435
Test name
Test status
Simulation time 2901493508 ps
CPU time 33.78 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:54 PM PST 24
Peak memory 249148 kb
Host smart-c7f4ac49-59db-4a41-b88f-c7d344425978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13254
36517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.1325436517
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3277282085
Short name T517
Test name
Test status
Simulation time 236715722 ps
CPU time 23.58 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 255372 kb
Host smart-c713a8b3-d08c-4c6c-a877-1c3d3fe5b1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32772
82085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3277282085
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2808436670
Short name T429
Test name
Test status
Simulation time 954599960 ps
CPU time 53.12 seconds
Started Mar 07 01:51:15 PM PST 24
Finished Mar 07 01:52:09 PM PST 24
Peak memory 249044 kb
Host smart-7abd808e-dcea-4b80-a533-77dc2e3bc9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28084
36670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2808436670
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2301264948
Short name T86
Test name
Test status
Simulation time 37380136342 ps
CPU time 1761.5 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 02:20:47 PM PST 24
Peak memory 289856 kb
Host smart-9328ccd5-81b4-4dca-ae5f-0892fd06dffb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301264948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2301264948
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2241500769
Short name T206
Test name
Test status
Simulation time 45524374 ps
CPU time 3.63 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:34 PM PST 24
Peak memory 249148 kb
Host smart-cd3c321a-e29d-4fa7-a600-5008be330d54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2241500769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2241500769
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.266162199
Short name T628
Test name
Test status
Simulation time 69614910940 ps
CPU time 1053.81 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 02:08:54 PM PST 24
Peak memory 272932 kb
Host smart-a7bd5dab-5219-43fe-9824-291ad4a061eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266162199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.266162199
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.33684729
Short name T468
Test name
Test status
Simulation time 449222129 ps
CPU time 12.97 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 01:51:47 PM PST 24
Peak memory 240768 kb
Host smart-2d2f8bdf-3f23-40c3-aa98-d2aa0efec7ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=33684729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.33684729
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4214525934
Short name T510
Test name
Test status
Simulation time 602890797 ps
CPU time 21.07 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:51:40 PM PST 24
Peak memory 254436 kb
Host smart-ccf5f2f3-b35f-4a89-88d5-208ca42fe0a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42145
25934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4214525934
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3959876764
Short name T631
Test name
Test status
Simulation time 257235985 ps
CPU time 23.25 seconds
Started Mar 07 01:51:26 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 247296 kb
Host smart-05c299f7-63f4-4570-a828-8a5b804bd0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
76764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3959876764
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1690099418
Short name T611
Test name
Test status
Simulation time 306225229286 ps
CPU time 3195.5 seconds
Started Mar 07 01:51:21 PM PST 24
Finished Mar 07 02:44:37 PM PST 24
Peak memory 289464 kb
Host smart-a303164e-1090-4254-b2e8-3313c66829ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690099418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1690099418
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.150348724
Short name T305
Test name
Test status
Simulation time 20854825786 ps
CPU time 222.22 seconds
Started Mar 07 01:51:19 PM PST 24
Finished Mar 07 01:55:01 PM PST 24
Peak memory 246812 kb
Host smart-5ca85593-a9ec-4146-a2a4-8959acbad2ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150348724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.150348724
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2816999116
Short name T513
Test name
Test status
Simulation time 1332511846 ps
CPU time 23.13 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:43 PM PST 24
Peak memory 248840 kb
Host smart-3ffe86d6-4356-4738-b716-fdafc6d24caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
99116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2816999116
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.139157684
Short name T407
Test name
Test status
Simulation time 1634595085 ps
CPU time 25.16 seconds
Started Mar 07 01:51:24 PM PST 24
Finished Mar 07 01:51:49 PM PST 24
Peak memory 248368 kb
Host smart-4e427e0d-46bd-4e08-83f7-6ece07cbd432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13915
7684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.139157684
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.700796975
Short name T664
Test name
Test status
Simulation time 4109116873 ps
CPU time 64.64 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:52:30 PM PST 24
Peak memory 248140 kb
Host smart-27072803-a2c2-4b15-a366-0fc389d8850b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70079
6975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.700796975
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1095772368
Short name T608
Test name
Test status
Simulation time 3640617279 ps
CPU time 42.21 seconds
Started Mar 07 01:51:25 PM PST 24
Finished Mar 07 01:52:08 PM PST 24
Peak memory 249064 kb
Host smart-f7a8c551-9402-4576-ae8b-08506889d86e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
72368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1095772368
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1102585826
Short name T622
Test name
Test status
Simulation time 1481569245 ps
CPU time 36.34 seconds
Started Mar 07 01:51:20 PM PST 24
Finished Mar 07 01:51:57 PM PST 24
Peak memory 256012 kb
Host smart-bba0cd96-b98d-4b92-95d7-89b134fc1e24
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102585826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1102585826
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1374166955
Short name T564
Test name
Test status
Simulation time 122516796635 ps
CPU time 3011.11 seconds
Started Mar 07 01:51:29 PM PST 24
Finished Mar 07 02:41:41 PM PST 24
Peak memory 315196 kb
Host smart-ba2df70b-800c-4078-86c1-70f24375354a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374166955 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1374166955
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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