Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	56759	1			T5	1079		T26	8		T47	348
class_i[0x1]	83457	1			T9	1075		T27	115		T47	3
class_i[0x2]	77078	1			T1	2303		T5	1		T27	62
class_i[0x3]	66850	1			T5	48		T9	807		T15	6

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	72659	1			T1	477		T5	215		T9	1104
alert[0x1]	69148	1			T1	603		T5	297		T26	1
alert[0x2]	72571	1			T1	572		T5	289		T26	5
alert[0x3]	69766	1			T1	651		T5	327		T26	2

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

283866

1

T1

2303

T5

1128

T26

8

esc_ping_fail

278

1

T15

6

T17

4

T18

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	72587	1			T1	477		T5	215		T9	1104
esc_integrity_fail	alert[0x1]	69075	1			T1	603		T5	297		T26	1
esc_integrity_fail	alert[0x2]	72500	1			T1	572		T5	289		T26	5
esc_integrity_fail	alert[0x3]	69704	1			T1	651		T5	327		T26	2
esc_ping_fail	alert[0x0]	72	1			T15	2		T17	1		T18	3
esc_ping_fail	alert[0x1]	73	1			T15	2		T18	1		T38	2
esc_ping_fail	alert[0x2]	71	1			T15	1		T17	1		T18	2
esc_ping_fail	alert[0x3]	62	1			T15	1		T17	2		T18	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	56715	1			T5	1079		T26	8		T47	348
esc_integrity_fail	class_i[0x1]	83380	1			T9	1075		T27	115		T47	3
esc_integrity_fail	class_i[0x2]	77033	1			T1	2303		T5	1		T27	62
esc_integrity_fail	class_i[0x3]	66738	1			T5	48		T9	807		T45	347
esc_ping_fail	class_i[0x0]	44	1			T18	1		T299	1		T241	1
esc_ping_fail	class_i[0x1]	77	1			T18	6		T115	1		T304	7
esc_ping_fail	class_i[0x2]	45	1			T299	1		T241	6		T115	1
esc_ping_fail	class_i[0x3]	112	1			T15	6		T17	4		T38	7