Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	694166456	0	0	625
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	694166456	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	694166456	693980546	0	0
tb.dut.CheckAccuCntDw	0	0	625	625	0	0
tb.dut.CheckEscCntDw	0	0	625	625	0	0
tb.dut.CheckNAlerts	0	0	625	625	0	0
tb.dut.CheckNClasses	0	0	625	625	0	0
tb.dut.CheckNEscSev	0	0	625	625	0	0
tb.dut.CrashdumpKnownO_A	0	0	694166456	693980546	0	0
tb.dut.EdnKnownO_A	0	0	694166456	693980546	0	0
tb.dut.EscPKnownO_A	0	0	694166456	693980546	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	694166456	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	694166456	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	694166456	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	694166456	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	694166456	90	0	0
tb.dut.IrqAKnownO_A	0	0	694166456	693980546	0	0
tb.dut.IrqBKnownO_A	0	0	694166456	693980546	0	0
tb.dut.IrqCKnownO_A	0	0	694166456	693980546	0	0
tb.dut.IrqDKnownO_A	0	0	694166456	693980546	0	0
tb.dut.TlAReadyKnownO_A	0	0	694166456	693980546	0	0
tb.dut.TlDValidKnownO_A	0	0	694166456	693980546	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	719926393	2899123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	719926393	20794	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	719926393	22248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	719926393	22035	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	719926393	22249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	719926393	20715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	719926393	22241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	719926393	20621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	719926393	22052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	719926393	20847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	719926393	20828	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	719926393	22113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	719926393	21874	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	719926393	21014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	719926393	21029	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	719926393	21083	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	719926393	20835	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	719926393	21151	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	719926393	20503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	719926393	22058	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	719926393	20687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	719926393	21117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	719926393	21072	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	719926393	20982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	719926393	20832	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	719926393	20588	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	719926393	21221	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	719926393	21959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	719926393	23353	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	719926393	20936	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	719926393	20812	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	719926393	20361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	719926393	22295	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	719926393	22037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	719926393	21841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	719926393	21125	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	719926393	22087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	719926393	22103	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	719926393	21834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	719926393	22414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	719926393	22067	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	719926393	21173	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	719926393	20691	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	719926393	22341	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	719926393	21137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	719926393	20906	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	719926393	20966	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	719926393	23545	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	719926393	20961	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	719926393	20815	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	719926393	22054	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	719926393	21311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	719926393	20952	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	719926393	20392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	719926393	20790	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	719926393	22497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	719926393	22109	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	719926393	22031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	719926393	20841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	719926393	22247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	719926393	20725	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	719926393	20979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	719926393	21977	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	719926393	22283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	719926393	21925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	719926393	21006	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	719926393	21278	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	719926393	22084	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	719926393	20941	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	719926393	21247	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	719926393	42141	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	719926393	20672	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	719926393	20483	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	719926393	20817	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	719926393	20744	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	719926393	20290	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	719926393	20701	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	719926393	20773	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	719926393	20608	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	694166456	6429	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	694166456	221805	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	694166456	339652113	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	694166456	310	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	694166456	906	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	694166456	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	694166456	460	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	693902987	259115194	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	694166456	996	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	694166456	975	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	694166456	956	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	694166456	932	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	694166456	1508	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	694166456	147037	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	694166456	1396	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	694166456	61	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694166456	1580	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	694166456	1310	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	694166456	693980546	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	694166456	185	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	694166456	150394	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	694166456	431889312	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	694166456	308	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	694166456	426	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	694166456	12	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	694166456	153	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	693902987	349491710	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	694166456	490	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	694166456	483	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	694166456	475	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	694166456	466	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	694166456	1064	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	694166456	117998	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	694166456	993	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	694166456	57	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694166456	1601	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	694166456	1331	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	694166456	693980546	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	694166456	805	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	694166456	167026	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	694166456	414179997	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	694166456	361	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	694166456	497	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	694166456	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	694166456	235	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	693902987	344771252	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	694166456	580	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	694166456	568	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	694166456	558	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	694166456	544	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	694166456	851	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	694166456	98108	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	694166456	759	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	694166456	73	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694166456	1588	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	694166456	1318	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	694166456	693980546	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	694166456	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	694166456	5298	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	694166456	233604	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	694166456	401161657	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	694166456	301	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	694166456	536	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	694166456	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	694166456	248	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	693902987	318654845	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	694166456	615	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	694166456	608	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	694166456	595	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	694166456	580	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	694166456	1017	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	694166456	120099	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	694166456	928	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	694166456	63	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	694166456	1592	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	694166456	1322	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	625	625	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	694166456	693980546	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	719926393	136290136	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	719926393	719236792	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	719926393	719236792	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	719926393	202147816	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	719926393	719236792	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	719926393	719236792	0	0
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