Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	184	1			T1	3		T3	1		T5	1
index[0x1]	199	1			T5	1		T43	2		T27	3
index[0x2]	175	1			T1	1		T5	1		T9	1
index[0x3]	218	1			T1	2		T10	1		T26	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	244	1			T1	4		T5	2		T26	1
lens_less_than_1000[1]	133	1			T27	2		T21	1		T68	1
lens_less_than_1000[2]	130	1			T5	1		T10	1		T20	1
lens_less_than_1000[3]	85	1			T9	1		T49	2		T80	1
lens_less_than_1000[4]	47	1			T45	1		T71	1		T76	1
lens_less_than_1000[5]	56	1			T1	2		T28	1		T31	1
lens_less_than_1000[6]	28	1			T3	1		T21	1		T75	1
lens_less_than_1000[7]	33	1			T43	2		T28	3		T75	1
lens_less_than_1000[8]	7	1			T47	1		T206	1		T275	1
lens_less_than_1000[9]	4	1			T127	1		T276	1		T277	1
len_2	9	1			T50	2		T278	1		T279	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x2] , index[0x3]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	57	1			T1	2		T5	1		T21	1
index[0x0]	lens_less_than_1000[1]	29	1			T31	1		T52	1		T109	7
index[0x0]	lens_less_than_1000[2]	26	1			T20	1		T31	1		T35	1
index[0x0]	lens_less_than_1000[3]	25	1			T51	1		T280	1		T89	1
index[0x0]	lens_less_than_1000[4]	13	1			T45	1		T281	1		T194	2
index[0x0]	lens_less_than_1000[5]	15	1			T1	1		T282	1		T53	1
index[0x0]	lens_less_than_1000[6]	6	1			T3	1		T84	1		T259	1
index[0x0]	lens_less_than_1000[7]	6	1			T75	1		T117	1		T281	1
index[0x0]	lens_less_than_1000[8]	2	1			T206	1		T272	1		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T276	1		T283	1		-	-
index[0x0]	len_2	3	1			T50	1		T260	1		T284	1
index[0x1]	lens_less_than_1000[0]	72	1			T5	1		T27	3		T46	1
index[0x1]	lens_less_than_1000[1]	31	1			T21	1		T68	1		T28	1
index[0x1]	lens_less_than_1000[2]	35	1			T285	1		T39	9		T124	1
index[0x1]	lens_less_than_1000[3]	17	1			T49	1		T282	1		T86	1
index[0x1]	lens_less_than_1000[4]	6	1			T76	1		T52	1		T111	1
index[0x1]	lens_less_than_1000[5]	11	1			T37	1		T82	1		T96	1
index[0x1]	lens_less_than_1000[6]	8	1			T75	1		T51	1		T286	1
index[0x1]	lens_less_than_1000[7]	11	1			T43	2		T28	3		T117	1
index[0x1]	lens_less_than_1000[8]	2	1			T47	1		T287	1		-	-
index[0x1]	lens_less_than_1000[9]	2	1			T127	1		T277	1		-	-
index[0x1]	len_2	4	1			T50	1		T279	1		T260	1
index[0x2]	lens_less_than_1000[0]	53	1			T27	1		T45	1		T21	1
index[0x2]	lens_less_than_1000[1]	37	1			T27	1		T31	2		T38	1
index[0x2]	lens_less_than_1000[2]	31	1			T5	1		T288	1		T111	1
index[0x2]	lens_less_than_1000[3]	16	1			T9	1		T52	1		T205	1
index[0x2]	lens_less_than_1000[4]	14	1			T109	1		T256	1		T54	2
index[0x2]	lens_less_than_1000[5]	7	1			T1	1		T31	1		T89	1
index[0x2]	lens_less_than_1000[6]	8	1			T51	1		T289	1		T113	1
index[0x2]	lens_less_than_1000[7]	6	1			T76	1		T120	2		T95	1
index[0x2]	lens_less_than_1000[8]	2	1			T275	1		T255	1		-	-
index[0x2]	len_2	1	1			T278	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	62	1			T1	2		T26	1		T8	1
index[0x3]	lens_less_than_1000[1]	36	1			T27	1		T75	1		T31	4
index[0x3]	lens_less_than_1000[2]	38	1			T10	1		T52	3		T208	1
index[0x3]	lens_less_than_1000[3]	27	1			T49	1		T80	1		T241	1
index[0x3]	lens_less_than_1000[4]	14	1			T71	1		T205	1		T55	1
index[0x3]	lens_less_than_1000[5]	23	1			T28	1		T256	1		T96	1
index[0x3]	lens_less_than_1000[6]	6	1			T21	1		T268	1		T290	1
index[0x3]	lens_less_than_1000[7]	10	1			T76	1		T33	1		T291	1
index[0x3]	lens_less_than_1000[8]	1	1			T292	1		-	-		-	-
index[0x3]	len_2	1	1			T293	1		-	-		-	-