Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.44	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	3	37	92.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	3	37	92.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	61	1			T5	1		T27	1		T45	1
class_index[0x1]	57	1			T1	2		T67	1		T21	1
class_index[0x2]	73	1			T11	1		T23	1		T26	3
class_index[0x3]	63	1			T26	1		T21	1		T75	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	79	1			T47	1		T21	2		T28	1
intr_timeout_cnt[1]	64	1			T1	1		T23	1		T67	1
intr_timeout_cnt[2]	32	1			T11	1		T75	3		T78	1
intr_timeout_cnt[3]	16	1			T80	1		T35	1		T97	1
intr_timeout_cnt[4]	17	1			T1	1		T5	1		T26	3
intr_timeout_cnt[5]	17	1			T27	1		T45	1		T79	1
intr_timeout_cnt[6]	14	1			T75	1		T31	2		T80	1
intr_timeout_cnt[7]	6	1			T33	1		T35	1		T119	1
intr_timeout_cnt[8]	6	1			T45	1		T35	1		T254	1
intr_timeout_cnt[9]	3	1			T26	1		T98	1		T255	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	3	37	92.50	3

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	11	1			T33	1		T256	1		T55	1
class_index[0x0]	intr_timeout_cnt[1]	17	1			T122	1		T257	1		T125	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T78	1		T51	1		T258	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T80	1		T259	1		T198	1
class_index[0x0]	intr_timeout_cnt[4]	5	1			T5	1		T75	1		T260	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T27	1		T79	1		T57	1
class_index[0x0]	intr_timeout_cnt[6]	6	1			T52	1		T261	1		T262	2
class_index[0x0]	intr_timeout_cnt[8]	3	1			T45	1		T254	1		T102	1
class_index[0x1]	intr_timeout_cnt[0]	24	1			T21	1		T75	3		T82	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T1	1		T67	1		T51	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T75	1		T52	2		T125	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T81	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T1	1		T75	1		T263	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T61	2		T251	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	2	1			T80	1		T33	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T119	1		T252	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T255	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	20	1			T47	1		T28	1		T49	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T23	1		T81	1		T264	1
class_index[0x2]	intr_timeout_cnt[2]	11	1			T11	1		T75	2		T55	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T97	1		T265	1		T255	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T26	3		T75	1		T98	1
class_index[0x2]	intr_timeout_cnt[5]	8	1			T45	1		T246	1		T125	1
class_index[0x2]	intr_timeout_cnt[6]	4	1			T31	2		T94	1		T266	1
class_index[0x2]	intr_timeout_cnt[7]	2	1			T35	1		T125	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T267	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T98	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	24	1			T21	1		T75	1		T80	1
class_index[0x3]	intr_timeout_cnt[1]	15	1			T75	1		T117	1		T123	1
class_index[0x3]	intr_timeout_cnt[2]	7	1			T122	1		T268	1		T255	2
class_index[0x3]	intr_timeout_cnt[3]	5	1			T35	1		T269	1		T270	3
class_index[0x3]	intr_timeout_cnt[4]	4	1			T98	1		T260	2		T271	1
class_index[0x3]	intr_timeout_cnt[5]	1	1			T272	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T75	1		T212	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T33	1		T273	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	2	1			T35	1		T274	1		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T26	1		-	-		-	-