Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	360227	1			T1	1390		T2	21		T3	1845
all_values[1]	360227	1			T1	1390		T2	21		T3	1845
all_values[2]	360227	1			T1	1390		T2	21		T3	1845
all_values[3]	360227	1			T1	1390		T2	21		T3	1845

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718568

1

T1

2742

T2

49

T3

3702

auto[1]

722340

1

T1

2818

T2

35

T3

3678

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

852288

1

T1

3145

T2

44

T3

3710

auto[1]

588620

1

T1

2415

T2

40

T3

3670

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103509	1			T1	374		T2	5		T3	447
all_values[0]	auto[0]	auto[1]	76441	1			T1	265		T2	4		T3	438
all_values[0]	auto[1]	auto[0]	104260	1			T1	453		T2	6		T3	486
all_values[0]	auto[1]	auto[1]	76017	1			T1	298		T2	6		T3	474
all_values[1]	auto[0]	auto[0]	107771	1			T1	402		T2	7		T3	471
all_values[1]	auto[0]	auto[1]	72029	1			T1	323		T2	6		T3	469
all_values[1]	auto[1]	auto[0]	108639	1			T1	370		T2	4		T3	453
all_values[1]	auto[1]	auto[1]	71788	1			T1	295		T2	4		T3	452
all_values[2]	auto[0]	auto[0]	105832	1			T1	368		T2	5		T3	475
all_values[2]	auto[0]	auto[1]	73089	1			T1	322		T2	5		T3	475
all_values[2]	auto[1]	auto[0]	107882	1			T1	383		T2	6		T3	448
all_values[2]	auto[1]	auto[1]	73424	1			T1	317		T2	5		T3	447
all_values[3]	auto[0]	auto[0]	106863	1			T1	395		T2	9		T3	469
all_values[3]	auto[0]	auto[1]	73034	1			T1	293		T2	8		T3	458
all_values[3]	auto[1]	auto[0]	107532	1			T1	400		T2	2		T3	461
all_values[3]	auto[1]	auto[1]	72798	1			T1	302		T2	2		T3	457