Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	360227	1			T1	1390		T2	21		T3	1845
all_pins[1]	360227	1			T1	1390		T2	21		T3	1845
all_pins[2]	360227	1			T1	1390		T2	21		T3	1845
all_pins[3]	360227	1			T1	1390		T2	21		T3	1845

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1146881	1			T1	4348		T2	67		T3	5550
values[0x1]	294027	1			T1	1212		T2	17		T3	1830
transitions[0x0=>0x1]	194931	1			T1	775		T2	13		T3	1163
transitions[0x1=>0x0]	195183	1			T1	775		T2	13		T3	1163

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	284210	1			T1	1092		T2	15		T3	1371
all_pins[0]	values[0x1]	76017	1			T1	298		T2	6		T3	474
all_pins[0]	transitions[0x0=>0x1]	75349	1			T1	297		T2	6		T3	474
all_pins[0]	transitions[0x1=>0x0]	72382	1			T1	301		T2	2		T3	457
all_pins[1]	values[0x0]	288439	1			T1	1095		T2	17		T3	1393
all_pins[1]	values[0x1]	71788	1			T1	295		T2	4		T3	452
all_pins[1]	transitions[0x0=>0x1]	39154	1			T1	160		T2	2		T3	226
all_pins[1]	transitions[0x1=>0x0]	43383	1			T1	163		T2	4		T3	248
all_pins[2]	values[0x0]	286803	1			T1	1073		T2	16		T3	1398
all_pins[2]	values[0x1]	73424	1			T1	317		T2	5		T3	447
all_pins[2]	transitions[0x0=>0x1]	40724	1			T1	165		T2	3		T3	230
all_pins[2]	transitions[0x1=>0x0]	39088	1			T1	143		T2	2		T3	235
all_pins[3]	values[0x0]	287429	1			T1	1088		T2	19		T3	1388
all_pins[3]	values[0x1]	72798	1			T1	302		T2	2		T3	457
all_pins[3]	transitions[0x0=>0x1]	39704	1			T1	153		T2	2		T3	233
all_pins[3]	transitions[0x1=>0x0]	40330	1			T1	168		T2	5		T3	223