Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	245	1			T171	4		T172	4		T173	4
all_values[1]	245	1			T171	4		T172	4		T173	4
all_values[2]	245	1			T171	4		T172	4		T173	4
all_values[3]	245	1			T171	4		T172	4		T173	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

580

1

T171

10

T172

9

T173

10

auto[1]

400

1

T171

6

T172

7

T173

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

420

1

T171

5

T172

6

T173

5

auto[1]

560

1

T171

11

T172

10

T173

11

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T171

10

T172

11

T173

9

auto[1]

379

1

T171

6

T172

5

T173

7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

70

1

T171

1

T173

3

T341

1

all_values[0]

auto[0]

auto[0]

auto[1]

29

1

T171

2

T250

1

T342

2

all_values[0]

auto[0]

auto[1]

auto[0]

32

1

T173

1

T250

1

T343

2

all_values[0]

auto[0]

auto[1]

auto[1]

20

1

T172

2

T250

1

T344

3

all_values[0]

auto[1]

auto[0]

auto[1]

55

1

T172

1

T250

1

T344

1

all_values[0]

auto[1]

auto[1]

auto[1]

39

1

T171

1

T172

1

T250

3

all_values[1]

auto[0]

auto[0]

auto[0]

55

1

T171

1

T172

2

T345

1

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T171

1

T172

1

T250

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T250

2

T344

2

T341

2

all_values[1]

auto[0]

auto[1]

auto[1]

21

1

T173

2

T250

1

T344

1

all_values[1]

auto[1]

auto[0]

auto[1]

65

1

T171

1

T172

1

T173

2

all_values[1]

auto[1]

auto[1]

auto[1]

38

1

T171

1

T250

2

T342

2

all_values[2]

auto[0]

auto[0]

auto[0]

68

1

T171

2

T172

2

T173

1

all_values[2]

auto[0]

auto[0]

auto[1]

23

1

T173

1

T250

3

T343

1

all_values[2]

auto[0]

auto[1]

auto[0]

41

1

T250

2

T344

3

T345

1

all_values[2]

auto[0]

auto[1]

auto[1]

21

1

T171

1

T172

1

T341

1

all_values[2]

auto[1]

auto[0]

auto[1]

60

1

T171

1

T172

1

T173

1

all_values[2]

auto[1]

auto[1]

auto[1]

32

1

T173

1

T341

1

T345

1

all_values[3]

auto[0]

auto[0]

auto[0]

55

1

T341

1

T345

1

T346

1

all_values[3]

auto[0]

auto[0]

auto[1]

17

1

T250

2

T344

1

T342

2

all_values[3]

auto[0]

auto[1]

auto[0]

61

1

T171

1

T172

2

T250

2

all_values[3]

auto[0]

auto[1]

auto[1]

22

1

T171

1

T172

1

T173

1

all_values[3]

auto[1]

auto[0]

auto[1]

55

1

T171

1

T172

1

T173

2

all_values[3]

auto[1]

auto[1]

auto[1]

35

1

T171

1

T173

1

T344

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal