Summary for Variable accum_cnt_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for accum_cnt_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
accum_cnt_2000 |
91033 |
1 |
|
|
T1 |
264 |
|
T3 |
572 |
|
T5 |
65 |
accum_cnt_1000 |
230529 |
1 |
|
|
T1 |
277 |
|
T3 |
513 |
|
T5 |
1108 |
accum_cnt_100 |
28961 |
1 |
|
|
T1 |
38 |
|
T3 |
28 |
|
T5 |
334 |
accum_cnt_50 |
55704 |
1 |
|
|
T1 |
180 |
|
T2 |
10 |
|
T3 |
20 |
accum_cnt_10 |
203402 |
1 |
|
|
T1 |
1626 |
|
T2 |
30 |
|
T3 |
1359 |
accum_cnt_0 |
410918 |
1 |
|
|
T1 |
1541 |
|
T2 |
40 |
|
T3 |
2711 |
Summary for Variable class_index_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for class_index_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
class_index[0x0] |
266053 |
1 |
|
|
T1 |
1019 |
|
T2 |
20 |
|
T3 |
1354 |
class_index[0x1] |
266053 |
1 |
|
|
T1 |
1019 |
|
T2 |
20 |
|
T3 |
1354 |
class_index[0x2] |
266053 |
1 |
|
|
T1 |
1019 |
|
T2 |
20 |
|
T3 |
1354 |
class_index[0x3] |
266053 |
1 |
|
|
T1 |
1019 |
|
T2 |
20 |
|
T3 |
1354 |
Summary for Cross class_cnt_cross
Samples crossed: class_index_cp accum_cnt_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
24 |
0 |
24 |
100.00 |
|
Automatically Generated Cross Bins for class_cnt_cross
Bins
class_index_cp | accum_cnt_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
class_index[0x0] |
accum_cnt_2000 |
23697 |
1 |
|
|
T5 |
65 |
|
T73 |
518 |
|
T30 |
598 |
class_index[0x0] |
accum_cnt_1000 |
63454 |
1 |
|
|
T5 |
446 |
|
T9 |
127 |
|
T27 |
45 |
class_index[0x0] |
accum_cnt_100 |
8015 |
1 |
|
|
T5 |
75 |
|
T43 |
2 |
|
T9 |
18 |
class_index[0x0] |
accum_cnt_50 |
16893 |
1 |
|
|
T1 |
28 |
|
T5 |
111 |
|
T26 |
2 |
class_index[0x0] |
accum_cnt_10 |
47484 |
1 |
|
|
T1 |
75 |
|
T2 |
3 |
|
T5 |
181 |
class_index[0x0] |
accum_cnt_0 |
94921 |
1 |
|
|
T1 |
916 |
|
T2 |
17 |
|
T3 |
1354 |
class_index[0x1] |
accum_cnt_2000 |
19014 |
1 |
|
|
T3 |
572 |
|
T70 |
422 |
|
T73 |
649 |
class_index[0x1] |
accum_cnt_1000 |
54060 |
1 |
|
|
T1 |
51 |
|
T3 |
513 |
|
T5 |
116 |
class_index[0x1] |
accum_cnt_100 |
7928 |
1 |
|
|
T1 |
21 |
|
T3 |
28 |
|
T5 |
42 |
class_index[0x1] |
accum_cnt_50 |
11901 |
1 |
|
|
T1 |
56 |
|
T3 |
20 |
|
T5 |
36 |
class_index[0x1] |
accum_cnt_10 |
61712 |
1 |
|
|
T1 |
748 |
|
T2 |
3 |
|
T3 |
7 |
class_index[0x1] |
accum_cnt_0 |
102826 |
1 |
|
|
T1 |
143 |
|
T2 |
17 |
|
T3 |
1 |
class_index[0x2] |
accum_cnt_2000 |
21143 |
1 |
|
|
T1 |
264 |
|
T14 |
354 |
|
T69 |
105 |
class_index[0x2] |
accum_cnt_1000 |
54194 |
1 |
|
|
T1 |
226 |
|
T5 |
441 |
|
T14 |
846 |
class_index[0x2] |
accum_cnt_100 |
6685 |
1 |
|
|
T1 |
15 |
|
T5 |
85 |
|
T14 |
43 |
class_index[0x2] |
accum_cnt_50 |
13874 |
1 |
|
|
T1 |
38 |
|
T2 |
4 |
|
T11 |
16 |
class_index[0x2] |
accum_cnt_10 |
47454 |
1 |
|
|
T1 |
42 |
|
T2 |
14 |
|
T11 |
4 |
class_index[0x2] |
accum_cnt_0 |
114320 |
1 |
|
|
T1 |
284 |
|
T2 |
2 |
|
T3 |
1354 |
class_index[0x3] |
accum_cnt_2000 |
27179 |
1 |
|
|
T20 |
525 |
|
T31 |
625 |
|
T49 |
136 |
class_index[0x3] |
accum_cnt_1000 |
58821 |
1 |
|
|
T5 |
105 |
|
T20 |
498 |
|
T21 |
5 |
class_index[0x3] |
accum_cnt_100 |
6333 |
1 |
|
|
T1 |
2 |
|
T5 |
132 |
|
T77 |
10 |
class_index[0x3] |
accum_cnt_50 |
13036 |
1 |
|
|
T1 |
58 |
|
T2 |
6 |
|
T5 |
16 |
class_index[0x3] |
accum_cnt_10 |
46752 |
1 |
|
|
T1 |
761 |
|
T2 |
10 |
|
T3 |
1352 |
class_index[0x3] |
accum_cnt_0 |
98851 |
1 |
|
|
T1 |
198 |
|
T2 |
4 |
|
T3 |
2 |