Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6180	1			T5	55		T9	87		T47	2
alert[0x1]	6353	1			T49	2		T50	1106		T33	24
alert[0x2]	5920	1			T28	8		T75	3		T49	26
alert[0x3]	9428	1			T1	47		T15	1		T75	58
alert[0x4]	6846	1			T5	6		T9	1		T15	1
alert[0x5]	10721	1			T5	9		T16	1		T51	3
alert[0x6]	2572	1			T16	1		T72	1		T18	1
alert[0x7]	3307	1			T9	18		T15	1		T49	2
alert[0x8]	5119	1			T5	3		T9	8		T31	3
alert[0x9]	6330	1			T1	206		T28	1		T50	22
alert[0xa]	3137	1			T1	1		T9	35		T72	1
alert[0xb]	9546	1			T9	2		T15	1		T75	17
alert[0xc]	8477	1			T1	33		T15	1		T45	2
alert[0xd]	7622	1			T26	3		T9	1		T15	1
alert[0xe]	4512	1			T45	15		T28	143		T49	60
alert[0xf]	3999	1			T1	8		T49	94		T51	1
alert[0x10]	5893	1			T1	253		T9	124		T17	1
alert[0x11]	6435	1			T1	14		T5	5		T9	56
alert[0x12]	6161	1			T9	11		T15	1		T45	1
alert[0x13]	7769	1			T27	1		T17	2		T49	327
alert[0x14]	1567	1			T9	301		T27	2		T21	1
alert[0x15]	3485	1			T8	1		T9	1		T45	47
alert[0x16]	6960	1			T5	1		T21	2		T28	29
alert[0x17]	5283	1			T9	13		T21	1		T28	1
alert[0x18]	5972	1			T26	1		T15	1		T21	5
alert[0x19]	8877	1			T1	4		T9	192		T18	1
alert[0x1a]	7779	1			T17	2		T28	2		T75	4
alert[0x1b]	5199	1			T9	26		T27	2		T33	2
alert[0x1c]	5114	1			T1	145		T5	1		T9	11
alert[0x1d]	9717	1			T5	2		T15	1		T21	4
alert[0x1e]	6191	1			T5	20		T9	6		T28	14
alert[0x1f]	3394	1			T9	12		T49	3		T50	8
alert[0x20]	4099	1			T1	118		T28	169		T299	1
alert[0x21]	5978	1			T21	14		T28	16		T31	9
alert[0x22]	2929	1			T1	51		T5	1		T26	1
alert[0x23]	15791	1			T108	6		T38	1		T52	104
alert[0x24]	5404	1			T9	8		T27	18		T45	1
alert[0x25]	2793	1			T1	82		T9	22		T45	26
alert[0x26]	6866	1			T1	204		T9	39		T15	1
alert[0x27]	6575	1			T75	9		T50	73		T76	15
alert[0x28]	5524	1			T28	3		T18	1		T51	28
alert[0x29]	4847	1			T27	7		T17	1		T28	3
alert[0x2a]	2910	1			T75	1		T50	2		T299	1
alert[0x2b]	5885	1			T9	11		T21	3		T28	3
alert[0x2c]	7427	1			T69	1		T33	24		T242	15
alert[0x2d]	6255	1			T15	1		T38	1		T299	1
alert[0x2e]	5839	1			T5	8		T9	1		T28	31
alert[0x2f]	2172	1			T26	4		T17	1		T28	65
alert[0x30]	3207	1			T9	187		T15	1		T21	3
alert[0x31]	5173	1			T1	18		T9	1		T45	3
alert[0x32]	2382	1			T9	62		T27	1		T45	10
alert[0x33]	4820	1			T18	2		T50	4		T33	5
alert[0x34]	8665	1			T9	257		T27	4		T75	1
alert[0x35]	6165	1			T9	4		T75	4		T50	786
alert[0x36]	6175	1			T5	3		T28	35		T50	228
alert[0x37]	2695	1			T1	67		T5	2		T15	1
alert[0x38]	7001	1			T9	704		T38	1		T35	7
alert[0x39]	5145	1			T9	27		T27	5		T50	34
alert[0x3a]	12733	1			T26	1		T27	3		T28	32
alert[0x3b]	11004	1			T1	54		T15	1		T28	33
alert[0x3c]	5061	1			T27	1		T18	3		T49	9
alert[0x3d]	2646	1			T47	11		T21	13		T75	1
alert[0x3e]	8706	1			T1	3		T9	27		T28	5
alert[0x3f]	3951	1			T9	4		T27	4		T31	9
alert[0x40]	5313	1			T5	37		T28	3		T75	43

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	74918	1			T5	13		T26	1		T21	8
class_i[0x1]	121692	1			T1	1308		T26	6		T8	1
class_i[0x2]	101403	1			T5	22		T26	3		T9	3
class_i[0x3]	89988	1			T5	118		T9	2398		T15	17

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

387280

1

T1

1308

T5

153

T26

10

alert_ping_fail

721

1

T8

1

T15

17

T16

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6173	1			T5	55		T9	87		T47	2
alert_integrity_fail	alert[0x1]	6340	1			T49	2		T50	1106		T33	24
alert_integrity_fail	alert[0x2]	5917	1			T28	8		T75	3		T49	26
alert_integrity_fail	alert[0x3]	9419	1			T1	47		T75	58		T108	6
alert_integrity_fail	alert[0x4]	6835	1			T5	6		T9	1		T28	33
alert_integrity_fail	alert[0x5]	10707	1			T5	9		T51	3		T33	1
alert_integrity_fail	alert[0x6]	2550	1			T76	1		T242	18		T109	82
alert_integrity_fail	alert[0x7]	3298	1			T9	18		T49	2		T50	2
alert_integrity_fail	alert[0x8]	5105	1			T5	3		T9	8		T31	3
alert_integrity_fail	alert[0x9]	6324	1			T1	206		T28	1		T50	22
alert_integrity_fail	alert[0xa]	3127	1			T1	1		T9	35		T108	1
alert_integrity_fail	alert[0xb]	9539	1			T9	2		T75	17		T50	4
alert_integrity_fail	alert[0xc]	8465	1			T1	33		T45	2		T21	55
alert_integrity_fail	alert[0xd]	7612	1			T26	3		T9	1		T31	1
alert_integrity_fail	alert[0xe]	4502	1			T45	15		T28	143		T49	60
alert_integrity_fail	alert[0xf]	3989	1			T1	8		T49	94		T51	1
alert_integrity_fail	alert[0x10]	5879	1			T1	253		T9	124		T28	1
alert_integrity_fail	alert[0x11]	6427	1			T1	14		T5	5		T9	56
alert_integrity_fail	alert[0x12]	6150	1			T9	11		T45	1		T75	2
alert_integrity_fail	alert[0x13]	7752	1			T27	1		T49	327		T51	1
alert_integrity_fail	alert[0x14]	1550	1			T9	301		T27	2		T21	1
alert_integrity_fail	alert[0x15]	3471	1			T9	1		T45	47		T50	4
alert_integrity_fail	alert[0x16]	6949	1			T5	1		T21	2		T28	29
alert_integrity_fail	alert[0x17]	5273	1			T9	13		T21	1		T28	1
alert_integrity_fail	alert[0x18]	5963	1			T26	1		T21	5		T49	1313
alert_integrity_fail	alert[0x19]	8864	1			T1	4		T9	192		T50	28
alert_integrity_fail	alert[0x1a]	7765	1			T28	2		T75	4		T242	39
alert_integrity_fail	alert[0x1b]	5184	1			T9	26		T27	2		T33	2
alert_integrity_fail	alert[0x1c]	5102	1			T1	145		T5	1		T9	11
alert_integrity_fail	alert[0x1d]	9704	1			T5	2		T21	4		T31	2
alert_integrity_fail	alert[0x1e]	6181	1			T5	20		T9	6		T28	14
alert_integrity_fail	alert[0x1f]	3382	1			T9	12		T49	3		T50	8
alert_integrity_fail	alert[0x20]	4084	1			T1	118		T28	169		T242	157
alert_integrity_fail	alert[0x21]	5962	1			T21	14		T28	16		T31	9
alert_integrity_fail	alert[0x22]	2921	1			T1	51		T5	1		T26	1
alert_integrity_fail	alert[0x23]	15776	1			T108	6		T52	104		T205	12
alert_integrity_fail	alert[0x24]	5395	1			T9	8		T27	18		T45	1
alert_integrity_fail	alert[0x25]	2787	1			T1	82		T9	22		T45	26
alert_integrity_fail	alert[0x26]	6855	1			T1	204		T9	39		T45	1
alert_integrity_fail	alert[0x27]	6562	1			T75	9		T50	73		T76	15
alert_integrity_fail	alert[0x28]	5505	1			T28	3		T51	28		T52	12
alert_integrity_fail	alert[0x29]	4830	1			T27	7		T28	3		T75	5
alert_integrity_fail	alert[0x2a]	2901	1			T75	1		T50	2		T35	28
alert_integrity_fail	alert[0x2b]	5880	1			T9	11		T21	3		T28	3
alert_integrity_fail	alert[0x2c]	7415	1			T33	24		T242	15		T52	16
alert_integrity_fail	alert[0x2d]	6245	1			T35	2		T52	10		T205	419
alert_integrity_fail	alert[0x2e]	5826	1			T5	8		T9	1		T28	31
alert_integrity_fail	alert[0x2f]	2158	1			T26	4		T28	65		T51	2
alert_integrity_fail	alert[0x30]	3199	1			T9	187		T21	3		T28	2
alert_integrity_fail	alert[0x31]	5154	1			T1	18		T9	1		T45	3
alert_integrity_fail	alert[0x32]	2371	1			T9	62		T27	1		T45	10
alert_integrity_fail	alert[0x33]	4807	1			T50	4		T33	5		T52	77
alert_integrity_fail	alert[0x34]	8659	1			T9	257		T27	4		T75	1
alert_integrity_fail	alert[0x35]	6154	1			T9	4		T75	4		T50	786
alert_integrity_fail	alert[0x36]	6170	1			T5	3		T28	35		T50	228
alert_integrity_fail	alert[0x37]	2686	1			T1	67		T5	2		T49	25
alert_integrity_fail	alert[0x38]	6993	1			T9	704		T35	7		T52	13
alert_integrity_fail	alert[0x39]	5136	1			T9	27		T27	5		T50	34
alert_integrity_fail	alert[0x3a]	12722	1			T26	1		T27	3		T28	32
alert_integrity_fail	alert[0x3b]	10994	1			T1	54		T28	33		T75	19
alert_integrity_fail	alert[0x3c]	5048	1			T27	1		T49	9		T35	25
alert_integrity_fail	alert[0x3d]	2636	1			T47	11		T21	13		T75	1
alert_integrity_fail	alert[0x3e]	8694	1			T1	3		T9	27		T28	5
alert_integrity_fail	alert[0x3f]	3947	1			T9	4		T27	4		T31	9
alert_integrity_fail	alert[0x40]	5310	1			T5	37		T28	3		T75	43
alert_ping_fail	alert[0x0]	7	1			T300	1		T301	1		T302	1
alert_ping_fail	alert[0x1]	13	1			T207	1		T209	1		T303	1
alert_ping_fail	alert[0x2]	3	1			T304	1		T301	1		T305	1
alert_ping_fail	alert[0x3]	9	1			T15	1		T18	1		T115	1
alert_ping_fail	alert[0x4]	11	1			T15	1		T38	1		T115	1
alert_ping_fail	alert[0x5]	14	1			T16	1		T241	1		T298	1
alert_ping_fail	alert[0x6]	22	1			T16	1		T72	1		T18	1
alert_ping_fail	alert[0x7]	9	1			T15	1		T299	1		T241	1
alert_ping_fail	alert[0x8]	14	1			T300	1		T249	1		T306	1
alert_ping_fail	alert[0x9]	6	1			T299	1		T115	1		T306	1
alert_ping_fail	alert[0xa]	10	1			T72	1		T38	1		T249	1
alert_ping_fail	alert[0xb]	7	1			T15	1		T300	1		T307	1
alert_ping_fail	alert[0xc]	12	1			T15	1		T17	1		T18	1
alert_ping_fail	alert[0xd]	10	1			T15	1		T209	1		T308	1
alert_ping_fail	alert[0xe]	10	1			T299	1		T301	1		T303	1
alert_ping_fail	alert[0xf]	10	1			T300	1		T309	1		T307	1
alert_ping_fail	alert[0x10]	14	1			T17	1		T38	1		T299	1
alert_ping_fail	alert[0x11]	8	1			T15	2		T310	1		T305	1
alert_ping_fail	alert[0x12]	11	1			T15	1		T241	2		T115	2
alert_ping_fail	alert[0x13]	17	1			T17	2		T38	2		T299	1
alert_ping_fail	alert[0x14]	17	1			T72	1		T299	1		T304	1
alert_ping_fail	alert[0x15]	14	1			T8	1		T72	3		T241	1
alert_ping_fail	alert[0x16]	11	1			T32	1		T299	2		T241	2
alert_ping_fail	alert[0x17]	10	1			T241	2		T311	1		T312	1
alert_ping_fail	alert[0x18]	9	1			T15	1		T241	1		T306	1
alert_ping_fail	alert[0x19]	13	1			T18	1		T299	1		T309	1
alert_ping_fail	alert[0x1a]	14	1			T17	2		T38	2		T241	1
alert_ping_fail	alert[0x1b]	15	1			T241	1		T313	2		T307	1
alert_ping_fail	alert[0x1c]	12	1			T15	1		T241	1		T249	1
alert_ping_fail	alert[0x1d]	13	1			T15	1		T38	1		T241	2
alert_ping_fail	alert[0x1e]	10	1			T18	1		T38	1		T241	2
alert_ping_fail	alert[0x1f]	12	1			T115	1		T84	1		T297	1
alert_ping_fail	alert[0x20]	15	1			T299	1		T300	1		T306	1
alert_ping_fail	alert[0x21]	16	1			T38	1		T207	1		T300	1
alert_ping_fail	alert[0x22]	8	1			T314	1		T310	1		T315	1
alert_ping_fail	alert[0x23]	15	1			T38	1		T209	1		T311	1
alert_ping_fail	alert[0x24]	9	1			T115	2		T304	1		T312	1
alert_ping_fail	alert[0x25]	6	1			T17	1		T299	1		T308	1
alert_ping_fail	alert[0x26]	11	1			T15	1		T115	1		T301	1
alert_ping_fail	alert[0x27]	13	1			T207	1		T300	1		T306	1
alert_ping_fail	alert[0x28]	19	1			T18	1		T299	2		T306	1
alert_ping_fail	alert[0x29]	17	1			T17	1		T249	2		T301	1
alert_ping_fail	alert[0x2a]	9	1			T299	1		T316	1		T317	1
alert_ping_fail	alert[0x2b]	5	1			T318	1		T302	1		T319	1
alert_ping_fail	alert[0x2c]	12	1			T69	1		T304	1		T320	1
alert_ping_fail	alert[0x2d]	10	1			T15	1		T38	1		T299	1
alert_ping_fail	alert[0x2e]	13	1			T304	1		T303	1		T309	2
alert_ping_fail	alert[0x2f]	14	1			T17	1		T38	1		T304	2
alert_ping_fail	alert[0x30]	8	1			T15	1		T300	1		T321	1
alert_ping_fail	alert[0x31]	19	1			T18	1		T299	2		T115	1
alert_ping_fail	alert[0x32]	11	1			T18	1		T38	1		T311	1
alert_ping_fail	alert[0x33]	13	1			T18	2		T241	1		T115	1
alert_ping_fail	alert[0x34]	6	1			T304	1		T309	1		T307	1
alert_ping_fail	alert[0x35]	11	1			T38	1		T309	1		T312	1
alert_ping_fail	alert[0x36]	5	1			T115	1		T304	1		T301	1
alert_ping_fail	alert[0x37]	9	1			T15	1		T300	1		T311	2
alert_ping_fail	alert[0x38]	8	1			T38	1		T309	1		T311	1
alert_ping_fail	alert[0x39]	9	1			T304	1		T310	1		T317	1
alert_ping_fail	alert[0x3a]	11	1			T38	1		T303	1		T312	1
alert_ping_fail	alert[0x3b]	10	1			T15	1		T300	1		T301	1
alert_ping_fail	alert[0x3c]	13	1			T18	3		T241	1		T207	1
alert_ping_fail	alert[0x3d]	10	1			T38	2		T299	1		T301	2
alert_ping_fail	alert[0x3e]	12	1			T18	2		T38	1		T241	1
alert_ping_fail	alert[0x3f]	4	1			T299	1		T316	1		T322	1
alert_ping_fail	alert[0x40]	3	1			T299	1		T318	1		T323	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	74736	1			T5	13		T26	1		T21	8
alert_integrity_fail	class_i[0x1]	121519	1			T1	1308		T26	6		T9	2
alert_integrity_fail	class_i[0x2]	101165	1			T5	22		T26	3		T9	3
alert_integrity_fail	class_i[0x3]	89860	1			T5	118		T9	2398		T28	16
alert_ping_fail	class_i[0x0]	182	1			T69	1		T18	1		T241	21
alert_ping_fail	class_i[0x1]	173	1			T8	1		T17	9		T18	1
alert_ping_fail	class_i[0x2]	238	1			T16	2		T72	6		T18	13
alert_ping_fail	class_i[0x3]	128	1			T15	17		T32	1		T299	19