Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.99 98.70 91.98 100.00 100.00 99.38 99.60


Total test records in report: 830
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T773 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3367679103 Mar 10 01:08:20 PM PDT 24 Mar 10 01:08:42 PM PDT 24 1029798153 ps
T186 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3727373209 Mar 10 01:08:19 PM PDT 24 Mar 10 01:08:22 PM PDT 24 61704228 ps
T774 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3480116804 Mar 10 01:08:38 PM PDT 24 Mar 10 01:08:39 PM PDT 24 17405374 ps
T775 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4083107017 Mar 10 01:08:04 PM PDT 24 Mar 10 01:08:09 PM PDT 24 207301861 ps
T150 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1572325866 Mar 10 01:08:21 PM PDT 24 Mar 10 01:11:57 PM PDT 24 1632841737 ps
T776 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3793038920 Mar 10 01:08:37 PM PDT 24 Mar 10 01:08:40 PM PDT 24 17536110 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3238817192 Mar 10 01:08:20 PM PDT 24 Mar 10 01:08:24 PM PDT 24 8680206 ps
T778 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4082701417 Mar 10 01:08:00 PM PDT 24 Mar 10 01:08:09 PM PDT 24 113823537 ps
T779 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1969540993 Mar 10 01:08:20 PM PDT 24 Mar 10 01:08:27 PM PDT 24 135956901 ps
T780 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3467926678 Mar 10 01:08:14 PM PDT 24 Mar 10 01:08:20 PM PDT 24 128110713 ps
T781 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.877476884 Mar 10 01:08:36 PM PDT 24 Mar 10 01:08:39 PM PDT 24 11025047 ps
T782 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3194963238 Mar 10 01:08:11 PM PDT 24 Mar 10 01:08:27 PM PDT 24 497458758 ps
T158 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2359331747 Mar 10 01:08:14 PM PDT 24 Mar 10 01:13:36 PM PDT 24 4493810809 ps
T783 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3867484021 Mar 10 01:08:11 PM PDT 24 Mar 10 01:08:15 PM PDT 24 20864242 ps
T784 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3657692493 Mar 10 01:08:08 PM PDT 24 Mar 10 01:08:17 PM PDT 24 870398824 ps
T155 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3495313222 Mar 10 01:07:58 PM PDT 24 Mar 10 01:09:50 PM PDT 24 3716198247 ps
T785 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.142708744 Mar 10 01:08:32 PM PDT 24 Mar 10 01:08:34 PM PDT 24 6616050 ps
T786 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1547514921 Mar 10 01:08:03 PM PDT 24 Mar 10 01:08:15 PM PDT 24 425911029 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2058470730 Mar 10 01:08:05 PM PDT 24 Mar 10 01:08:11 PM PDT 24 288515146 ps
T161 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.874235432 Mar 10 01:08:27 PM PDT 24 Mar 10 01:10:15 PM PDT 24 2525714810 ps
T153 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3383492715 Mar 10 01:08:27 PM PDT 24 Mar 10 01:10:15 PM PDT 24 3865895425 ps
T788 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2217591456 Mar 10 01:08:33 PM PDT 24 Mar 10 01:08:37 PM PDT 24 9810838 ps
T789 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2678922016 Mar 10 01:08:33 PM PDT 24 Mar 10 01:09:32 PM PDT 24 1389441519 ps
T790 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.235020627 Mar 10 01:08:37 PM PDT 24 Mar 10 01:08:40 PM PDT 24 9896828 ps
T791 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2485224036 Mar 10 01:08:06 PM PDT 24 Mar 10 01:08:08 PM PDT 24 9692518 ps
T180 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3024579050 Mar 10 01:08:06 PM PDT 24 Mar 10 01:09:33 PM PDT 24 2375371604 ps
T146 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1418499588 Mar 10 01:08:26 PM PDT 24 Mar 10 01:27:03 PM PDT 24 15460762214 ps
T792 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4264088294 Mar 10 01:08:07 PM PDT 24 Mar 10 01:08:12 PM PDT 24 252575616 ps
T793 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3410730110 Mar 10 01:08:26 PM PDT 24 Mar 10 01:08:34 PM PDT 24 360816091 ps
T794 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1225970965 Mar 10 01:08:16 PM PDT 24 Mar 10 01:08:25 PM PDT 24 97392706 ps
T795 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3743303075 Mar 10 01:08:27 PM PDT 24 Mar 10 01:08:29 PM PDT 24 9547681 ps
T151 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2571406461 Mar 10 01:08:14 PM PDT 24 Mar 10 01:11:54 PM PDT 24 6537466956 ps
T796 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2216644581 Mar 10 01:07:59 PM PDT 24 Mar 10 01:08:04 PM PDT 24 112564634 ps
T797 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3685699618 Mar 10 01:08:26 PM PDT 24 Mar 10 01:08:31 PM PDT 24 181529483 ps
T162 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3430519490 Mar 10 01:08:25 PM PDT 24 Mar 10 01:13:42 PM PDT 24 15650929388 ps
T798 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1648594037 Mar 10 01:08:17 PM PDT 24 Mar 10 01:08:33 PM PDT 24 3760083653 ps
T799 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3436479708 Mar 10 01:08:36 PM PDT 24 Mar 10 01:08:40 PM PDT 24 7445235 ps
T800 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2207868260 Mar 10 01:08:01 PM PDT 24 Mar 10 01:08:11 PM PDT 24 421532810 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1388138353 Mar 10 01:07:58 PM PDT 24 Mar 10 01:08:49 PM PDT 24 2862742986 ps
T175 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4105475496 Mar 10 01:08:27 PM PDT 24 Mar 10 01:09:06 PM PDT 24 901450845 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1556076605 Mar 10 01:08:13 PM PDT 24 Mar 10 01:19:40 PM PDT 24 4481990947 ps
T802 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.657960311 Mar 10 01:08:26 PM PDT 24 Mar 10 01:08:33 PM PDT 24 305644157 ps
T165 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1906176687 Mar 10 01:08:21 PM PDT 24 Mar 10 01:15:45 PM PDT 24 6572354573 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1927236652 Mar 10 01:08:28 PM PDT 24 Mar 10 01:08:30 PM PDT 24 8004190 ps
T804 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.186955247 Mar 10 01:08:09 PM PDT 24 Mar 10 01:08:20 PM PDT 24 242280372 ps
T805 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1860380410 Mar 10 01:08:35 PM PDT 24 Mar 10 01:08:37 PM PDT 24 18751372 ps
T806 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1713897690 Mar 10 01:08:10 PM PDT 24 Mar 10 01:08:30 PM PDT 24 615295332 ps
T807 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1830052766 Mar 10 01:08:24 PM PDT 24 Mar 10 01:08:44 PM PDT 24 256188019 ps
T808 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3059938309 Mar 10 01:08:12 PM PDT 24 Mar 10 01:08:20 PM PDT 24 147071152 ps
T809 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.7558017 Mar 10 01:08:34 PM PDT 24 Mar 10 01:08:37 PM PDT 24 9250369 ps
T167 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2746941400 Mar 10 01:08:01 PM PDT 24 Mar 10 01:13:26 PM PDT 24 2153305396 ps
T157 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.964432071 Mar 10 01:08:28 PM PDT 24 Mar 10 01:24:54 PM PDT 24 125818369618 ps
T810 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3294769407 Mar 10 01:08:25 PM PDT 24 Mar 10 01:08:41 PM PDT 24 776670396 ps
T811 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.430627901 Mar 10 01:08:11 PM PDT 24 Mar 10 01:11:08 PM PDT 24 2437258272 ps
T812 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2555128134 Mar 10 01:08:35 PM PDT 24 Mar 10 01:08:37 PM PDT 24 6340812 ps
T813 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.918351751 Mar 10 01:08:34 PM PDT 24 Mar 10 01:08:37 PM PDT 24 17453159 ps
T349 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3959765702 Mar 10 01:08:36 PM PDT 24 Mar 10 01:18:54 PM PDT 24 37840452803 ps
T163 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2118068328 Mar 10 01:08:07 PM PDT 24 Mar 10 01:11:08 PM PDT 24 2703154382 ps
T164 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3940950790 Mar 10 01:08:09 PM PDT 24 Mar 10 01:19:03 PM PDT 24 4846875846 ps
T814 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1119992513 Mar 10 01:08:25 PM PDT 24 Mar 10 01:08:27 PM PDT 24 10735754 ps
T190 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3971511336 Mar 10 01:08:07 PM PDT 24 Mar 10 01:08:43 PM PDT 24 5528871602 ps
T815 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1572526974 Mar 10 01:07:57 PM PDT 24 Mar 10 01:08:21 PM PDT 24 1075708369 ps
T816 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1445343366 Mar 10 01:08:19 PM PDT 24 Mar 10 01:08:26 PM PDT 24 140625799 ps
T817 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.419817810 Mar 10 01:08:27 PM PDT 24 Mar 10 01:08:51 PM PDT 24 183407906 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3229596989 Mar 10 01:08:10 PM PDT 24 Mar 10 01:08:51 PM PDT 24 505614150 ps
T819 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.278925025 Mar 10 01:08:34 PM PDT 24 Mar 10 01:08:36 PM PDT 24 9448060 ps
T820 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3582010324 Mar 10 01:08:00 PM PDT 24 Mar 10 01:08:02 PM PDT 24 6510917 ps
T821 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1872386016 Mar 10 01:08:26 PM PDT 24 Mar 10 01:09:01 PM PDT 24 499853305 ps
T822 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3775927094 Mar 10 01:08:21 PM PDT 24 Mar 10 01:17:54 PM PDT 24 8244056336 ps
T166 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3313304075 Mar 10 01:08:08 PM PDT 24 Mar 10 01:11:41 PM PDT 24 1703631933 ps
T823 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1799503965 Mar 10 01:08:26 PM PDT 24 Mar 10 01:08:28 PM PDT 24 9943370 ps
T824 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.688163899 Mar 10 01:07:57 PM PDT 24 Mar 10 01:08:04 PM PDT 24 142996088 ps
T179 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2233276150 Mar 10 01:08:02 PM PDT 24 Mar 10 01:08:27 PM PDT 24 609508774 ps
T825 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1414975972 Mar 10 01:08:07 PM PDT 24 Mar 10 01:08:19 PM PDT 24 128792039 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2292037850 Mar 10 01:08:06 PM PDT 24 Mar 10 01:08:24 PM PDT 24 719910129 ps
T827 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2613795320 Mar 10 01:07:57 PM PDT 24 Mar 10 01:08:08 PM PDT 24 264798849 ps
T828 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3215950294 Mar 10 01:08:08 PM PDT 24 Mar 10 01:08:20 PM PDT 24 64646178 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4165096232 Mar 10 01:08:28 PM PDT 24 Mar 10 01:08:35 PM PDT 24 58466292 ps
T177 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.85953706 Mar 10 01:08:08 PM PDT 24 Mar 10 01:08:13 PM PDT 24 208385995 ps
T830 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1220485233 Mar 10 01:08:14 PM PDT 24 Mar 10 01:08:19 PM PDT 24 70294948 ps

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.473064609
Short name T5
Test name
Test status
Simulation time 224041477884 ps
CPU time 4847.13 seconds
Started Mar 10 01:28:13 PM PDT 24
Finished Mar 10 02:49:01 PM PDT 24
Peak memory 306248 kb
Host smart-b47c70a4-a28d-424f-80b5-abcf03f3bb6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473064609 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.473064609
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2686244654
Short name T28
Test name
Test status
Simulation time 229488331427 ps
CPU time 4436.1 seconds
Started Mar 10 01:28:58 PM PDT 24
Finished Mar 10 02:42:55 PM PDT 24
Peak memory 305920 kb
Host smart-5fc232bb-16dc-40ac-9c4a-0f7a7ca3ee12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686244654 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2686244654
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.439854909
Short name T21
Test name
Test status
Simulation time 146212939990 ps
CPU time 2878.68 seconds
Started Mar 10 01:28:07 PM PDT 24
Finished Mar 10 02:16:06 PM PDT 24
Peak memory 289876 kb
Host smart-fec0a0dc-80ed-4bbe-bfdd-63749c99ce15
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439854909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.439854909
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1246751736
Short name T6
Test name
Test status
Simulation time 447430803 ps
CPU time 14.02 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:31 PM PDT 24
Peak memory 273616 kb
Host smart-34814215-7c83-4e05-85e3-9c20b8b49aae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1246751736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1246751736
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2175373178
Short name T174
Test name
Test status
Simulation time 1877442741 ps
CPU time 58.05 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:09:24 PM PDT 24
Peak memory 240356 kb
Host smart-06947e3b-ed7a-4136-b32a-3092e2564183
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2175373178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2175373178
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.4116509573
Short name T31
Test name
Test status
Simulation time 84025483772 ps
CPU time 2711.08 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 02:11:32 PM PDT 24
Peak memory 297508 kb
Host smart-316159c3-6f0a-4c58-89f9-40fde21d79f1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116509573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.4116509573
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2798815325
Short name T1
Test name
Test status
Simulation time 182401337326 ps
CPU time 2400.23 seconds
Started Mar 10 01:27:16 PM PDT 24
Finished Mar 10 02:07:18 PM PDT 24
Peak memory 284816 kb
Host smart-56028a4d-3ee5-48c5-9262-31abaa259502
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798815325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2798815325
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.799419791
Short name T131
Test name
Test status
Simulation time 15892393011 ps
CPU time 1153.08 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:27:47 PM PDT 24
Peak memory 265064 kb
Host smart-d5d8077d-9f54-444c-916d-34db255bb761
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799419791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.799419791
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.1113910644
Short name T32
Test name
Test status
Simulation time 34378502530 ps
CPU time 2233.51 seconds
Started Mar 10 01:26:09 PM PDT 24
Finished Mar 10 02:03:24 PM PDT 24
Peak memory 286568 kb
Host smart-e999b8d7-fccb-4091-ba91-aacf51bbb973
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113910644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.1113910644
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2474573105
Short name T61
Test name
Test status
Simulation time 140339646640 ps
CPU time 3206.52 seconds
Started Mar 10 01:27:49 PM PDT 24
Finished Mar 10 02:21:16 PM PDT 24
Peak memory 321920 kb
Host smart-b6f7d2ad-b6d5-4644-9282-2e022e15dc07
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474573105 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2474573105
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.356312063
Short name T90
Test name
Test status
Simulation time 28351248627 ps
CPU time 1110.65 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:44:51 PM PDT 24
Peak memory 284456 kb
Host smart-5bb3a337-4280-4963-b2ea-b3fbdc111ea7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356312063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.356312063
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3169315293
Short name T141
Test name
Test status
Simulation time 8368110570 ps
CPU time 323.24 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:13:28 PM PDT 24
Peak memory 265124 kb
Host smart-b15235be-2268-4fdd-bd70-f6d4d0d8ada9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3169315293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3169315293
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.4231447077
Short name T38
Test name
Test status
Simulation time 15815294900 ps
CPU time 649.82 seconds
Started Mar 10 01:25:59 PM PDT 24
Finished Mar 10 01:36:50 PM PDT 24
Peak memory 247224 kb
Host smart-bda0bf36-9d22-4778-b64e-6ed4c03ddca3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231447077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.4231447077
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3800081586
Short name T144
Test name
Test status
Simulation time 65331220952 ps
CPU time 1197.95 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:28:17 PM PDT 24
Peak memory 272192 kb
Host smart-66a4448f-26a0-482b-9ce6-b59f75ad4cdd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800081586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3800081586
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2770616921
Short name T35
Test name
Test status
Simulation time 54088059814 ps
CPU time 897.14 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:41:15 PM PDT 24
Peak memory 271868 kb
Host smart-b9d32e20-7ddb-4db3-bdbe-fd1a84eb73c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770616921 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2770616921
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1097577392
Short name T34
Test name
Test status
Simulation time 11295380216 ps
CPU time 938.73 seconds
Started Mar 10 01:27:26 PM PDT 24
Finished Mar 10 01:43:05 PM PDT 24
Peak memory 272980 kb
Host smart-bf8be3ee-771b-4ae4-a2be-f2888b1e3f40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097577392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1097577392
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2148252929
Short name T19
Test name
Test status
Simulation time 489657353 ps
CPU time 11.5 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:26:40 PM PDT 24
Peak memory 240776 kb
Host smart-dcd35587-d36b-43e5-88b5-787c92969a75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2148252929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2148252929
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1048518973
Short name T142
Test name
Test status
Simulation time 6066634687 ps
CPU time 230.48 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:12:23 PM PDT 24
Peak memory 265312 kb
Host smart-c0919f17-f0c1-4060-b1cc-d0ed895da83f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1048518973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1048518973
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2303877876
Short name T52
Test name
Test status
Simulation time 375743527582 ps
CPU time 9911.76 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 04:11:45 PM PDT 24
Peak memory 389628 kb
Host smart-21d47d24-34d1-4b65-b878-31c24956febf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303877876 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2303877876
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3364303835
Short name T250
Test name
Test status
Simulation time 24510051 ps
CPU time 1.55 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 236296 kb
Host smart-b6bdc466-ce3a-4dc0-ae5a-499c1f29874a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3364303835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3364303835
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1061410927
Short name T133
Test name
Test status
Simulation time 4418232159 ps
CPU time 545.91 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:17:13 PM PDT 24
Peak memory 266212 kb
Host smart-2533cd92-addc-4883-883c-7143af46b02c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061410927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1061410927
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3781285
Short name T84
Test name
Test status
Simulation time 24693403806 ps
CPU time 1469.11 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:50:45 PM PDT 24
Peak memory 272996 kb
Host smart-ee06bff1-41e8-4735-b7f0-ab77c62bafd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3781285
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1140362083
Short name T241
Test name
Test status
Simulation time 24211441701 ps
CPU time 564.48 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:35:44 PM PDT 24
Peak memory 247976 kb
Host smart-d92e3876-fcab-449e-9a4a-019c7e1f8859
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140362083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1140362083
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1556076605
Short name T159
Test name
Test status
Simulation time 4481990947 ps
CPU time 686.11 seconds
Started Mar 10 01:08:13 PM PDT 24
Finished Mar 10 01:19:40 PM PDT 24
Peak memory 265260 kb
Host smart-257ae12c-fd35-4501-be55-aadd90f541a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556076605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1556076605
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1353803027
Short name T313
Test name
Test status
Simulation time 51566840624 ps
CPU time 2983.5 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 02:17:13 PM PDT 24
Peak memory 288456 kb
Host smart-ece4cf7b-1711-4a04-8730-0bdd88ddf33c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353803027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1353803027
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.536425744
Short name T91
Test name
Test status
Simulation time 118849659839 ps
CPU time 3305.56 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 02:22:13 PM PDT 24
Peak memory 322436 kb
Host smart-76b30bdf-905f-4e8d-af15-14b89ddeeb18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536425744 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.536425744
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.11677532
Short name T138
Test name
Test status
Simulation time 13196377428 ps
CPU time 1008.74 seconds
Started Mar 10 01:08:12 PM PDT 24
Finished Mar 10 01:25:01 PM PDT 24
Peak memory 272672 kb
Host smart-39c6f61d-a284-4e0d-bb25-589debb64089
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11677532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.11677532
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1467661785
Short name T300
Test name
Test status
Simulation time 18168919630 ps
CPU time 441.6 seconds
Started Mar 10 01:27:58 PM PDT 24
Finished Mar 10 01:35:20 PM PDT 24
Peak memory 247792 kb
Host smart-4df312f9-22ea-4536-ab3d-0ab8f610092f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467661785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1467661785
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1572325866
Short name T150
Test name
Test status
Simulation time 1632841737 ps
CPU time 215.05 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:11:57 PM PDT 24
Peak memory 265044 kb
Host smart-61bd6dfa-a28e-44f1-bed5-6a5c184bb935
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1572325866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1572325866
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.4053386947
Short name T94
Test name
Test status
Simulation time 37667301197 ps
CPU time 2615.03 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 02:10:42 PM PDT 24
Peak memory 289448 kb
Host smart-9cb3d20d-75cb-42be-a179-dbb57301f278
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053386947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.4053386947
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.2580788487
Short name T330
Test name
Test status
Simulation time 250618284121 ps
CPU time 1544.58 seconds
Started Mar 10 01:28:53 PM PDT 24
Finished Mar 10 01:54:38 PM PDT 24
Peak memory 270760 kb
Host smart-3231d40e-4615-4daf-87cf-158a860700c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580788487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2580788487
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.624667798
Short name T115
Test name
Test status
Simulation time 7686686325 ps
CPU time 318.91 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:32:01 PM PDT 24
Peak memory 247956 kb
Host smart-795ebc66-8809-4642-a36a-1485de443830
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624667798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.624667798
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.467023727
Short name T297
Test name
Test status
Simulation time 30787388738 ps
CPU time 1750.88 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 01:56:50 PM PDT 24
Peak memory 268540 kb
Host smart-01beae9a-1ee0-4704-a636-9b159ff121d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467023727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.467023727
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2557780337
Short name T50
Test name
Test status
Simulation time 294018180908 ps
CPU time 3248.72 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 02:20:53 PM PDT 24
Peak memory 306440 kb
Host smart-1130c0d6-dcf3-4927-99b2-9ab2d1f4a25c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557780337 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2557780337
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1154748871
Short name T345
Test name
Test status
Simulation time 25480717 ps
CPU time 1.37 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 236364 kb
Host smart-85ddf00f-768d-481c-b83a-d8fba828d56b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1154748871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1154748871
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3511930161
Short name T305
Test name
Test status
Simulation time 144127082586 ps
CPU time 652.34 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 01:37:25 PM PDT 24
Peak memory 247836 kb
Host smart-d5c88770-df74-40a4-b9f2-7bf1439c0102
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511930161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3511930161
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3875529180
Short name T255
Test name
Test status
Simulation time 133367397625 ps
CPU time 2085.39 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 02:02:04 PM PDT 24
Peak memory 288056 kb
Host smart-5fa06941-655c-4bf3-ba90-f41c12f7dfdb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875529180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3875529180
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3940950790
Short name T164
Test name
Test status
Simulation time 4846875846 ps
CPU time 653.69 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:19:03 PM PDT 24
Peak memory 265364 kb
Host smart-4d4c2ea6-cbb3-484d-bf04-22cb84a42d3f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940950790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3940950790
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2568007275
Short name T75
Test name
Test status
Simulation time 64994985354 ps
CPU time 2146.58 seconds
Started Mar 10 01:27:41 PM PDT 24
Finished Mar 10 02:03:27 PM PDT 24
Peak memory 289312 kb
Host smart-9b04f719-175c-4f86-8219-238a8a5bbe94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568007275 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2568007275
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.613001430
Short name T314
Test name
Test status
Simulation time 855737446958 ps
CPU time 2693.5 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 02:11:17 PM PDT 24
Peak memory 289388 kb
Host smart-ff4ffc68-83c2-4efd-9dc2-b25966ad36fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613001430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.613001430
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1248273841
Short name T276
Test name
Test status
Simulation time 13154378047 ps
CPU time 1402.18 seconds
Started Mar 10 01:26:36 PM PDT 24
Finished Mar 10 01:49:58 PM PDT 24
Peak memory 289296 kb
Host smart-10d3937c-c873-4a48-a341-3f50ff3178dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248273841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1248273841
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3695663848
Short name T33
Test name
Test status
Simulation time 4222820257 ps
CPU time 246.31 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:30:34 PM PDT 24
Peak memory 257228 kb
Host smart-d6b33b19-89cb-4501-8fbb-dcd533a60d0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695663848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3695663848
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3987241057
Short name T315
Test name
Test status
Simulation time 45999962189 ps
CPU time 515.04 seconds
Started Mar 10 01:27:38 PM PDT 24
Finished Mar 10 01:36:14 PM PDT 24
Peak memory 249056 kb
Host smart-e79ce00f-fe64-4e39-8ff7-242d7179b1b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987241057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3987241057
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.537040554
Short name T148
Test name
Test status
Simulation time 2708350414 ps
CPU time 167.47 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:10:54 PM PDT 24
Peak memory 256912 kb
Host smart-3e47ca06-1ce0-494e-81f5-5d72eef80f92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=537040554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.537040554
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2394900409
Short name T182
Test name
Test status
Simulation time 44731758 ps
CPU time 3.22 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:08:06 PM PDT 24
Peak memory 237376 kb
Host smart-c8b5abfd-65bf-4cb6-9a0d-a53e8c62b553
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2394900409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2394900409
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1906176687
Short name T165
Test name
Test status
Simulation time 6572354573 ps
CPU time 442.49 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:15:45 PM PDT 24
Peak memory 265084 kb
Host smart-0fc2634d-5d32-47a8-934a-ca2507c17f40
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906176687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1906176687
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2765473129
Short name T326
Test name
Test status
Simulation time 353834654720 ps
CPU time 2891.99 seconds
Started Mar 10 01:26:00 PM PDT 24
Finished Mar 10 02:14:12 PM PDT 24
Peak memory 286328 kb
Host smart-1939874f-b31b-4ce0-bd7d-daeadb5d4fbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765473129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2765473129
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2242940602
Short name T304
Test name
Test status
Simulation time 53541862176 ps
CPU time 569.32 seconds
Started Mar 10 01:26:15 PM PDT 24
Finished Mar 10 01:35:45 PM PDT 24
Peak memory 247844 kb
Host smart-048ab67a-298d-46b9-aec8-a2fba4acc980
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242940602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2242940602
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2679438902
Short name T45
Test name
Test status
Simulation time 746667248 ps
CPU time 46 seconds
Started Mar 10 01:28:52 PM PDT 24
Finished Mar 10 01:29:39 PM PDT 24
Peak memory 247524 kb
Host smart-6ca3d641-fc5b-4b1b-9e46-8ca12eb5e029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
38902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2679438902
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2052912043
Short name T140
Test name
Test status
Simulation time 14967072728 ps
CPU time 1150.02 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:27:20 PM PDT 24
Peak memory 265180 kb
Host smart-700e8f61-5447-48ac-90e8-b881ad7a1148
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052912043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2052912043
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1641944507
Short name T232
Test name
Test status
Simulation time 36284956 ps
CPU time 2.45 seconds
Started Mar 10 01:26:02 PM PDT 24
Finished Mar 10 01:26:06 PM PDT 24
Peak memory 249176 kb
Host smart-012c7458-29ef-4bb4-b1c5-edcefb5a4ff6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1641944507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1641944507
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.186958528
Short name T221
Test name
Test status
Simulation time 117933284 ps
CPU time 2.49 seconds
Started Mar 10 01:25:58 PM PDT 24
Finished Mar 10 01:26:01 PM PDT 24
Peak memory 249168 kb
Host smart-da90d68e-39f7-4c81-9db3-88a2fd5ca0f4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=186958528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.186958528
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.4120322434
Short name T223
Test name
Test status
Simulation time 33900182 ps
CPU time 3.27 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:27 PM PDT 24
Peak memory 249168 kb
Host smart-f820b9aa-c71e-4fe3-8fdc-e7d65cb6bc64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4120322434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.4120322434
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1505084965
Short name T228
Test name
Test status
Simulation time 39016606 ps
CPU time 2.66 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:34 PM PDT 24
Peak memory 249168 kb
Host smart-a430ba10-56b5-4672-aaac-79059ddc93f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1505084965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1505084965
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.911653040
Short name T272
Test name
Test status
Simulation time 130694856234 ps
CPU time 2610.17 seconds
Started Mar 10 01:26:29 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 289548 kb
Host smart-93e42746-72c5-44aa-8368-ffc16cbae215
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911653040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.911653040
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2271470442
Short name T294
Test name
Test status
Simulation time 34303181006 ps
CPU time 2060.86 seconds
Started Mar 10 01:27:01 PM PDT 24
Finished Mar 10 02:01:22 PM PDT 24
Peak memory 273596 kb
Host smart-1c65ef58-bbfc-4ac0-92ef-30c7071f9b84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271470442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2271470442
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.76426643
Short name T120
Test name
Test status
Simulation time 108363253847 ps
CPU time 1939.04 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 01:59:47 PM PDT 24
Peak memory 283292 kb
Host smart-c2f6f817-01af-4f2b-a410-f4abb556a35e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76426643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_hand
ler_stress_all.76426643
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2844668576
Short name T299
Test name
Test status
Simulation time 11428030466 ps
CPU time 472.41 seconds
Started Mar 10 01:28:18 PM PDT 24
Finished Mar 10 01:36:11 PM PDT 24
Peak memory 255112 kb
Host smart-290e37d1-2e3d-42b4-a2cb-bdf751085220
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844668576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2844668576
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2546739614
Short name T98
Test name
Test status
Simulation time 80109920266 ps
CPU time 2496.19 seconds
Started Mar 10 01:28:23 PM PDT 24
Finished Mar 10 02:09:59 PM PDT 24
Peak memory 289264 kb
Host smart-969cfb7a-9eca-4878-b72d-7da517e96ef1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546739614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2546739614
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2769989735
Short name T57
Test name
Test status
Simulation time 269267783825 ps
CPU time 4189.87 seconds
Started Mar 10 01:26:15 PM PDT 24
Finished Mar 10 02:36:06 PM PDT 24
Peak memory 298256 kb
Host smart-bb7823c4-d4bc-4f91-9686-0ca5cc5cd4fa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769989735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2769989735
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2456683316
Short name T12
Test name
Test status
Simulation time 57941522659 ps
CPU time 1203.27 seconds
Started Mar 10 01:26:25 PM PDT 24
Finished Mar 10 01:46:28 PM PDT 24
Peak memory 286928 kb
Host smart-c426fb02-9a8d-4439-bab2-f21d90c7950a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456683316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2456683316
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.650512221
Short name T273
Test name
Test status
Simulation time 17154845355 ps
CPU time 1937.77 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:58:42 PM PDT 24
Peak memory 297964 kb
Host smart-e6e0fd1d-5813-4d93-8a63-a433a3d1231f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650512221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.650512221
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.4014996305
Short name T135
Test name
Test status
Simulation time 35185102180 ps
CPU time 630.15 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:18:27 PM PDT 24
Peak memory 265168 kb
Host smart-2a040c3c-32b0-4251-a2b8-e4bb5dcb2ded
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014996305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.4014996305
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1868915036
Short name T185
Test name
Test status
Simulation time 481645844 ps
CPU time 33.86 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:08:59 PM PDT 24
Peak memory 236832 kb
Host smart-1102332f-52cf-4bde-b89a-7d537924411d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1868915036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1868915036
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.380565661
Short name T736
Test name
Test status
Simulation time 16357093 ps
CPU time 1.82 seconds
Started Mar 10 01:08:00 PM PDT 24
Finished Mar 10 01:08:02 PM PDT 24
Peak memory 235380 kb
Host smart-1c8dea93-9448-4141-bf64-d80d72c34094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=380565661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.380565661
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2338084809
Short name T292
Test name
Test status
Simulation time 18040820030 ps
CPU time 1641.78 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:53:28 PM PDT 24
Peak memory 288996 kb
Host smart-f767ba99-aa95-4a5d-b549-05a665fa74d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338084809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2338084809
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.417879482
Short name T586
Test name
Test status
Simulation time 24717458738 ps
CPU time 891.24 seconds
Started Mar 10 01:25:55 PM PDT 24
Finished Mar 10 01:40:47 PM PDT 24
Peak memory 272740 kb
Host smart-341ae2bd-093b-431f-bdf7-1e13043daeaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417879482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.417879482
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2412131255
Short name T80
Test name
Test status
Simulation time 270674066 ps
CPU time 33.85 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:55 PM PDT 24
Peak memory 255440 kb
Host smart-9bc4ae63-cdc4-40b9-a2d8-23aab44fd1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121
31255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2412131255
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3026982186
Short name T278
Test name
Test status
Simulation time 24943996142 ps
CPU time 1481.19 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:51:15 PM PDT 24
Peak memory 272440 kb
Host smart-e6f86d0a-273d-40ea-b57d-8d4bae6bdebe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026982186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3026982186
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3142185329
Short name T277
Test name
Test status
Simulation time 19006350407 ps
CPU time 1555.86 seconds
Started Mar 10 01:26:41 PM PDT 24
Finished Mar 10 01:52:37 PM PDT 24
Peak memory 289468 kb
Host smart-dd13596a-bca4-4bb6-be68-16d19f945631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142185329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3142185329
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4083971674
Short name T119
Test name
Test status
Simulation time 968986095 ps
CPU time 15.82 seconds
Started Mar 10 01:26:29 PM PDT 24
Finished Mar 10 01:26:45 PM PDT 24
Peak memory 254360 kb
Host smart-90c4455d-cf8e-49e2-b134-bd61cf65a5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40839
71674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4083971674
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4113772748
Short name T26
Test name
Test status
Simulation time 881069124 ps
CPU time 53.32 seconds
Started Mar 10 01:26:47 PM PDT 24
Finished Mar 10 01:27:40 PM PDT 24
Peak memory 255284 kb
Host smart-456ee120-86a6-400c-bc43-c119cfc3a381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41137
72748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4113772748
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3744393465
Short name T267
Test name
Test status
Simulation time 81781748988 ps
CPU time 2188.82 seconds
Started Mar 10 01:26:54 PM PDT 24
Finished Mar 10 02:03:24 PM PDT 24
Peak memory 304960 kb
Host smart-8338c743-5cee-4937-9758-66c6d59f6395
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744393465 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3744393465
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.402791382
Short name T293
Test name
Test status
Simulation time 9824739264 ps
CPU time 982.95 seconds
Started Mar 10 01:26:59 PM PDT 24
Finished Mar 10 01:43:23 PM PDT 24
Peak memory 271432 kb
Host smart-3c8efaa7-b25f-4063-9cae-d0118e19fe7f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402791382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_han
dler_stress_all.402791382
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.256547407
Short name T81
Test name
Test status
Simulation time 228683811 ps
CPU time 30.79 seconds
Started Mar 10 01:27:02 PM PDT 24
Finished Mar 10 01:27:33 PM PDT 24
Peak memory 249020 kb
Host smart-a4a232fa-7a8d-4164-b132-6ca46b1ee94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25654
7407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.256547407
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1154993786
Short name T287
Test name
Test status
Simulation time 3454914457 ps
CPU time 54.64 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 01:28:14 PM PDT 24
Peak memory 255236 kb
Host smart-04fc9c5a-bc4d-47ef-848d-7799d317d4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11549
93786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1154993786
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3442946694
Short name T96
Test name
Test status
Simulation time 28633548507 ps
CPU time 773.58 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:39:18 PM PDT 24
Peak memory 272640 kb
Host smart-03934a84-567c-429f-8e6e-faff5365e577
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442946694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3442946694
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3837059421
Short name T416
Test name
Test status
Simulation time 1022690384 ps
CPU time 24.97 seconds
Started Mar 10 01:25:58 PM PDT 24
Finished Mar 10 01:26:24 PM PDT 24
Peak memory 247500 kb
Host smart-fa4fd3fe-56a8-444c-b305-4168d72ed848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38370
59421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3837059421
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.1416737181
Short name T137
Test name
Test status
Simulation time 19210355441 ps
CPU time 685.79 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:19:34 PM PDT 24
Peak memory 273300 kb
Host smart-f91f48d0-9c96-4775-8ee6-9df1410a95ed
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416737181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.1416737181
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1636834863
Short name T136
Test name
Test status
Simulation time 809084137 ps
CPU time 95.44 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:10:03 PM PDT 24
Peak memory 256896 kb
Host smart-c2dcf1ee-19a3-477f-bdc9-5d815a3ae7c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1636834863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1636834863
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.47200181
Short name T170
Test name
Test status
Simulation time 84920364 ps
CPU time 4.06 seconds
Started Mar 10 01:07:59 PM PDT 24
Finished Mar 10 01:08:03 PM PDT 24
Peak memory 236824 kb
Host smart-07b94c04-af84-40e1-b623-1bd51c0cd783
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=47200181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.47200181
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2621922710
Short name T184
Test name
Test status
Simulation time 979224369 ps
CPU time 71.73 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:09:39 PM PDT 24
Peak memory 239092 kb
Host smart-8179edf3-9c8e-4014-970a-b5e7c7b5d8ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2621922710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2621922710
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3024579050
Short name T180
Test name
Test status
Simulation time 2375371604 ps
CPU time 86.61 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:09:33 PM PDT 24
Peak memory 237552 kb
Host smart-768d7b59-6a8b-4786-b40c-8ab469b93229
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3024579050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3024579050
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.355939387
Short name T176
Test name
Test status
Simulation time 64403827 ps
CPU time 3.31 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:10 PM PDT 24
Peak memory 236752 kb
Host smart-ab9b8f0e-28ca-4df6-ac82-e4046a8cb066
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=355939387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.355939387
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.85953706
Short name T177
Test name
Test status
Simulation time 208385995 ps
CPU time 4.39 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:13 PM PDT 24
Peak memory 236272 kb
Host smart-af2c26fc-e71a-447c-bf61-3532e0aa388b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=85953706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.85953706
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.1444046074
Short name T178
Test name
Test status
Simulation time 114981360 ps
CPU time 3.29 seconds
Started Mar 10 01:08:15 PM PDT 24
Finished Mar 10 01:08:19 PM PDT 24
Peak memory 236316 kb
Host smart-4b2560aa-c2ee-4eae-a76a-638456542fb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1444046074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.1444046074
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2728507818
Short name T181
Test name
Test status
Simulation time 89940327 ps
CPU time 4.14 seconds
Started Mar 10 01:08:17 PM PDT 24
Finished Mar 10 01:08:22 PM PDT 24
Peak memory 236776 kb
Host smart-94448c12-5144-4ae1-be4a-59fc58c62a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2728507818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2728507818
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.361820484
Short name T145
Test name
Test status
Simulation time 851356772 ps
CPU time 104.99 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:10:04 PM PDT 24
Peak memory 256112 kb
Host smart-1693e546-56a2-4639-aae0-19e3a3622a31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=361820484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.361820484
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.4105475496
Short name T175
Test name
Test status
Simulation time 901450845 ps
CPU time 38.93 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:09:06 PM PDT 24
Peak memory 236544 kb
Host smart-9e181fe0-3272-41b1-8499-12a20cba6f9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4105475496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.4105475496
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3971511336
Short name T190
Test name
Test status
Simulation time 5528871602 ps
CPU time 35.2 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:43 PM PDT 24
Peak memory 245340 kb
Host smart-5d4e8b78-9368-4593-a5d6-aa39d3ee88f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3971511336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3971511336
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3125066077
Short name T168
Test name
Test status
Simulation time 86956752 ps
CPU time 2.75 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:08:22 PM PDT 24
Peak memory 237220 kb
Host smart-2812c966-0981-4a05-b49b-f1e8900a83f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3125066077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3125066077
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3727373209
Short name T186
Test name
Test status
Simulation time 61704228 ps
CPU time 2.83 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:08:22 PM PDT 24
Peak memory 236380 kb
Host smart-3337b5a6-fa14-4683-97b4-2670da6934e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3727373209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3727373209
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2233276150
Short name T179
Test name
Test status
Simulation time 609508774 ps
CPU time 24.1 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 236616 kb
Host smart-e47b3dc6-4734-412e-b25f-0c9432c0b3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2233276150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2233276150
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1743107302
Short name T183
Test name
Test status
Simulation time 92734853 ps
CPU time 5.31 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:08:15 PM PDT 24
Peak memory 235460 kb
Host smart-12933185-5e11-4b02-9142-8eaacb300765
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1743107302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1743107302
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.4174729777
Short name T29
Test name
Test status
Simulation time 49718769733 ps
CPU time 2927.99 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 02:14:54 PM PDT 24
Peak memory 290024 kb
Host smart-b3fa2f7a-a9f8-4219-9dcc-bf06af87bf7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174729777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.4174729777
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3065607643
Short name T728
Test name
Test status
Simulation time 2267081930 ps
CPU time 158.89 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:10:36 PM PDT 24
Peak memory 236316 kb
Host smart-d2493202-b8c3-458a-9f5e-e3b07ed1cff1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3065607643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3065607643
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1859834259
Short name T347
Test name
Test status
Simulation time 30928190390 ps
CPU time 458.14 seconds
Started Mar 10 01:07:59 PM PDT 24
Finished Mar 10 01:15:37 PM PDT 24
Peak memory 235472 kb
Host smart-75f7b31f-745b-4cb4-9a40-af3c91b58bb0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1859834259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1859834259
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.3657692493
Short name T784
Test name
Test status
Simulation time 870398824 ps
CPU time 9.04 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:17 PM PDT 24
Peak memory 240224 kb
Host smart-54046967-0ec8-4cbf-a842-82720fbd823a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3657692493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.3657692493
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2216644581
Short name T796
Test name
Test status
Simulation time 112564634 ps
CPU time 5.67 seconds
Started Mar 10 01:07:59 PM PDT 24
Finished Mar 10 01:08:04 PM PDT 24
Peak memory 240336 kb
Host smart-c348ba2e-a1b1-4a88-ab30-abf3d60f9bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216644581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2216644581
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4082701417
Short name T778
Test name
Test status
Simulation time 113823537 ps
CPU time 8.93 seconds
Started Mar 10 01:08:00 PM PDT 24
Finished Mar 10 01:08:09 PM PDT 24
Peak memory 235288 kb
Host smart-882e6f38-83d6-435c-b724-e7917fcaa89a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4082701417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4082701417
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3582010324
Short name T820
Test name
Test status
Simulation time 6510917 ps
CPU time 1.53 seconds
Started Mar 10 01:08:00 PM PDT 24
Finished Mar 10 01:08:02 PM PDT 24
Peak memory 236252 kb
Host smart-90ad3f17-8931-41ac-b2a3-0958edbc8cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3582010324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3582010324
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1388138353
Short name T801
Test name
Test status
Simulation time 2862742986 ps
CPU time 51.3 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:08:49 PM PDT 24
Peak memory 244468 kb
Host smart-03e776f9-cff6-445b-b380-24b5b12aa9b0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1388138353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1388138353
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3193073866
Short name T139
Test name
Test status
Simulation time 8407860684 ps
CPU time 381.67 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:14:19 PM PDT 24
Peak memory 264624 kb
Host smart-49d10e6f-2939-401d-9638-c2b096fd40d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3193073866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3193073866
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1787901604
Short name T705
Test name
Test status
Simulation time 66935592 ps
CPU time 3.25 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:10 PM PDT 24
Peak memory 248068 kb
Host smart-97447e70-f580-48e9-a7be-f9ba86a0506f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1787901604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1787901604
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2370975665
Short name T169
Test name
Test status
Simulation time 63623682 ps
CPU time 4.15 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:08:01 PM PDT 24
Peak memory 235468 kb
Host smart-d817fb47-7145-468c-9cfc-618d0141c00d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2370975665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2370975665
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3810221679
Short name T753
Test name
Test status
Simulation time 2158728599 ps
CPU time 147.29 seconds
Started Mar 10 01:07:56 PM PDT 24
Finished Mar 10 01:10:24 PM PDT 24
Peak memory 236236 kb
Host smart-ec60acc5-96af-4843-ba3e-34b4196d2827
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3810221679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3810221679
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3400085417
Short name T732
Test name
Test status
Simulation time 8920507998 ps
CPU time 501.43 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:16:29 PM PDT 24
Peak memory 240304 kb
Host smart-7e0df20a-b035-41f8-8b70-14f83eeb9db9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3400085417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3400085417
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.732664226
Short name T201
Test name
Test status
Simulation time 73473142 ps
CPU time 6.36 seconds
Started Mar 10 01:08:01 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 240204 kb
Host smart-9ec612a5-aa1a-4b94-b3d3-f84cc73ea1a4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=732664226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.732664226
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.764656463
Short name T189
Test name
Test status
Simulation time 41950459 ps
CPU time 5.42 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:08:03 PM PDT 24
Peak memory 256720 kb
Host smart-aa9e64f2-8cc2-4130-bebd-69771c805b6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764656463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.alert_handler_csr_mem_rw_with_rand_reset.764656463
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4274214397
Short name T738
Test name
Test status
Simulation time 487863675 ps
CPU time 9.81 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 236284 kb
Host smart-8ea16b8e-2c4f-4d62-85ae-340f12df58e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4274214397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4274214397
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1572526974
Short name T815
Test name
Test status
Simulation time 1075708369 ps
CPU time 23.65 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:08:21 PM PDT 24
Peak memory 244524 kb
Host smart-45f073ce-5c2a-4b10-898a-bc8e9696bcfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1572526974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1572526974
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3495313222
Short name T155
Test name
Test status
Simulation time 3716198247 ps
CPU time 112.51 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:09:50 PM PDT 24
Peak memory 256960 kb
Host smart-407e6afa-a9de-4c9d-9ef9-8aa64d639654
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3495313222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3495313222
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2746941400
Short name T167
Test name
Test status
Simulation time 2153305396 ps
CPU time 324.29 seconds
Started Mar 10 01:08:01 PM PDT 24
Finished Mar 10 01:13:26 PM PDT 24
Peak memory 267172 kb
Host smart-7d51d72d-6a16-4bee-bfcb-f882caa7522a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746941400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2746941400
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2613795320
Short name T827
Test name
Test status
Simulation time 264798849 ps
CPU time 10.34 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 250980 kb
Host smart-5536bff3-16c5-4cd2-9e16-3ea441d12081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2613795320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2613795320
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1225970965
Short name T794
Test name
Test status
Simulation time 97392706 ps
CPU time 8.67 seconds
Started Mar 10 01:08:16 PM PDT 24
Finished Mar 10 01:08:25 PM PDT 24
Peak memory 240308 kb
Host smart-1ea50aba-503e-44b3-8887-207c0d773319
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225970965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1225970965
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.3467926678
Short name T780
Test name
Test status
Simulation time 128110713 ps
CPU time 6.04 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 236324 kb
Host smart-9bb70697-c485-44e8-9fe0-2934cf41402a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3467926678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.3467926678
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3878926942
Short name T748
Test name
Test status
Simulation time 7941788 ps
CPU time 1.59 seconds
Started Mar 10 01:08:18 PM PDT 24
Finished Mar 10 01:08:21 PM PDT 24
Peak memory 234564 kb
Host smart-16abe6f9-1941-471e-955b-19eb7f3b948c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3878926942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3878926942
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1107721471
Short name T754
Test name
Test status
Simulation time 90398295 ps
CPU time 12.19 seconds
Started Mar 10 01:08:16 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 243528 kb
Host smart-beeec3bd-5d50-4e5d-bbee-fadcf5785c1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1107721471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1107721471
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2571406461
Short name T151
Test name
Test status
Simulation time 6537466956 ps
CPU time 219.8 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:11:54 PM PDT 24
Peak memory 270516 kb
Host smart-2df416f2-4e66-409d-a4ea-af4bdbad21bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2571406461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2571406461
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2359331747
Short name T158
Test name
Test status
Simulation time 4493810809 ps
CPU time 320.86 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:13:36 PM PDT 24
Peak memory 265164 kb
Host smart-7e98f614-922a-4ada-8a51-5f880e13ea0a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359331747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2359331747
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1648594037
Short name T798
Test name
Test status
Simulation time 3760083653 ps
CPU time 14.67 seconds
Started Mar 10 01:08:17 PM PDT 24
Finished Mar 10 01:08:33 PM PDT 24
Peak memory 248548 kb
Host smart-f56b1a40-d623-4eb3-99a3-5f85ded645d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1648594037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1648594037
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3832871730
Short name T735
Test name
Test status
Simulation time 101372618 ps
CPU time 5.9 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 237652 kb
Host smart-2e07830a-e127-46e1-8a18-1962fc781f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3832871730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3832871730
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.1969540993
Short name T779
Test name
Test status
Simulation time 135956901 ps
CPU time 5.08 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 236500 kb
Host smart-6129d317-609c-48ab-a760-15fcf92bca07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969540993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.1969540993
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.917356058
Short name T740
Test name
Test status
Simulation time 34321960 ps
CPU time 6.11 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:26 PM PDT 24
Peak memory 236244 kb
Host smart-3fa7ad99-ffdf-47f2-884e-41b709f7a2ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=917356058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.917356058
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3238817192
Short name T777
Test name
Test status
Simulation time 8680206 ps
CPU time 1.57 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:24 PM PDT 24
Peak memory 236404 kb
Host smart-ef943b13-fbc6-4eba-be5a-7ed8d37a5c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3238817192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3238817192
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1755674089
Short name T202
Test name
Test status
Simulation time 522938369 ps
CPU time 40.34 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:09:03 PM PDT 24
Peak memory 243632 kb
Host smart-1f05207a-cf38-4170-a3e6-ed161c941ceb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1755674089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1755674089
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1702950565
Short name T152
Test name
Test status
Simulation time 1940783106 ps
CPU time 145.04 seconds
Started Mar 10 01:08:15 PM PDT 24
Finished Mar 10 01:10:40 PM PDT 24
Peak memory 256940 kb
Host smart-3892bd10-13c0-4335-91bd-16f8a5df6044
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1702950565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1702950565
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2939221652
Short name T731
Test name
Test status
Simulation time 128167968 ps
CPU time 9.93 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 248120 kb
Host smart-de7cfaf0-8df2-4243-94db-691866e1db69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2939221652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2939221652
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.1445343366
Short name T816
Test name
Test status
Simulation time 140625799 ps
CPU time 6.02 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:08:26 PM PDT 24
Peak memory 248596 kb
Host smart-6e079dcb-9646-4b56-b87e-174db2ea8dea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445343366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.1445343366
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.891987676
Short name T765
Test name
Test status
Simulation time 528578442 ps
CPU time 10.31 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:30 PM PDT 24
Peak memory 236244 kb
Host smart-b42acfb6-a329-4fac-9c5c-3e0a16f73004
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=891987676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.891987676
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.15431602
Short name T727
Test name
Test status
Simulation time 17980882 ps
CPU time 1.41 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:24 PM PDT 24
Peak memory 235528 kb
Host smart-322eb042-68e4-44a1-9c4d-a40509ee427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=15431602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.15431602
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3367679103
Short name T773
Test name
Test status
Simulation time 1029798153 ps
CPU time 22.62 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:42 PM PDT 24
Peak memory 244464 kb
Host smart-bab5d58c-7f74-4ddf-a5d1-217123233201
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3367679103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3367679103
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3383492715
Short name T153
Test name
Test status
Simulation time 3865895425 ps
CPU time 108.52 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:10:15 PM PDT 24
Peak memory 256936 kb
Host smart-1704af89-beba-4247-9933-4fb9b36f8915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3383492715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3383492715
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3902563008
Short name T760
Test name
Test status
Simulation time 545539812 ps
CPU time 8.73 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:31 PM PDT 24
Peak memory 248476 kb
Host smart-f0eba39c-0417-4614-8bd9-b70613bd01b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902563008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3902563008
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2771684529
Short name T712
Test name
Test status
Simulation time 54565705 ps
CPU time 4.71 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 240376 kb
Host smart-df75ba29-4231-4bcb-8654-5ca5b50e79ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771684529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2771684529
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2681079515
Short name T187
Test name
Test status
Simulation time 503827387 ps
CPU time 9.86 seconds
Started Mar 10 01:08:19 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 236336 kb
Host smart-8a5223bf-7e22-4f42-b639-eabd2c9b7a53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2681079515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2681079515
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.4220395733
Short name T745
Test name
Test status
Simulation time 6650961 ps
CPU time 1.57 seconds
Started Mar 10 01:08:18 PM PDT 24
Finished Mar 10 01:08:21 PM PDT 24
Peak memory 235412 kb
Host smart-83b24ec8-1ca6-4b53-b28f-59f6eedbfc66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4220395733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.4220395733
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.3231344004
Short name T200
Test name
Test status
Simulation time 350319314 ps
CPU time 17.16 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:39 PM PDT 24
Peak memory 244636 kb
Host smart-81ee803f-62d2-410d-a7be-a24ed8a138f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3231344004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.3231344004
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1092477954
Short name T713
Test name
Test status
Simulation time 568154898 ps
CPU time 20.4 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 248392 kb
Host smart-883634e7-e8d8-4913-97a2-b7e4951aa2a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1092477954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1092477954
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2352284392
Short name T756
Test name
Test status
Simulation time 400041508 ps
CPU time 9.42 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:35 PM PDT 24
Peak memory 256720 kb
Host smart-584252e1-f3a2-407b-9469-1d0a17de5058
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352284392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2352284392
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3041851438
Short name T741
Test name
Test status
Simulation time 34223273 ps
CPU time 5.2 seconds
Started Mar 10 01:08:22 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 235412 kb
Host smart-1bde3f8b-8ac8-4cd0-9e71-a4387b86507f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3041851438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3041851438
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2134834250
Short name T726
Test name
Test status
Simulation time 7658828 ps
CPU time 1.49 seconds
Started Mar 10 01:08:22 PM PDT 24
Finished Mar 10 01:08:24 PM PDT 24
Peak memory 235496 kb
Host smart-fe509795-6c75-4e51-8527-d079c79194ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2134834250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2134834250
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.1830052766
Short name T807
Test name
Test status
Simulation time 256188019 ps
CPU time 19.82 seconds
Started Mar 10 01:08:24 PM PDT 24
Finished Mar 10 01:08:44 PM PDT 24
Peak memory 245716 kb
Host smart-5f4a0759-a317-4e3c-9194-5ae24ea24434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1830052766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.1830052766
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3775927094
Short name T822
Test name
Test status
Simulation time 8244056336 ps
CPU time 571.46 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:17:54 PM PDT 24
Peak memory 268668 kb
Host smart-6b6e0d29-3ec9-45c4-b4c3-62991fc50348
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775927094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3775927094
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3760738199
Short name T725
Test name
Test status
Simulation time 109117132 ps
CPU time 14.94 seconds
Started Mar 10 01:08:21 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 252308 kb
Host smart-a292b1fb-d68e-4b7f-b1fa-aa5a29bc3648
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3760738199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3760738199
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1734581497
Short name T742
Test name
Test status
Simulation time 55900420 ps
CPU time 2.48 seconds
Started Mar 10 01:08:20 PM PDT 24
Finished Mar 10 01:08:25 PM PDT 24
Peak memory 235444 kb
Host smart-3e486c6e-b55a-400d-881d-998d0fa776fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1734581497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1734581497
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3294769407
Short name T810
Test name
Test status
Simulation time 776670396 ps
CPU time 15.12 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:08:41 PM PDT 24
Peak memory 251424 kb
Host smart-1c8b453a-37d9-45ca-953c-778eb3a1117a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294769407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3294769407
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3795612153
Short name T764
Test name
Test status
Simulation time 184351605 ps
CPU time 4.51 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 239040 kb
Host smart-b066b82d-7f11-4c99-b4df-43ba206e9586
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3795612153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3795612153
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2981426422
Short name T719
Test name
Test status
Simulation time 9689512 ps
CPU time 1.52 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 234412 kb
Host smart-83258bef-1e1b-4748-992f-05aa7a176069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2981426422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2981426422
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1872386016
Short name T821
Test name
Test status
Simulation time 499853305 ps
CPU time 35.63 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:09:01 PM PDT 24
Peak memory 248528 kb
Host smart-13b1feb2-03ef-492d-872e-7863609ab660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1872386016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1872386016
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1631515143
Short name T132
Test name
Test status
Simulation time 2091399249 ps
CPU time 157.48 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:11:03 PM PDT 24
Peak memory 256392 kb
Host smart-a4102090-77a8-4664-b6fd-3d408acfc5ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1631515143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1631515143
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1418499588
Short name T146
Test name
Test status
Simulation time 15460762214 ps
CPU time 1116.42 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:27:03 PM PDT 24
Peak memory 272556 kb
Host smart-8021d134-48b8-4f58-925a-cdceb0077871
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418499588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1418499588
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.657960311
Short name T802
Test name
Test status
Simulation time 305644157 ps
CPU time 6.35 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:33 PM PDT 24
Peak memory 248588 kb
Host smart-a375314d-e078-410a-b3a0-5c4f76f70624
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=657960311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.657960311
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1446041972
Short name T730
Test name
Test status
Simulation time 29001306 ps
CPU time 5.26 seconds
Started Mar 10 01:08:28 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 238680 kb
Host smart-46bae6c1-b34e-4b23-a5d2-577e1911a3fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446041972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1446041972
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3505154504
Short name T348
Test name
Test status
Simulation time 64338953 ps
CPU time 5.66 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:08:31 PM PDT 24
Peak memory 235400 kb
Host smart-d08a65a1-48c8-4580-b26a-16f9865d4981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3505154504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3505154504
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1119992513
Short name T814
Test name
Test status
Simulation time 10735754 ps
CPU time 1.7 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 235488 kb
Host smart-e4f157dd-77b7-4372-8c12-958fec65dd0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1119992513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1119992513
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1722753149
Short name T714
Test name
Test status
Simulation time 253122784 ps
CPU time 18.67 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:45 PM PDT 24
Peak memory 240328 kb
Host smart-7f144a70-168a-4b55-a244-4beb8450d0f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1722753149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1722753149
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.874235432
Short name T161
Test name
Test status
Simulation time 2525714810 ps
CPU time 107.38 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:10:15 PM PDT 24
Peak memory 265140 kb
Host smart-f2a4c204-da72-4645-917a-a866e1b2dd46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=874235432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.874235432
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3959765702
Short name T349
Test name
Test status
Simulation time 37840452803 ps
CPU time 618.34 seconds
Started Mar 10 01:08:36 PM PDT 24
Finished Mar 10 01:18:54 PM PDT 24
Peak memory 271996 kb
Host smart-c6fb5ecc-ca80-4ea7-b76e-3383b45a8561
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959765702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3959765702
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2011019282
Short name T770
Test name
Test status
Simulation time 146951193 ps
CPU time 5.18 seconds
Started Mar 10 01:08:35 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 248444 kb
Host smart-a930a6a0-3915-4cf5-bb96-77816d35458a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2011019282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2011019282
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3120889570
Short name T769
Test name
Test status
Simulation time 412008314 ps
CPU time 15.32 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:42 PM PDT 24
Peak memory 249552 kb
Host smart-176a9c0b-0ad7-4f51-8088-7a5e8b80f060
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120889570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3120889570
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3410730110
Short name T793
Test name
Test status
Simulation time 360816091 ps
CPU time 8.17 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 240208 kb
Host smart-3f517794-1074-4149-aa06-5646090248ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3410730110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3410730110
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3175999185
Short name T758
Test name
Test status
Simulation time 10223699 ps
CPU time 1.31 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 236416 kb
Host smart-685da041-cd6b-409f-bb79-ecb665ad6efb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3175999185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3175999185
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2678922016
Short name T789
Test name
Test status
Simulation time 1389441519 ps
CPU time 57.89 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:09:32 PM PDT 24
Peak memory 244460 kb
Host smart-4e604840-8ebe-48ab-a104-537fdeeed5b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2678922016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2678922016
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3430519490
Short name T162
Test name
Test status
Simulation time 15650929388 ps
CPU time 316.59 seconds
Started Mar 10 01:08:25 PM PDT 24
Finished Mar 10 01:13:42 PM PDT 24
Peak memory 265168 kb
Host smart-fb3d5366-24da-493b-9a53-7e6369bea5d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3430519490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3430519490
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3182047675
Short name T710
Test name
Test status
Simulation time 125984491 ps
CPU time 13.36 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 248052 kb
Host smart-9488f122-9d8a-4a97-a9e0-6110a07d7a16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3182047675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3182047675
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4165096232
Short name T829
Test name
Test status
Simulation time 58466292 ps
CPU time 5.64 seconds
Started Mar 10 01:08:28 PM PDT 24
Finished Mar 10 01:08:35 PM PDT 24
Peak memory 236424 kb
Host smart-862850de-e2ee-4822-9acf-1d4d12381993
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165096232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4165096232
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3672587775
Short name T755
Test name
Test status
Simulation time 62596973 ps
CPU time 6.31 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 236260 kb
Host smart-a4823d7e-daeb-400b-ae88-84e1fd4d0f85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3672587775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3672587775
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2432026569
Short name T717
Test name
Test status
Simulation time 14734083 ps
CPU time 1.45 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 235500 kb
Host smart-ede7c8c9-8248-46b6-b4f6-f4162b7ee893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2432026569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2432026569
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.4035000800
Short name T763
Test name
Test status
Simulation time 1652607777 ps
CPU time 48.68 seconds
Started Mar 10 01:08:24 PM PDT 24
Finished Mar 10 01:09:13 PM PDT 24
Peak memory 244532 kb
Host smart-1600c82a-c840-496d-a5b4-b4176a51a6d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4035000800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.4035000800
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1067844279
Short name T156
Test name
Test status
Simulation time 39402033242 ps
CPU time 1051.73 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:25:58 PM PDT 24
Peak memory 265272 kb
Host smart-32909115-4c17-42eb-b6e6-bffe52a12fcd
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067844279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1067844279
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3685699618
Short name T797
Test name
Test status
Simulation time 181529483 ps
CPU time 5.38 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:31 PM PDT 24
Peak memory 247064 kb
Host smart-1be481e9-c060-4d55-97f5-ec156b661818
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3685699618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3685699618
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1647992215
Short name T253
Test name
Test status
Simulation time 134222693 ps
CPU time 4.19 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:32 PM PDT 24
Peak memory 236832 kb
Host smart-15a9640d-68c8-4bcd-801a-54968f9c2502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647992215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1647992215
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.435285935
Short name T711
Test name
Test status
Simulation time 775087406 ps
CPU time 14.17 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 250612 kb
Host smart-d859a91d-3b37-4e32-98c7-b825c5c7f7e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435285935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.alert_handler_csr_mem_rw_with_rand_reset.435285935
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2981211647
Short name T761
Test name
Test status
Simulation time 51411403 ps
CPU time 4.6 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 240100 kb
Host smart-9ddac5a2-8d1e-4b05-928a-5b85457d892a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981211647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2981211647
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.1927236652
Short name T803
Test name
Test status
Simulation time 8004190 ps
CPU time 1.47 seconds
Started Mar 10 01:08:28 PM PDT 24
Finished Mar 10 01:08:30 PM PDT 24
Peak memory 234528 kb
Host smart-85e422a6-0eaa-48e7-b9e1-6f9df203f0e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1927236652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.1927236652
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.419817810
Short name T817
Test name
Test status
Simulation time 183407906 ps
CPU time 23.4 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:51 PM PDT 24
Peak memory 243664 kb
Host smart-3bb1104b-d6db-485b-acec-863e709b44d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=419817810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.419817810
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.964432071
Short name T157
Test name
Test status
Simulation time 125818369618 ps
CPU time 985.19 seconds
Started Mar 10 01:08:28 PM PDT 24
Finished Mar 10 01:24:54 PM PDT 24
Peak memory 265192 kb
Host smart-78b97a40-f155-445e-88f1-d368a3a5aa01
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964432071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.964432071
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2759983050
Short name T706
Test name
Test status
Simulation time 836069740 ps
CPU time 16.51 seconds
Started Mar 10 01:08:28 PM PDT 24
Finished Mar 10 01:08:45 PM PDT 24
Peak memory 248312 kb
Host smart-05551be0-4ac0-4a64-8365-bbc49526606c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2759983050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2759983050
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4140602678
Short name T772
Test name
Test status
Simulation time 561039052 ps
CPU time 62.63 seconds
Started Mar 10 01:08:03 PM PDT 24
Finished Mar 10 01:09:06 PM PDT 24
Peak memory 236396 kb
Host smart-d527955b-6c2f-419b-8398-3cfbb04d6f84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4140602678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4140602678
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.1534613368
Short name T213
Test name
Test status
Simulation time 74238595991 ps
CPU time 216.48 seconds
Started Mar 10 01:07:56 PM PDT 24
Finished Mar 10 01:11:33 PM PDT 24
Peak memory 235376 kb
Host smart-50d0a43d-9ea0-4e4c-aab9-b17c47e49a3b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1534613368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.1534613368
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.688163899
Short name T824
Test name
Test status
Simulation time 142996088 ps
CPU time 6.59 seconds
Started Mar 10 01:07:57 PM PDT 24
Finished Mar 10 01:08:04 PM PDT 24
Peak memory 240204 kb
Host smart-a0c6317b-9e4e-4e06-9c59-45ffeb308bc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=688163899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.688163899
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3029133306
Short name T746
Test name
Test status
Simulation time 66400724 ps
CPU time 11.76 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:08:16 PM PDT 24
Peak memory 251856 kb
Host smart-afe36863-e6c1-4b5b-b363-78c75eb8b6e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029133306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3029133306
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.4264088294
Short name T792
Test name
Test status
Simulation time 252575616 ps
CPU time 4.94 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:12 PM PDT 24
Peak memory 236332 kb
Host smart-f2d848ce-60ef-4014-8b11-bb6b57e0ce8c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4264088294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.4264088294
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3793321280
Short name T751
Test name
Test status
Simulation time 7035230 ps
CPU time 1.47 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 235516 kb
Host smart-39f586eb-5dee-42c4-9d0c-e5eed49085ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793321280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3793321280
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.189787540
Short name T762
Test name
Test status
Simulation time 427536684 ps
CPU time 13.9 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 244480 kb
Host smart-5146109c-bcfb-4143-b10c-d83a2cc8b033
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=189787540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.189787540
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.657815628
Short name T143
Test name
Test status
Simulation time 3769670621 ps
CPU time 188.23 seconds
Started Mar 10 01:07:58 PM PDT 24
Finished Mar 10 01:11:06 PM PDT 24
Peak memory 272752 kb
Host smart-ea82fffa-a181-4d8f-8a7f-ba41a9f74bfa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=657815628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.657815628
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1934602187
Short name T160
Test name
Test status
Simulation time 2326687051 ps
CPU time 329.15 seconds
Started Mar 10 01:08:00 PM PDT 24
Finished Mar 10 01:13:29 PM PDT 24
Peak memory 265056 kb
Host smart-10ffc67e-7b2e-4a79-935f-5845563435cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934602187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1934602187
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.4177757300
Short name T734
Test name
Test status
Simulation time 265411122 ps
CPU time 5.3 seconds
Started Mar 10 01:07:56 PM PDT 24
Finished Mar 10 01:08:02 PM PDT 24
Peak memory 248900 kb
Host smart-bcc486a7-22a1-4433-9a85-fd711dcbc12a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4177757300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.4177757300
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1055849063
Short name T722
Test name
Test status
Simulation time 18497901 ps
CPU time 1.35 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 236264 kb
Host smart-6ecdf64e-3d01-4dea-829d-5af254316a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1055849063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1055849063
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1639170993
Short name T342
Test name
Test status
Simulation time 8723837 ps
CPU time 1.5 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 236380 kb
Host smart-4a3be92d-a89b-4cbb-b0ba-fdea453ceb77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1639170993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1639170993
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1799503965
Short name T823
Test name
Test status
Simulation time 9943370 ps
CPU time 1.41 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 235540 kb
Host smart-157eaa14-c011-47a2-96c0-c6195fe5b243
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1799503965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1799503965
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1074527874
Short name T341
Test name
Test status
Simulation time 24471254 ps
CPU time 1.43 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:08:35 PM PDT 24
Peak memory 236284 kb
Host smart-5e56a2cb-ec20-460d-93d9-e0c05295d17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1074527874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1074527874
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1860380410
Short name T805
Test name
Test status
Simulation time 18751372 ps
CPU time 1.87 seconds
Started Mar 10 01:08:35 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 234496 kb
Host smart-da72cf49-7043-406c-b4c7-1463f1ea9394
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1860380410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1860380410
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.3743303075
Short name T795
Test name
Test status
Simulation time 9547681 ps
CPU time 1.29 seconds
Started Mar 10 01:08:27 PM PDT 24
Finished Mar 10 01:08:29 PM PDT 24
Peak memory 236340 kb
Host smart-5fff41fc-671e-4faf-b85f-2102d5e11a74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3743303075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.3743303075
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2534371571
Short name T729
Test name
Test status
Simulation time 12027686 ps
CPU time 1.4 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 234476 kb
Host smart-d45fca7c-dc6e-4dce-a037-a4d789d2cf32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534371571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2534371571
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.916571200
Short name T747
Test name
Test status
Simulation time 9183426 ps
CPU time 1.64 seconds
Started Mar 10 01:08:26 PM PDT 24
Finished Mar 10 01:08:28 PM PDT 24
Peak memory 236312 kb
Host smart-c97a1bda-8c79-4c5e-9f50-f0a04ad41b91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=916571200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.916571200
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1588060456
Short name T199
Test name
Test status
Simulation time 573101381 ps
CPU time 65.6 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:09:08 PM PDT 24
Peak memory 236416 kb
Host smart-8f26a421-91a1-4305-811c-407b4ea3bd33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1588060456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1588060456
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3088157520
Short name T733
Test name
Test status
Simulation time 18552924389 ps
CPU time 277.12 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:12:39 PM PDT 24
Peak memory 240276 kb
Host smart-cf7ebc83-9dcb-41f6-ac30-d5f13a189f9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3088157520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3088157520
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1680046660
Short name T744
Test name
Test status
Simulation time 129177199 ps
CPU time 3.79 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:10 PM PDT 24
Peak memory 240140 kb
Host smart-c0961d21-8db1-4210-9a2b-1564ee21a087
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1680046660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1680046660
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.2588017697
Short name T759
Test name
Test status
Simulation time 216695381 ps
CPU time 9.69 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:08:16 PM PDT 24
Peak memory 242440 kb
Host smart-f89c6575-13bf-4785-9211-5c0b72692660
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588017697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.2588017697
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2207868260
Short name T800
Test name
Test status
Simulation time 421532810 ps
CPU time 9.12 seconds
Started Mar 10 01:08:01 PM PDT 24
Finished Mar 10 01:08:11 PM PDT 24
Peak memory 235476 kb
Host smart-1b3de059-5a36-40a6-9e8b-bddf4913d539
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2207868260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2207868260
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2485224036
Short name T791
Test name
Test status
Simulation time 9692518 ps
CPU time 1.54 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 234508 kb
Host smart-be217ee5-6e87-464d-9b60-5f4688a0ca24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2485224036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2485224036
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.1030571625
Short name T716
Test name
Test status
Simulation time 1002620477 ps
CPU time 39.04 seconds
Started Mar 10 01:08:03 PM PDT 24
Finished Mar 10 01:08:43 PM PDT 24
Peak memory 244504 kb
Host smart-6862ac4c-504b-421a-a0d8-8254719f8743
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1030571625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.1030571625
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1860254699
Short name T147
Test name
Test status
Simulation time 2578305568 ps
CPU time 194.13 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:11:18 PM PDT 24
Peak memory 267732 kb
Host smart-9e429a0b-8e2c-494b-be29-f41fab37941b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1860254699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1860254699
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1161581773
Short name T149
Test name
Test status
Simulation time 31247669726 ps
CPU time 669.46 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:19:14 PM PDT 24
Peak memory 265148 kb
Host smart-0e669777-67e3-483c-ab2a-bb946d38be41
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161581773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1161581773
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2058470730
Short name T787
Test name
Test status
Simulation time 288515146 ps
CPU time 5.11 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:08:11 PM PDT 24
Peak memory 240236 kb
Host smart-2e51701e-4d9a-484c-86e6-c51a2eadfc2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2058470730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2058470730
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.1784482422
Short name T173
Test name
Test status
Simulation time 7547260 ps
CPU time 1.49 seconds
Started Mar 10 01:08:35 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 234456 kb
Host smart-edbbfbeb-58aa-40ce-b08d-45ca17c5c02b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1784482422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.1784482422
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3480116804
Short name T774
Test name
Test status
Simulation time 17405374 ps
CPU time 1.34 seconds
Started Mar 10 01:08:38 PM PDT 24
Finished Mar 10 01:08:39 PM PDT 24
Peak memory 236340 kb
Host smart-9f0a38fd-bcf2-4e8b-be02-7c7415344ddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480116804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3480116804
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3436479708
Short name T799
Test name
Test status
Simulation time 7445235 ps
CPU time 1.48 seconds
Started Mar 10 01:08:36 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 234564 kb
Host smart-0fcbf336-f117-40dd-af1c-c5bad6c3073b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3436479708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3436479708
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.942906045
Short name T718
Test name
Test status
Simulation time 14142523 ps
CPU time 1.35 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 235484 kb
Host smart-ee4c4722-66ba-48fe-8f67-9a5852e84c2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=942906045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.942906045
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3943017926
Short name T344
Test name
Test status
Simulation time 9445315 ps
CPU time 1.41 seconds
Started Mar 10 01:08:41 PM PDT 24
Finished Mar 10 01:08:42 PM PDT 24
Peak memory 235424 kb
Host smart-0606148f-4e64-4b21-b741-441df7be4025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3943017926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3943017926
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.235020627
Short name T790
Test name
Test status
Simulation time 9896828 ps
CPU time 1.57 seconds
Started Mar 10 01:08:37 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 235448 kb
Host smart-451c6257-9d5a-490b-96a0-41f07e9510f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=235020627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.235020627
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1104238328
Short name T343
Test name
Test status
Simulation time 6091749 ps
CPU time 1.4 seconds
Started Mar 10 01:08:38 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 236340 kb
Host smart-a0820426-3585-4b98-89cf-22ae639f0e41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1104238328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1104238328
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.278925025
Short name T819
Test name
Test status
Simulation time 9448060 ps
CPU time 1.48 seconds
Started Mar 10 01:08:34 PM PDT 24
Finished Mar 10 01:08:36 PM PDT 24
Peak memory 235564 kb
Host smart-3ab82dc7-8e8a-49f2-b5f3-410a1082f4a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=278925025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.278925025
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3835084426
Short name T171
Test name
Test status
Simulation time 6377931 ps
CPU time 1.4 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 236252 kb
Host smart-b1b14c3c-14e8-4700-a0e8-6184960476bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3835084426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3835084426
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.142708744
Short name T785
Test name
Test status
Simulation time 6616050 ps
CPU time 1.53 seconds
Started Mar 10 01:08:32 PM PDT 24
Finished Mar 10 01:08:34 PM PDT 24
Peak memory 236300 kb
Host smart-bfe64046-5404-4a66-ae87-414c2c1cb341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=142708744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.142708744
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2858801580
Short name T721
Test name
Test status
Simulation time 1087435927 ps
CPU time 141.17 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:10:28 PM PDT 24
Peak memory 240200 kb
Host smart-df6b9290-b0d7-4631-a1f9-c110554bddd2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2858801580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2858801580
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3015929076
Short name T214
Test name
Test status
Simulation time 4491992610 ps
CPU time 253.21 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:12:17 PM PDT 24
Peak memory 240224 kb
Host smart-9e173b06-9737-42d9-9c7c-d1301f36356e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3015929076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3015929076
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3004938653
Short name T768
Test name
Test status
Simulation time 78099003 ps
CPU time 3.93 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:08:10 PM PDT 24
Peak memory 240244 kb
Host smart-b38bdc40-dc34-4db2-9044-9cf6f2825ed5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3004938653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3004938653
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1567127598
Short name T771
Test name
Test status
Simulation time 699731522 ps
CPU time 14.14 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:08:17 PM PDT 24
Peak memory 250572 kb
Host smart-705d41b2-3722-4e43-a113-a6bf9db90fdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567127598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1567127598
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4083107017
Short name T775
Test name
Test status
Simulation time 207301861 ps
CPU time 4.56 seconds
Started Mar 10 01:08:04 PM PDT 24
Finished Mar 10 01:08:09 PM PDT 24
Peak memory 239100 kb
Host smart-d1d6c60c-4748-49a2-b4d1-d2689bfe3097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4083107017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4083107017
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3370855453
Short name T749
Test name
Test status
Simulation time 15245884 ps
CPU time 1.45 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 236360 kb
Host smart-6f71f97e-5c89-488e-a20e-9775e0a8887e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3370855453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3370855453
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1547514921
Short name T786
Test name
Test status
Simulation time 425911029 ps
CPU time 12.35 seconds
Started Mar 10 01:08:03 PM PDT 24
Finished Mar 10 01:08:15 PM PDT 24
Peak memory 244496 kb
Host smart-435e1d72-aaea-4400-950f-777d04273752
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1547514921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1547514921
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3843638662
Short name T134
Test name
Test status
Simulation time 4218552857 ps
CPU time 599.06 seconds
Started Mar 10 01:08:02 PM PDT 24
Finished Mar 10 01:18:02 PM PDT 24
Peak memory 265108 kb
Host smart-846053f2-1a74-4eaa-90b2-ccedc2abe8c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843638662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3843638662
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2292037850
Short name T826
Test name
Test status
Simulation time 719910129 ps
CPU time 17.76 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:24 PM PDT 24
Peak memory 247808 kb
Host smart-f30063d5-c404-40d2-83da-2786efcf9602
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2292037850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2292037850
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2555128134
Short name T812
Test name
Test status
Simulation time 6340812 ps
CPU time 1.5 seconds
Started Mar 10 01:08:35 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 236344 kb
Host smart-3a62532a-42ea-4a3a-8dda-e195677f6486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2555128134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2555128134
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3793038920
Short name T776
Test name
Test status
Simulation time 17536110 ps
CPU time 1.88 seconds
Started Mar 10 01:08:37 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 235408 kb
Host smart-f8b30db3-39e5-4c27-9f92-8c2db7c5958e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3793038920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3793038920
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.918351751
Short name T813
Test name
Test status
Simulation time 17453159 ps
CPU time 1.4 seconds
Started Mar 10 01:08:34 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 236364 kb
Host smart-74644f39-ea98-4885-a6d4-216e492d9f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=918351751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.918351751
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1972604511
Short name T346
Test name
Test status
Simulation time 12840815 ps
CPU time 1.71 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:08:36 PM PDT 24
Peak memory 235568 kb
Host smart-b82cec0e-67bf-40ba-9f73-039c1d56cd8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972604511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1972604511
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2970797896
Short name T743
Test name
Test status
Simulation time 10577007 ps
CPU time 1.29 seconds
Started Mar 10 01:08:36 PM PDT 24
Finished Mar 10 01:08:39 PM PDT 24
Peak memory 235524 kb
Host smart-cb2aa025-e1d6-4e39-9942-1cf0892cb21c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2970797896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2970797896
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.877476884
Short name T781
Test name
Test status
Simulation time 11025047 ps
CPU time 1.31 seconds
Started Mar 10 01:08:36 PM PDT 24
Finished Mar 10 01:08:39 PM PDT 24
Peak memory 236400 kb
Host smart-393eef4c-3848-46f7-86bc-330df7e19e30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=877476884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.877476884
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4281028115
Short name T752
Test name
Test status
Simulation time 13577596 ps
CPU time 1.69 seconds
Started Mar 10 01:08:34 PM PDT 24
Finished Mar 10 01:08:36 PM PDT 24
Peak memory 234380 kb
Host smart-e02f9057-9475-46fd-bd5d-7a7c8f82bea9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4281028115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4281028115
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.7558017
Short name T809
Test name
Test status
Simulation time 9250369 ps
CPU time 1.57 seconds
Started Mar 10 01:08:34 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 236372 kb
Host smart-96d44140-4f99-4f4d-9858-e6bddb01bc97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=7558017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.7558017
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2217591456
Short name T788
Test name
Test status
Simulation time 9810838 ps
CPU time 1.33 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:08:37 PM PDT 24
Peak memory 236328 kb
Host smart-d441a5d3-4946-45d5-a310-73dc3d71ce4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2217591456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2217591456
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3055774863
Short name T750
Test name
Test status
Simulation time 12777889 ps
CPU time 1.43 seconds
Started Mar 10 01:08:33 PM PDT 24
Finished Mar 10 01:08:36 PM PDT 24
Peak memory 236364 kb
Host smart-0a921b2a-b3da-4ffb-9b3c-7fff0f173276
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3055774863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3055774863
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3215950294
Short name T828
Test name
Test status
Simulation time 64646178 ps
CPU time 10.98 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 252128 kb
Host smart-871fd4d7-f9ee-4c16-9db7-a24fed835aeb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215950294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3215950294
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2829705572
Short name T715
Test name
Test status
Simulation time 38470143 ps
CPU time 5.77 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:14 PM PDT 24
Peak memory 236264 kb
Host smart-c5dca3b5-b4e0-4ac6-a9e3-e29264c8183b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2829705572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2829705572
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1997424016
Short name T172
Test name
Test status
Simulation time 7971336 ps
CPU time 1.32 seconds
Started Mar 10 01:08:06 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 235496 kb
Host smart-867d9be4-7582-450e-aca4-0adfc9647eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1997424016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1997424016
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3229596989
Short name T818
Test name
Test status
Simulation time 505614150 ps
CPU time 41.37 seconds
Started Mar 10 01:08:10 PM PDT 24
Finished Mar 10 01:08:51 PM PDT 24
Peak memory 248516 kb
Host smart-6d62e2e5-d00f-4ce3-a36b-73c32367303e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3229596989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3229596989
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1883459708
Short name T720
Test name
Test status
Simulation time 275894699 ps
CPU time 10.06 seconds
Started Mar 10 01:08:05 PM PDT 24
Finished Mar 10 01:08:16 PM PDT 24
Peak memory 250232 kb
Host smart-adaf0f7c-349d-454f-870f-540b93ab7224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1883459708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1883459708
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2477597982
Short name T737
Test name
Test status
Simulation time 83706981 ps
CPU time 6.94 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:08:16 PM PDT 24
Peak memory 238980 kb
Host smart-2cfef6ff-00c6-42da-a620-b3280c7469d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477597982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2477597982
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1414975972
Short name T825
Test name
Test status
Simulation time 128792039 ps
CPU time 10.65 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:19 PM PDT 24
Peak memory 236236 kb
Host smart-bde0ccaf-c409-415c-9cab-527f025b9ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1414975972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1414975972
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3928980145
Short name T724
Test name
Test status
Simulation time 8252898 ps
CPU time 1.47 seconds
Started Mar 10 01:08:11 PM PDT 24
Finished Mar 10 01:08:13 PM PDT 24
Peak memory 236340 kb
Host smart-aed49269-8be9-473f-b5c1-eeac2f8818f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3928980145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3928980145
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1973549642
Short name T204
Test name
Test status
Simulation time 85978954 ps
CPU time 12.72 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:21 PM PDT 24
Peak memory 244592 kb
Host smart-aea7bf93-9c6e-4627-a9cf-d6daf03c8952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1973549642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1973549642
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3313304075
Short name T166
Test name
Test status
Simulation time 1703631933 ps
CPU time 212.95 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:11:41 PM PDT 24
Peak memory 272612 kb
Host smart-56027e62-4829-4b07-94ed-152454e507df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3313304075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3313304075
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3194963238
Short name T782
Test name
Test status
Simulation time 497458758 ps
CPU time 15.54 seconds
Started Mar 10 01:08:11 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 248444 kb
Host smart-bcfca93c-5283-4f6f-84a7-5156ab856933
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194963238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3194963238
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3193554722
Short name T188
Test name
Test status
Simulation time 142317648 ps
CPU time 6.78 seconds
Started Mar 10 01:08:12 PM PDT 24
Finished Mar 10 01:08:19 PM PDT 24
Peak memory 252600 kb
Host smart-a7eda43d-2dce-40c8-9dfa-c8228edd397d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193554722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3193554722
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3867484021
Short name T783
Test name
Test status
Simulation time 20864242 ps
CPU time 3.54 seconds
Started Mar 10 01:08:11 PM PDT 24
Finished Mar 10 01:08:15 PM PDT 24
Peak memory 240108 kb
Host smart-0d7c546a-8376-4211-ac00-2b7c230f11e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3867484021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3867484021
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3276588594
Short name T757
Test name
Test status
Simulation time 8110769 ps
CPU time 1.36 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:08:08 PM PDT 24
Peak memory 235524 kb
Host smart-914cd3bb-d4f8-4d1a-a1fe-83ffa8404e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3276588594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3276588594
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1713897690
Short name T806
Test name
Test status
Simulation time 615295332 ps
CPU time 19.7 seconds
Started Mar 10 01:08:10 PM PDT 24
Finished Mar 10 01:08:30 PM PDT 24
Peak memory 240316 kb
Host smart-a1715eb6-5525-4845-a7e4-306a14d46b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1713897690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1713897690
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.163994031
Short name T154
Test name
Test status
Simulation time 2932285092 ps
CPU time 86.3 seconds
Started Mar 10 01:08:12 PM PDT 24
Finished Mar 10 01:09:39 PM PDT 24
Peak memory 256432 kb
Host smart-c43ce823-4287-4ff1-a946-270014d31699
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=163994031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.163994031
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3048392253
Short name T707
Test name
Test status
Simulation time 167613117 ps
CPU time 11.35 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 248564 kb
Host smart-46c7e292-48fb-4e5e-8cf6-4cd0d2b44eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3048392253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3048392253
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.482302244
Short name T739
Test name
Test status
Simulation time 50778430 ps
CPU time 5.33 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:08:14 PM PDT 24
Peak memory 240268 kb
Host smart-4547ae2b-0b37-4273-8978-2bd28680d76e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482302244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.482302244
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.186955247
Short name T804
Test name
Test status
Simulation time 242280372 ps
CPU time 9.81 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 240164 kb
Host smart-8087d958-39a2-4708-a3c8-8938de3fbd80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=186955247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.186955247
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1418798864
Short name T766
Test name
Test status
Simulation time 13136527 ps
CPU time 1.25 seconds
Started Mar 10 01:08:09 PM PDT 24
Finished Mar 10 01:08:11 PM PDT 24
Peak memory 236304 kb
Host smart-7b37d7af-3aca-4807-958a-7ac44939a8ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1418798864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1418798864
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.565843097
Short name T767
Test name
Test status
Simulation time 676806278 ps
CPU time 21.44 seconds
Started Mar 10 01:08:08 PM PDT 24
Finished Mar 10 01:08:30 PM PDT 24
Peak memory 248520 kb
Host smart-67cff7ef-bb9f-4ded-9d9e-b25b8099ad67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=565843097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.565843097
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2118068328
Short name T163
Test name
Test status
Simulation time 2703154382 ps
CPU time 181.09 seconds
Started Mar 10 01:08:07 PM PDT 24
Finished Mar 10 01:11:08 PM PDT 24
Peak memory 256988 kb
Host smart-44058ae7-43ee-4669-ad9d-dfb67d34d192
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2118068328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2118068328
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3059938309
Short name T808
Test name
Test status
Simulation time 147071152 ps
CPU time 7.71 seconds
Started Mar 10 01:08:12 PM PDT 24
Finished Mar 10 01:08:20 PM PDT 24
Peak memory 248412 kb
Host smart-d868f5b3-eb8d-46f4-a885-4bfd766a979f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3059938309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3059938309
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1220485233
Short name T830
Test name
Test status
Simulation time 70294948 ps
CPU time 5.28 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:08:19 PM PDT 24
Peak memory 242796 kb
Host smart-c608b8c6-122c-4fd3-9bf6-3194788c39fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220485233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1220485233
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2528148511
Short name T709
Test name
Test status
Simulation time 91048985 ps
CPU time 5.11 seconds
Started Mar 10 01:08:15 PM PDT 24
Finished Mar 10 01:08:21 PM PDT 24
Peak memory 236244 kb
Host smart-b8723be6-01a6-46b1-9a82-2137f4658ddb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2528148511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2528148511
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2136582351
Short name T723
Test name
Test status
Simulation time 25523572 ps
CPU time 1.29 seconds
Started Mar 10 01:08:14 PM PDT 24
Finished Mar 10 01:08:16 PM PDT 24
Peak memory 235488 kb
Host smart-d2a290e3-334c-4bbf-9b65-669a9bb2d4b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2136582351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2136582351
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.24733847
Short name T203
Test name
Test status
Simulation time 1284462363 ps
CPU time 20.97 seconds
Started Mar 10 01:08:18 PM PDT 24
Finished Mar 10 01:08:40 PM PDT 24
Peak memory 240228 kb
Host smart-fa5489c2-10c5-41ee-8432-fc249551c446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=24733847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outst
anding.24733847
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.430627901
Short name T811
Test name
Test status
Simulation time 2437258272 ps
CPU time 176.34 seconds
Started Mar 10 01:08:11 PM PDT 24
Finished Mar 10 01:11:08 PM PDT 24
Peak memory 264612 kb
Host smart-043989fe-30f3-4731-949a-18361ceb13fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=430627901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.430627901
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1154865735
Short name T708
Test name
Test status
Simulation time 96639713 ps
CPU time 7.6 seconds
Started Mar 10 01:08:18 PM PDT 24
Finished Mar 10 01:08:27 PM PDT 24
Peak memory 247440 kb
Host smart-b0a8147b-a965-4bbc-80f4-30cdee250c9d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1154865735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1154865735
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.277619199
Short name T618
Test name
Test status
Simulation time 797773239 ps
CPU time 10.9 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:25 PM PDT 24
Peak memory 240808 kb
Host smart-168146cd-b3c2-4a91-b692-7f20f72f289b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=277619199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.277619199
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3402629213
Short name T593
Test name
Test status
Simulation time 3953817539 ps
CPU time 117.85 seconds
Started Mar 10 01:26:00 PM PDT 24
Finished Mar 10 01:27:59 PM PDT 24
Peak memory 248576 kb
Host smart-82f117c2-6be9-402e-ac51-24e4ca89f0cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34026
29213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3402629213
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.3408974387
Short name T615
Test name
Test status
Simulation time 356845680 ps
CPU time 10.34 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:26:21 PM PDT 24
Peak memory 254752 kb
Host smart-5dd20142-8c91-4217-abc7-14af109d1485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34089
74387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.3408974387
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3704116892
Short name T688
Test name
Test status
Simulation time 133356729335 ps
CPU time 2030.05 seconds
Started Mar 10 01:25:59 PM PDT 24
Finished Mar 10 01:59:50 PM PDT 24
Peak memory 282336 kb
Host smart-b37644e8-bf72-4a7f-a531-99bfd5147d74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704116892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3704116892
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.92184272
Short name T481
Test name
Test status
Simulation time 1901829697 ps
CPU time 59.68 seconds
Started Mar 10 01:25:53 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 248972 kb
Host smart-84b43f00-d74c-47f6-a337-1cfa6270df23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92184
272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.92184272
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3602097797
Short name T605
Test name
Test status
Simulation time 706863950 ps
CPU time 22.11 seconds
Started Mar 10 01:25:56 PM PDT 24
Finished Mar 10 01:26:19 PM PDT 24
Peak memory 247296 kb
Host smart-60d5a95b-9a49-4037-b12a-34d8224a9fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36020
97797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3602097797
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3209496027
Short name T41
Test name
Test status
Simulation time 1127649903 ps
CPU time 49.69 seconds
Started Mar 10 01:26:02 PM PDT 24
Finished Mar 10 01:26:54 PM PDT 24
Peak memory 276664 kb
Host smart-b7e845f5-f362-4656-963c-5f5eb80ceca1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3209496027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3209496027
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2748934602
Short name T361
Test name
Test status
Simulation time 557788040 ps
CPU time 33.4 seconds
Started Mar 10 01:25:56 PM PDT 24
Finished Mar 10 01:26:30 PM PDT 24
Peak memory 247476 kb
Host smart-bcf9a9bd-969b-4084-886e-e5658c20a35f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27489
34602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2748934602
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.839144575
Short name T357
Test name
Test status
Simulation time 109038332 ps
CPU time 10.17 seconds
Started Mar 10 01:25:52 PM PDT 24
Finished Mar 10 01:26:03 PM PDT 24
Peak memory 257172 kb
Host smart-b19f2239-b01a-4f32-b5fa-ff80879e54a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83914
4575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.839144575
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1400542672
Short name T452
Test name
Test status
Simulation time 126781476136 ps
CPU time 3531.7 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 02:25:03 PM PDT 24
Peak memory 289904 kb
Host smart-9236f482-0c6a-48f2-8800-4cdbaec47e30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400542672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1400542672
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.996587960
Short name T89
Test name
Test status
Simulation time 53234711791 ps
CPU time 3049.13 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 02:16:47 PM PDT 24
Peak memory 288048 kb
Host smart-eaf13763-ad44-4cc4-bd4e-95038faa0f95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996587960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.996587960
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1309563513
Short name T405
Test name
Test status
Simulation time 2011756391 ps
CPU time 69.53 seconds
Started Mar 10 01:25:55 PM PDT 24
Finished Mar 10 01:27:05 PM PDT 24
Peak memory 240808 kb
Host smart-715751fc-c57e-41b6-a30c-91bb5f8996ba
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1309563513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1309563513
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.345352000
Short name T191
Test name
Test status
Simulation time 5606405653 ps
CPU time 161.35 seconds
Started Mar 10 01:26:06 PM PDT 24
Finished Mar 10 01:28:48 PM PDT 24
Peak memory 256688 kb
Host smart-95a8b171-05a1-4fdd-b773-0873ea5d7ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
2000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.345352000
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1200753178
Short name T67
Test name
Test status
Simulation time 806574708 ps
CPU time 35.03 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 255156 kb
Host smart-78854c19-21e2-481d-a299-f141fa69f40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12007
53178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1200753178
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.291795975
Short name T471
Test name
Test status
Simulation time 8041789501 ps
CPU time 683.13 seconds
Started Mar 10 01:26:03 PM PDT 24
Finished Mar 10 01:37:29 PM PDT 24
Peak memory 268616 kb
Host smart-ab26dac4-2000-4d54-b4d0-56823a48eea1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291795975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.291795975
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.595096531
Short name T606
Test name
Test status
Simulation time 31615309743 ps
CPU time 204.38 seconds
Started Mar 10 01:26:00 PM PDT 24
Finished Mar 10 01:29:25 PM PDT 24
Peak memory 247724 kb
Host smart-ce04f30e-d157-4e78-bc07-14b8fbf7db9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595096531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.595096531
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.565482499
Short name T510
Test name
Test status
Simulation time 886193141 ps
CPU time 30.44 seconds
Started Mar 10 01:26:01 PM PDT 24
Finished Mar 10 01:26:31 PM PDT 24
Peak memory 255840 kb
Host smart-ce8c7ee4-1a7a-44b5-8d1e-f36d63cc4184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56548
2499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.565482499
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1167176719
Short name T46
Test name
Test status
Simulation time 505167196 ps
CPU time 24.31 seconds
Started Mar 10 01:26:06 PM PDT 24
Finished Mar 10 01:26:31 PM PDT 24
Peak memory 255256 kb
Host smart-b3427411-efcf-41c8-abd6-ec7a81c3f9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11671
76719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1167176719
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.705731747
Short name T4
Test name
Test status
Simulation time 719379619 ps
CPU time 26.42 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 264344 kb
Host smart-739fea47-3a19-4d9c-9ed1-2033a20dd67a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=705731747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.705731747
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2156713210
Short name T608
Test name
Test status
Simulation time 169547128 ps
CPU time 10.29 seconds
Started Mar 10 01:25:58 PM PDT 24
Finished Mar 10 01:26:08 PM PDT 24
Peak memory 253632 kb
Host smart-08402288-ebc4-4f5f-af9b-f46beea782fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21567
13210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2156713210
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.3330877684
Short name T103
Test name
Test status
Simulation time 32510836474 ps
CPU time 2124.81 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 02:01:36 PM PDT 24
Peak memory 289980 kb
Host smart-d62aded3-eaea-43bc-b7be-1f400e5e20e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330877684 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.3330877684
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1399859021
Short name T599
Test name
Test status
Simulation time 45181625760 ps
CPU time 2706.75 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 02:11:31 PM PDT 24
Peak memory 289488 kb
Host smart-fb048f04-a0e7-4fec-9d4f-8bd024510e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399859021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1399859021
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.718486875
Short name T460
Test name
Test status
Simulation time 711499104 ps
CPU time 30.11 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:50 PM PDT 24
Peak memory 240784 kb
Host smart-0a8a85d3-0665-4f2e-86f2-57cfbaa0824b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=718486875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.718486875
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2117879058
Short name T542
Test name
Test status
Simulation time 7663266658 ps
CPU time 142.88 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:28:41 PM PDT 24
Peak memory 256512 kb
Host smart-61bf7dcb-d406-49a1-8bd3-4bd44cc526e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21178
79058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2117879058
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3679113574
Short name T550
Test name
Test status
Simulation time 829500409 ps
CPU time 18.54 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:37 PM PDT 24
Peak memory 248464 kb
Host smart-5b236321-660d-46dd-812c-e22fe28e6fc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
13574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3679113574
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.988712469
Short name T376
Test name
Test status
Simulation time 32216531447 ps
CPU time 1291.83 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:47:49 PM PDT 24
Peak memory 287960 kb
Host smart-1b658aee-5b22-48e0-b202-75c6f2c10b2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988712469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.988712469
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2748322368
Short name T391
Test name
Test status
Simulation time 576357768 ps
CPU time 36.06 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:54 PM PDT 24
Peak memory 248980 kb
Host smart-af531e97-2b3f-4a93-af47-2e103adb6196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27483
22368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2748322368
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.52553382
Short name T571
Test name
Test status
Simulation time 542064194 ps
CPU time 32.55 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 253992 kb
Host smart-07b9285d-c70a-443b-b9cc-381cbf50a592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52553
382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.52553382
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1376790290
Short name T496
Test name
Test status
Simulation time 1024448164 ps
CPU time 30.83 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 247336 kb
Host smart-559fe41e-23f0-4bee-bcb6-5d5e1697b412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13767
90290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1376790290
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2870169659
Short name T106
Test name
Test status
Simulation time 2758381036 ps
CPU time 41.22 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:58 PM PDT 24
Peak memory 249064 kb
Host smart-14884f5b-8c4e-44a3-a477-499f3b5ab4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28701
69659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2870169659
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1441031424
Short name T125
Test name
Test status
Simulation time 53406438100 ps
CPU time 3239.81 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 02:20:17 PM PDT 24
Peak memory 303052 kb
Host smart-6d45b610-f19b-4c6c-862d-9db9c74f8fcc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441031424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1441031424
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3164101017
Short name T230
Test name
Test status
Simulation time 486607052 ps
CPU time 3.93 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:25 PM PDT 24
Peak memory 249172 kb
Host smart-93500a24-ec35-47d3-ab6c-792e7051c0c9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3164101017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3164101017
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1000991804
Short name T482
Test name
Test status
Simulation time 478414236 ps
CPU time 17.07 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:38 PM PDT 24
Peak memory 240772 kb
Host smart-ba235e7e-3bcd-4dc8-9a93-1faad391c1a9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1000991804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1000991804
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3846390172
Short name T629
Test name
Test status
Simulation time 4931431733 ps
CPU time 264.3 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:30:45 PM PDT 24
Peak memory 257188 kb
Host smart-4cb9d594-3918-403a-b473-6f7b3dbdaf28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38463
90172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3846390172
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1690478677
Short name T580
Test name
Test status
Simulation time 1267077239 ps
CPU time 18.22 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 254092 kb
Host smart-cb748170-1274-4968-8268-aae985a23ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16904
78677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1690478677
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.33025485
Short name T72
Test name
Test status
Simulation time 48321549693 ps
CPU time 2907.76 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 02:14:46 PM PDT 24
Peak memory 288040 kb
Host smart-41bd463d-a9e4-4615-ae6d-faaba0a5ed0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33025485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.33025485
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3438064944
Short name T446
Test name
Test status
Simulation time 55880880462 ps
CPU time 3148.74 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 02:18:52 PM PDT 24
Peak memory 289088 kb
Host smart-d13ed7fb-20a5-4a8a-a9a9-cf96433e6b29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438064944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3438064944
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2200378022
Short name T308
Test name
Test status
Simulation time 24944094962 ps
CPU time 525.41 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:35:02 PM PDT 24
Peak memory 247044 kb
Host smart-7dccc9e3-d968-4f47-8370-c5338f295a81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200378022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2200378022
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.402049651
Short name T371
Test name
Test status
Simulation time 2079710508 ps
CPU time 21.66 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:38 PM PDT 24
Peak memory 249000 kb
Host smart-eb7e93fd-2700-4870-906b-77145ffb6b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
9651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.402049651
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.1444066196
Short name T403
Test name
Test status
Simulation time 2125423350 ps
CPU time 27.51 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:48 PM PDT 24
Peak memory 255440 kb
Host smart-7ce7fa76-db71-46bc-9594-62d22aaeb107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
66196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.1444066196
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.202621662
Short name T263
Test name
Test status
Simulation time 3990621232 ps
CPU time 35.84 seconds
Started Mar 10 01:26:22 PM PDT 24
Finished Mar 10 01:26:58 PM PDT 24
Peak memory 247840 kb
Host smart-bfe20f4f-3e26-457f-9b27-a470baa515e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
1662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.202621662
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3606621363
Short name T369
Test name
Test status
Simulation time 815780254 ps
CPU time 50.3 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:27:07 PM PDT 24
Peak memory 257168 kb
Host smart-19d79c1b-6114-429c-abe4-a05a61fd6533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36066
21363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3606621363
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1633510321
Short name T516
Test name
Test status
Simulation time 66974856481 ps
CPU time 1953.27 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:58:54 PM PDT 24
Peak memory 271772 kb
Host smart-69024219-93de-4467-8f04-d25c0e658b03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633510321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1633510321
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.631722352
Short name T251
Test name
Test status
Simulation time 159198624606 ps
CPU time 2743.56 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 02:12:10 PM PDT 24
Peak memory 289712 kb
Host smart-3498ed45-eb38-40a9-848c-9f2852c37f02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631722352 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.631722352
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.268885871
Short name T219
Test name
Test status
Simulation time 36229807 ps
CPU time 3.4 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 01:26:29 PM PDT 24
Peak memory 249180 kb
Host smart-b6bf7247-a87c-43b5-912d-54ecce843d6e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=268885871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.268885871
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3152482911
Short name T546
Test name
Test status
Simulation time 15710423261 ps
CPU time 1441.4 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:50:26 PM PDT 24
Peak memory 287292 kb
Host smart-3df0e437-eff8-4d49-82bd-5e02a582fbd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152482911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3152482911
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.846932252
Short name T643
Test name
Test status
Simulation time 423678653 ps
CPU time 10.74 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:32 PM PDT 24
Peak memory 240708 kb
Host smart-380d4a81-3a07-42f1-9836-2f3e265ae0fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=846932252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.846932252
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3908506591
Short name T412
Test name
Test status
Simulation time 5961751472 ps
CPU time 93.56 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:27:54 PM PDT 24
Peak memory 256508 kb
Host smart-d7d7dbf3-3393-4680-9c43-8e75d0e3dbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39085
06591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3908506591
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3356669611
Short name T409
Test name
Test status
Simulation time 276593160 ps
CPU time 12.12 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:31 PM PDT 24
Peak memory 251800 kb
Host smart-d34ee7f2-ffdc-491a-b3c0-df7de43730ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33566
69611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3356669611
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3204786052
Short name T8
Test name
Test status
Simulation time 7825037016 ps
CPU time 715.46 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:38:12 PM PDT 24
Peak memory 273264 kb
Host smart-75033b8e-c2cc-4ee7-9db6-1933885df822
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204786052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3204786052
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.31784797
Short name T3
Test name
Test status
Simulation time 147781918805 ps
CPU time 1518.47 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:51:39 PM PDT 24
Peak memory 289156 kb
Host smart-90ca2a70-5e20-4fcb-8edb-87bf1dc90d4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31784797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.31784797
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3283569509
Short name T18
Test name
Test status
Simulation time 18770599754 ps
CPU time 356.96 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:32:16 PM PDT 24
Peak memory 247640 kb
Host smart-45478efb-1b20-4566-b5ab-3ea9cafb5485
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283569509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3283569509
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1190715966
Short name T105
Test name
Test status
Simulation time 726917356 ps
CPU time 43.63 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:27:02 PM PDT 24
Peak memory 248944 kb
Host smart-9aa7f6eb-947f-408a-847a-e6e38bcb0584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11907
15966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1190715966
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.212368236
Short name T656
Test name
Test status
Simulation time 1795986549 ps
CPU time 49.03 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:27:09 PM PDT 24
Peak memory 256460 kb
Host smart-5ef837fb-b3f2-42e9-8789-9db10bd311ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21236
8236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.212368236
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.2501169966
Short name T515
Test name
Test status
Simulation time 432681816 ps
CPU time 27.66 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:26:52 PM PDT 24
Peak memory 254820 kb
Host smart-1f50c801-78b2-4a1d-a8ea-530f9b21bf26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25011
69966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.2501169966
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2495184763
Short name T215
Test name
Test status
Simulation time 49010018 ps
CPU time 4.07 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:26:37 PM PDT 24
Peak memory 249148 kb
Host smart-74bd0813-685d-4026-809e-accb72a192fe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2495184763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2495184763
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.3440962324
Short name T614
Test name
Test status
Simulation time 76565684729 ps
CPU time 2282.32 seconds
Started Mar 10 01:26:25 PM PDT 24
Finished Mar 10 02:04:28 PM PDT 24
Peak memory 288664 kb
Host smart-6a5ee161-81f9-4049-b7b6-0ad2f83a51bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440962324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3440962324
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.756149329
Short name T652
Test name
Test status
Simulation time 372334570 ps
CPU time 9.52 seconds
Started Mar 10 01:26:27 PM PDT 24
Finished Mar 10 01:26:36 PM PDT 24
Peak memory 240616 kb
Host smart-8bad5fac-f590-4335-b485-9d3885e7bd39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=756149329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.756149329
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4155603359
Short name T598
Test name
Test status
Simulation time 418700471 ps
CPU time 24.36 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:26:45 PM PDT 24
Peak memory 248544 kb
Host smart-1f1ede55-7520-45a7-9a0d-67d3d145e0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41556
03359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4155603359
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2592821892
Short name T397
Test name
Test status
Simulation time 460798070 ps
CPU time 32.92 seconds
Started Mar 10 01:26:25 PM PDT 24
Finished Mar 10 01:26:58 PM PDT 24
Peak memory 255380 kb
Host smart-cdf3cc92-63b7-413d-9792-de2201ce1d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25928
21892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2592821892
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.241380553
Short name T324
Test name
Test status
Simulation time 135144522571 ps
CPU time 1868.99 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:57:40 PM PDT 24
Peak memory 272712 kb
Host smart-9aa6a993-116c-4b4e-b03f-c18873e8f61c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241380553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.241380553
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.3885611779
Short name T507
Test name
Test status
Simulation time 27753584160 ps
CPU time 718.45 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:38:29 PM PDT 24
Peak memory 268516 kb
Host smart-e4cbd7ce-55c3-43fe-9eca-f0e6febc724c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885611779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3885611779
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1533257587
Short name T530
Test name
Test status
Simulation time 133068669832 ps
CPU time 402.07 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 01:33:15 PM PDT 24
Peak memory 246984 kb
Host smart-f98a7c68-f907-42d4-881e-9907cb59dbcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533257587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1533257587
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3746551786
Short name T647
Test name
Test status
Simulation time 5107620350 ps
CPU time 69.97 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 01:27:33 PM PDT 24
Peak memory 249048 kb
Host smart-552c6554-592b-42b4-a130-d8dc24dd665f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37465
51786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3746551786
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.520971690
Short name T280
Test name
Test status
Simulation time 3826460433 ps
CPU time 31.85 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:52 PM PDT 24
Peak memory 255320 kb
Host smart-49b613d6-8549-4da3-a38d-4bd233800616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52097
1690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.520971690
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2215473847
Short name T365
Test name
Test status
Simulation time 1967400325 ps
CPU time 36.6 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:55 PM PDT 24
Peak memory 255232 kb
Host smart-f6cbdd05-2922-43d1-81c6-e3fee295e131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22154
73847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2215473847
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1142850881
Short name T400
Test name
Test status
Simulation time 2276765726 ps
CPU time 60.79 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:27:19 PM PDT 24
Peak memory 249056 kb
Host smart-1dec392a-546e-4ac3-90de-250bc66573e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11428
50881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1142850881
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3890943328
Short name T254
Test name
Test status
Simulation time 40461013161 ps
CPU time 2422.86 seconds
Started Mar 10 01:26:46 PM PDT 24
Finished Mar 10 02:07:10 PM PDT 24
Peak memory 289384 kb
Host smart-5663d258-0cd0-4a31-b1c9-704bfd32fa71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890943328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3890943328
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3182769135
Short name T514
Test name
Test status
Simulation time 198632025988 ps
CPU time 2871.64 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 02:14:20 PM PDT 24
Peak memory 306016 kb
Host smart-21a0ba2a-9ceb-4d57-8e70-451d6ab0f4bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182769135 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3182769135
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.806356156
Short name T229
Test name
Test status
Simulation time 102511427 ps
CPU time 3.18 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 249112 kb
Host smart-312e637d-e638-4b1d-8010-5fd340ee895a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=806356156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.806356156
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3478769484
Short name T479
Test name
Test status
Simulation time 16749647420 ps
CPU time 1464.44 seconds
Started Mar 10 01:26:21 PM PDT 24
Finished Mar 10 01:50:46 PM PDT 24
Peak memory 289216 kb
Host smart-386c5d48-25d3-4dc4-9097-39ebc42736b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478769484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3478769484
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.356138125
Short name T450
Test name
Test status
Simulation time 144516042 ps
CPU time 9.42 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 01:26:33 PM PDT 24
Peak memory 240808 kb
Host smart-d227590d-f6db-4919-9204-f339db73458c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=356138125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.356138125
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.396819795
Short name T569
Test name
Test status
Simulation time 1121144492 ps
CPU time 97.34 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:28:06 PM PDT 24
Peak memory 256588 kb
Host smart-e7a7a195-dc76-4c23-a277-c2640db707d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39681
9795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.396819795
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3330418071
Short name T433
Test name
Test status
Simulation time 1685326748 ps
CPU time 25.79 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 01:26:52 PM PDT 24
Peak memory 254632 kb
Host smart-51e64456-4728-4722-8c79-f7d92503e3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33304
18071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3330418071
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.812912132
Short name T331
Test name
Test status
Simulation time 828912856703 ps
CPU time 2212.19 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 02:03:16 PM PDT 24
Peak memory 282220 kb
Host smart-f668611a-c319-4b8d-97d7-e89071c4af2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812912132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.812912132
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3255849817
Short name T275
Test name
Test status
Simulation time 133941898224 ps
CPU time 2272.8 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 02:04:27 PM PDT 24
Peak memory 273640 kb
Host smart-4d8e79fb-e2f4-4a90-907c-a7660208696a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255849817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3255849817
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1340671876
Short name T439
Test name
Test status
Simulation time 310338598 ps
CPU time 11.49 seconds
Started Mar 10 01:26:27 PM PDT 24
Finished Mar 10 01:26:39 PM PDT 24
Peak memory 254472 kb
Host smart-c5963333-368f-418e-8c44-ac7490242063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
71876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1340671876
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.3843335472
Short name T513
Test name
Test status
Simulation time 112031827 ps
CPU time 15 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 255088 kb
Host smart-15f7c872-963a-4469-9433-cb9f6e2176e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38433
35472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.3843335472
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1620788825
Short name T265
Test name
Test status
Simulation time 2886000257 ps
CPU time 18.85 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:26:52 PM PDT 24
Peak memory 255116 kb
Host smart-9d885cf7-85ec-42df-aebf-199e59c05eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16207
88825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1620788825
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.117142053
Short name T456
Test name
Test status
Simulation time 1233127648 ps
CPU time 26.21 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 255560 kb
Host smart-80839cc9-0241-4610-86cd-565d543515aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11714
2053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.117142053
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3134238198
Short name T49
Test name
Test status
Simulation time 277755884653 ps
CPU time 4667.03 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 02:44:12 PM PDT 24
Peak memory 315648 kb
Host smart-a8ce059a-60dd-49af-8a5e-563528fef387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134238198 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3134238198
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1097655356
Short name T100
Test name
Test status
Simulation time 10761030063 ps
CPU time 1354.22 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 01:49:06 PM PDT 24
Peak memory 289220 kb
Host smart-7307f70d-c17a-4987-82cb-41ba63786090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097655356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1097655356
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3577489294
Short name T393
Test name
Test status
Simulation time 1880198100 ps
CPU time 76.11 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:27:59 PM PDT 24
Peak memory 248948 kb
Host smart-a5c45365-4527-42f2-ae89-ef2808b4661f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3577489294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3577489294
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1093705843
Short name T464
Test name
Test status
Simulation time 1697979963 ps
CPU time 147.35 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 01:28:54 PM PDT 24
Peak memory 256212 kb
Host smart-516927c9-174d-476d-9ecd-9cc6ad7b0608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
05843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1093705843
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.112508585
Short name T498
Test name
Test status
Simulation time 134446828 ps
CPU time 11.84 seconds
Started Mar 10 01:26:29 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 254144 kb
Host smart-459f54b9-f7c2-4ece-b9bd-adadd0b0281d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11250
8585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.112508585
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.432380823
Short name T667
Test name
Test status
Simulation time 7664526130 ps
CPU time 899.54 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:41:38 PM PDT 24
Peak memory 273516 kb
Host smart-e79cb3d2-f438-4532-a716-bed862f9f2c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432380823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.432380823
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2445438258
Short name T17
Test name
Test status
Simulation time 11253039809 ps
CPU time 225.03 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:30:09 PM PDT 24
Peak memory 246912 kb
Host smart-381d0993-9219-43d4-b069-2ce28d8ec6a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445438258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2445438258
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2554067605
Short name T42
Test name
Test status
Simulation time 111726106 ps
CPU time 8.52 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:26:38 PM PDT 24
Peak memory 240808 kb
Host smart-0b5a4145-3e01-4800-b8c9-e0d44be11491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25540
67605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2554067605
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3878512919
Short name T521
Test name
Test status
Simulation time 573108774 ps
CPU time 36.71 seconds
Started Mar 10 01:26:36 PM PDT 24
Finished Mar 10 01:27:13 PM PDT 24
Peak memory 249008 kb
Host smart-10439d5c-2955-4813-93be-992ca79897d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38785
12919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3878512919
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.120867027
Short name T538
Test name
Test status
Simulation time 227152751 ps
CPU time 25.76 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:27:00 PM PDT 24
Peak memory 247332 kb
Host smart-7aef85fc-b3b6-4c92-99a1-927aed34cff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12086
7027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.120867027
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.732576409
Short name T443
Test name
Test status
Simulation time 392784628 ps
CPU time 11.02 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 01:26:34 PM PDT 24
Peak memory 248952 kb
Host smart-5a13792a-6713-4911-aa23-c31149b6f76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73257
6409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.732576409
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2934521588
Short name T24
Test name
Test status
Simulation time 31694680 ps
CPU time 3.4 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:34 PM PDT 24
Peak memory 249168 kb
Host smart-fe7bcbf8-580f-4e3b-bd2e-3193b7730b81
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2934521588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2934521588
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3175397634
Short name T13
Test name
Test status
Simulation time 51450263347 ps
CPU time 1002.73 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:43:13 PM PDT 24
Peak memory 273552 kb
Host smart-cbd2b5b4-20c8-4a4f-aff2-df1c7152a8ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175397634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3175397634
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.3565835449
Short name T476
Test name
Test status
Simulation time 314803627 ps
CPU time 9.52 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 01:26:46 PM PDT 24
Peak memory 240748 kb
Host smart-15c64dff-6b1e-4534-ab55-c77efecc9c21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3565835449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.3565835449
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3653037792
Short name T458
Test name
Test status
Simulation time 1467085847 ps
CPU time 24.49 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 255696 kb
Host smart-066cd5e8-e31e-426f-9085-70e0df621ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36530
37792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3653037792
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4181640159
Short name T413
Test name
Test status
Simulation time 806468613 ps
CPU time 12.56 seconds
Started Mar 10 01:26:27 PM PDT 24
Finished Mar 10 01:26:40 PM PDT 24
Peak memory 252236 kb
Host smart-9c2242a5-cf8d-41f0-999f-0207afab9be8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41816
40159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4181640159
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4149493619
Short name T549
Test name
Test status
Simulation time 92527723519 ps
CPU time 2742.97 seconds
Started Mar 10 01:26:47 PM PDT 24
Finished Mar 10 02:12:30 PM PDT 24
Peak memory 273508 kb
Host smart-00722e0c-6dcd-455f-80fc-dbfda708cccf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149493619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4149493619
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.273175820
Short name T572
Test name
Test status
Simulation time 645406890231 ps
CPU time 3287.99 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 02:21:14 PM PDT 24
Peak memory 289712 kb
Host smart-062c65e6-6351-4a2f-ab33-ca7328864b06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273175820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.273175820
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2199882955
Short name T312
Test name
Test status
Simulation time 21685976963 ps
CPU time 228.24 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 01:30:14 PM PDT 24
Peak memory 247676 kb
Host smart-291ff5fc-debe-4321-9ab3-5ffbb47d717f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199882955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2199882955
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2744335148
Short name T487
Test name
Test status
Simulation time 4118629620 ps
CPU time 61.03 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:27:29 PM PDT 24
Peak memory 249188 kb
Host smart-1199ce6c-fc82-4458-8d6d-e8afb41719fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27443
35148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2744335148
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1807092436
Short name T478
Test name
Test status
Simulation time 958459332 ps
CPU time 17.4 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 255252 kb
Host smart-b5b5337e-83ed-4954-9bfa-54e095d6bff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18070
92436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1807092436
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.4266529181
Short name T554
Test name
Test status
Simulation time 1206543153 ps
CPU time 41.69 seconds
Started Mar 10 01:26:25 PM PDT 24
Finished Mar 10 01:27:06 PM PDT 24
Peak memory 248988 kb
Host smart-d4d9d17f-3430-478b-b04a-59ec212fba61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42665
29181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.4266529181
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.2465874874
Short name T671
Test name
Test status
Simulation time 691907849 ps
CPU time 36.84 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:27:08 PM PDT 24
Peak memory 249088 kb
Host smart-f4e8f52f-1c4b-465a-861b-ca9e28a13189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24658
74874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.2465874874
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2707685597
Short name T666
Test name
Test status
Simulation time 635635324 ps
CPU time 37.5 seconds
Started Mar 10 01:26:44 PM PDT 24
Finished Mar 10 01:27:22 PM PDT 24
Peak memory 249012 kb
Host smart-35493e31-a0de-4e5a-8e87-834cdcc16ead
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707685597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2707685597
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2684567250
Short name T217
Test name
Test status
Simulation time 52910694 ps
CPU time 4.32 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 249104 kb
Host smart-9aa30329-f29b-45cb-8945-a7fa735901ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2684567250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2684567250
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2536051542
Short name T116
Test name
Test status
Simulation time 45385705105 ps
CPU time 1264.16 seconds
Started Mar 10 01:26:27 PM PDT 24
Finished Mar 10 01:47:32 PM PDT 24
Peak memory 287068 kb
Host smart-82f76e55-9c34-4a49-9506-385b9b5a6c55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536051542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2536051542
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2439713980
Short name T401
Test name
Test status
Simulation time 36071967818 ps
CPU time 173.98 seconds
Started Mar 10 01:26:35 PM PDT 24
Finished Mar 10 01:29:29 PM PDT 24
Peak memory 249072 kb
Host smart-425f5837-d37f-4332-b6c4-ccb9dc9e8f83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24397
13980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2439713980
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2443890882
Short name T607
Test name
Test status
Simulation time 2245418433 ps
CPU time 67.28 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:27:46 PM PDT 24
Peak memory 254880 kb
Host smart-61cf149f-9405-4f9a-9186-9208830eb02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
90882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2443890882
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2244617656
Short name T16
Test name
Test status
Simulation time 28188557943 ps
CPU time 1766.1 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:55:57 PM PDT 24
Peak memory 273320 kb
Host smart-67cd3108-e5d1-4402-8f93-fede9d789abe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244617656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2244617656
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2706602412
Short name T366
Test name
Test status
Simulation time 57246406161 ps
CPU time 1152.16 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:45:41 PM PDT 24
Peak memory 273120 kb
Host smart-6569f78d-7962-4432-8136-3f5b5cf42775
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706602412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2706602412
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.347622937
Short name T429
Test name
Test status
Simulation time 21211852629 ps
CPU time 220.96 seconds
Started Mar 10 01:26:36 PM PDT 24
Finished Mar 10 01:30:17 PM PDT 24
Peak memory 247724 kb
Host smart-a2911f69-0639-4378-976c-ece8b4c228c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347622937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.347622937
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.915802206
Short name T197
Test name
Test status
Simulation time 591765311 ps
CPU time 15.53 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:26:43 PM PDT 24
Peak memory 254856 kb
Host smart-eef82469-c802-4e81-9a29-edc237c2f90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91580
2206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.915802206
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3048673964
Short name T447
Test name
Test status
Simulation time 345240299 ps
CPU time 11.24 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:26:45 PM PDT 24
Peak memory 253716 kb
Host smart-6b6ce5a4-8c85-4099-97a4-3064ee3a19f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30486
73964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3048673964
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.4207462638
Short name T621
Test name
Test status
Simulation time 438106025 ps
CPU time 9.46 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 253208 kb
Host smart-1e4bad64-8f71-4bd0-84aa-34c1c8902b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42074
62638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.4207462638
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1194770701
Short name T380
Test name
Test status
Simulation time 820881497 ps
CPU time 48.29 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:27:30 PM PDT 24
Peak memory 256012 kb
Host smart-da71c116-4b5a-43ff-8f01-7539c636f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11947
70701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1194770701
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2565656501
Short name T198
Test name
Test status
Simulation time 429026247335 ps
CPU time 8117.82 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 03:42:02 PM PDT 24
Peak memory 322212 kb
Host smart-c7ec507e-b4ae-41eb-bd4d-0fc96cb1952d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565656501 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2565656501
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1565429426
Short name T218
Test name
Test status
Simulation time 256094419 ps
CPU time 3.52 seconds
Started Mar 10 01:26:44 PM PDT 24
Finished Mar 10 01:26:48 PM PDT 24
Peak memory 249160 kb
Host smart-2652115d-4097-442e-88ec-95d9901d51af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1565429426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1565429426
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.865054601
Short name T492
Test name
Test status
Simulation time 520883794 ps
CPU time 14.29 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:45 PM PDT 24
Peak memory 240780 kb
Host smart-a671f9ad-905c-45e0-beb8-8d7a18ea9ebd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=865054601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.865054601
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1345106836
Short name T474
Test name
Test status
Simulation time 5557513580 ps
CPU time 320.24 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:31:51 PM PDT 24
Peak memory 256352 kb
Host smart-2898eeee-53f4-4383-9591-d460e4522da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13451
06836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1345106836
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3623415872
Short name T427
Test name
Test status
Simulation time 2279483082 ps
CPU time 38.7 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:27:17 PM PDT 24
Peak memory 255368 kb
Host smart-188a0e29-ddab-45d1-82e0-314caba2de88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36234
15872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3623415872
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3037428860
Short name T573
Test name
Test status
Simulation time 75957437982 ps
CPU time 1716.45 seconds
Started Mar 10 01:26:27 PM PDT 24
Finished Mar 10 01:55:04 PM PDT 24
Peak memory 273408 kb
Host smart-99962a84-a5a8-4d63-ac16-1fee6c1e0b5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037428860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3037428860
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2375478606
Short name T528
Test name
Test status
Simulation time 172154075408 ps
CPU time 1096.21 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:44:46 PM PDT 24
Peak memory 289368 kb
Host smart-0305df97-4469-4512-9931-4ddf2ddaafb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375478606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2375478606
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1772668564
Short name T317
Test name
Test status
Simulation time 9760392540 ps
CPU time 384.52 seconds
Started Mar 10 01:26:29 PM PDT 24
Finished Mar 10 01:32:54 PM PDT 24
Peak memory 247960 kb
Host smart-79c5c9c8-8fc0-40f9-a80e-42fbcc6fd5de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772668564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1772668564
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1540910655
Short name T408
Test name
Test status
Simulation time 774204595 ps
CPU time 42.73 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:27:11 PM PDT 24
Peak memory 255760 kb
Host smart-ab5fb062-3cb0-427c-80f9-8f5528dbb424
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15409
10655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1540910655
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.919789317
Short name T244
Test name
Test status
Simulation time 3979687955 ps
CPU time 27.43 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:26:56 PM PDT 24
Peak memory 256324 kb
Host smart-f9c2d35d-995f-4295-979a-5de332155f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91978
9317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.919789317
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2089860430
Short name T541
Test name
Test status
Simulation time 1805007746 ps
CPU time 26.61 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:27:01 PM PDT 24
Peak memory 247360 kb
Host smart-32853cab-36c2-4c70-8d36-73cbafa5d1d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898
60430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2089860430
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2565543396
Short name T495
Test name
Test status
Simulation time 253308729 ps
CPU time 21.23 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:26:55 PM PDT 24
Peak memory 257180 kb
Host smart-bbcf4fcb-57ff-4b98-a18c-836bb7edf70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
43396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2565543396
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1975354917
Short name T227
Test name
Test status
Simulation time 105305633 ps
CPU time 2.86 seconds
Started Mar 10 01:26:46 PM PDT 24
Finished Mar 10 01:26:50 PM PDT 24
Peak memory 249176 kb
Host smart-ccb742e5-6d49-44d1-87bd-a70b5b1584df
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1975354917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1975354917
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2489805445
Short name T435
Test name
Test status
Simulation time 38456862708 ps
CPU time 1635.2 seconds
Started Mar 10 01:26:35 PM PDT 24
Finished Mar 10 01:53:50 PM PDT 24
Peak memory 272888 kb
Host smart-2f70d832-1bf7-48c0-8621-5112a881f8a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489805445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2489805445
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1220446367
Short name T414
Test name
Test status
Simulation time 305338440 ps
CPU time 15.64 seconds
Started Mar 10 01:26:35 PM PDT 24
Finished Mar 10 01:26:51 PM PDT 24
Peak memory 248992 kb
Host smart-848510c5-36d1-4fbf-b8e4-9f56de825039
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1220446367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1220446367
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2459590052
Short name T359
Test name
Test status
Simulation time 78060725 ps
CPU time 10.48 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 255428 kb
Host smart-3dc9e030-e08d-4165-9203-d209cd926c51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24595
90052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2459590052
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3891704445
Short name T537
Test name
Test status
Simulation time 1058703262 ps
CPU time 63.57 seconds
Started Mar 10 01:26:39 PM PDT 24
Finished Mar 10 01:27:43 PM PDT 24
Peak memory 256440 kb
Host smart-fdb51c59-eecd-4a95-9e26-7b7df08cbbe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38917
04445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3891704445
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.90258501
Short name T238
Test name
Test status
Simulation time 42713274061 ps
CPU time 2613.57 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 02:10:05 PM PDT 24
Peak memory 281364 kb
Host smart-190fef0f-0d6e-4bf0-aba4-401f65764121
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90258501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.90258501
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.2206208483
Short name T609
Test name
Test status
Simulation time 34584374154 ps
CPU time 706.08 seconds
Started Mar 10 01:26:32 PM PDT 24
Finished Mar 10 01:38:19 PM PDT 24
Peak memory 265432 kb
Host smart-018dbad9-90ed-404d-b99d-98800f99b0d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206208483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.2206208483
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.4191785292
Short name T639
Test name
Test status
Simulation time 3376001610 ps
CPU time 139.12 seconds
Started Mar 10 01:26:30 PM PDT 24
Finished Mar 10 01:28:50 PM PDT 24
Peak memory 247728 kb
Host smart-1fe2c97d-3932-421e-bfda-61eb0bc17c0c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191785292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.4191785292
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2334047816
Short name T418
Test name
Test status
Simulation time 470935388 ps
CPU time 10.93 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:26:44 PM PDT 24
Peak memory 248996 kb
Host smart-aa82d4fa-8068-46a2-b9fa-6db2b85161cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23340
47816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2334047816
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.562105828
Short name T118
Test name
Test status
Simulation time 77863621 ps
CPU time 12.02 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 01:26:44 PM PDT 24
Peak memory 248612 kb
Host smart-d3b21079-da17-4d47-b83c-d3b18f91818b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56210
5828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.562105828
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.3025731599
Short name T262
Test name
Test status
Simulation time 1553462526 ps
CPU time 48.25 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:27:22 PM PDT 24
Peak memory 255212 kb
Host smart-d72b98d7-e721-4766-b6b0-152fc943672d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30257
31599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3025731599
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1111944760
Short name T545
Test name
Test status
Simulation time 5707185163 ps
CPU time 50.09 seconds
Started Mar 10 01:26:28 PM PDT 24
Finished Mar 10 01:27:18 PM PDT 24
Peak memory 255860 kb
Host smart-6eced8bc-14ab-4c56-b86f-962202d8d310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11119
44760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1111944760
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.97742379
Short name T680
Test name
Test status
Simulation time 68057811852 ps
CPU time 2148.42 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 02:02:23 PM PDT 24
Peak memory 286748 kb
Host smart-9b1b54ee-cbec-49e0-b9d2-666092bb9ea9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97742379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_hand
ler_stress_all.97742379
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1122383393
Short name T270
Test name
Test status
Simulation time 19470300275 ps
CPU time 1368.53 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 01:49:32 PM PDT 24
Peak memory 273176 kb
Host smart-de1efb55-5c11-432c-ab7c-73be4847431a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122383393 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1122383393
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1937113495
Short name T216
Test name
Test status
Simulation time 14444982 ps
CPU time 2.4 seconds
Started Mar 10 01:26:15 PM PDT 24
Finished Mar 10 01:26:17 PM PDT 24
Peak memory 249200 kb
Host smart-66db2556-a0de-4f0a-be5d-8ada46f93537
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1937113495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1937113495
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1675322691
Short name T475
Test name
Test status
Simulation time 38870067205 ps
CPU time 2409.91 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 02:06:16 PM PDT 24
Peak memory 273636 kb
Host smart-7725c234-ef55-4646-90d6-612fe2fc5d1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675322691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1675322691
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2705667272
Short name T536
Test name
Test status
Simulation time 2662824201 ps
CPU time 42.87 seconds
Started Mar 10 01:26:06 PM PDT 24
Finished Mar 10 01:26:49 PM PDT 24
Peak memory 240780 kb
Host smart-c3c9ba03-b070-4543-9359-5beb4d9f82d2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2705667272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2705667272
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1579668435
Short name T533
Test name
Test status
Simulation time 251289730 ps
CPU time 24.44 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 01:26:22 PM PDT 24
Peak memory 248368 kb
Host smart-84b4d871-19a5-4bd5-ae1a-df16b89a98da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15796
68435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1579668435
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1542484491
Short name T485
Test name
Test status
Simulation time 368426075 ps
CPU time 24.16 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 01:26:22 PM PDT 24
Peak memory 248640 kb
Host smart-f4aafb21-ced4-4e61-b2da-ede90234cf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
84491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1542484491
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1319882657
Short name T350
Test name
Test status
Simulation time 29161064302 ps
CPU time 1446.76 seconds
Started Mar 10 01:26:01 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 265392 kb
Host smart-25ebb77d-b592-4511-a769-73179a3a07e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319882657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1319882657
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4186602135
Short name T634
Test name
Test status
Simulation time 38856907698 ps
CPU time 2286.53 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 02:04:21 PM PDT 24
Peak memory 271816 kb
Host smart-a432739a-9b6e-4753-8dc8-5ddffe389673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186602135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4186602135
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2686228659
Short name T15
Test name
Test status
Simulation time 67957695073 ps
CPU time 448.91 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 01:33:34 PM PDT 24
Peak memory 247712 kb
Host smart-c99200a2-8b47-4813-98d7-d6e800b914f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686228659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2686228659
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2778357442
Short name T58
Test name
Test status
Simulation time 1875578431 ps
CPU time 60.58 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 01:26:58 PM PDT 24
Peak memory 257160 kb
Host smart-97c28d6e-99a8-4965-8565-1f06cae1acac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27783
57442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2778357442
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2438879253
Short name T494
Test name
Test status
Simulation time 1431156442 ps
CPU time 40.33 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:46 PM PDT 24
Peak memory 248472 kb
Host smart-ae00e709-9275-4581-a6cc-5f9ded8e7b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24388
79253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2438879253
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.139584657
Short name T40
Test name
Test status
Simulation time 545305228 ps
CPU time 24.96 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:43 PM PDT 24
Peak memory 277188 kb
Host smart-283e9d2d-9438-44f7-85ef-1401424da72a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=139584657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.139584657
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3335904464
Short name T684
Test name
Test status
Simulation time 661856554 ps
CPU time 38.39 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 254712 kb
Host smart-3721e181-943e-4bdb-b8bb-de4601a67666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359
04464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3335904464
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3329906444
Short name T407
Test name
Test status
Simulation time 3874679895 ps
CPU time 59.3 seconds
Started Mar 10 01:25:57 PM PDT 24
Finished Mar 10 01:26:57 PM PDT 24
Peak memory 249060 kb
Host smart-2ff9a494-32c8-409e-aad5-9e8f52296208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33299
06444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3329906444
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.120706389
Short name T704
Test name
Test status
Simulation time 3457881314 ps
CPU time 221.9 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:30:00 PM PDT 24
Peak memory 257220 kb
Host smart-f7489ae5-5095-4327-af4f-61393e351ffc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120706389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.120706389
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.3188201441
Short name T121
Test name
Test status
Simulation time 35422952569 ps
CPU time 2062.74 seconds
Started Mar 10 01:26:31 PM PDT 24
Finished Mar 10 02:00:54 PM PDT 24
Peak memory 283728 kb
Host smart-cf40b6e2-db9a-40be-a862-7ff9781fda25
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188201441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.3188201441
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.4088058756
Short name T430
Test name
Test status
Simulation time 10654061537 ps
CPU time 159.55 seconds
Started Mar 10 01:26:45 PM PDT 24
Finished Mar 10 01:29:24 PM PDT 24
Peak memory 257212 kb
Host smart-1d817374-a9a6-457f-9bf9-6b04ce54081d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40880
58756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.4088058756
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.411984573
Short name T604
Test name
Test status
Simulation time 268631427 ps
CPU time 27.49 seconds
Started Mar 10 01:26:33 PM PDT 24
Finished Mar 10 01:27:01 PM PDT 24
Peak memory 254708 kb
Host smart-097d438c-b8ac-4fb9-9b37-ce9880b08a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41198
4573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.411984573
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.1126026098
Short name T333
Test name
Test status
Simulation time 29811778517 ps
CPU time 1933.93 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 01:58:57 PM PDT 24
Peak memory 272924 kb
Host smart-f331eb01-46e5-4b83-b6fc-7a5a19bdbf03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126026098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1126026098
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.978727861
Short name T392
Test name
Test status
Simulation time 202286207290 ps
CPU time 1981.63 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 01:59:39 PM PDT 24
Peak memory 281796 kb
Host smart-2daf63dd-dadc-426a-9990-d4f48d8751d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978727861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.978727861
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.73580077
Short name T700
Test name
Test status
Simulation time 8582992539 ps
CPU time 176.99 seconds
Started Mar 10 01:26:36 PM PDT 24
Finished Mar 10 01:29:33 PM PDT 24
Peak memory 248072 kb
Host smart-e30a10ca-8ed2-4aa4-bf56-f4a66655fb7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73580077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.73580077
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1898346235
Short name T582
Test name
Test status
Simulation time 500263487 ps
CPU time 31.87 seconds
Started Mar 10 01:26:35 PM PDT 24
Finished Mar 10 01:27:07 PM PDT 24
Peak memory 249000 kb
Host smart-6ddccf6f-5ffa-4a0a-98c6-1dec0377b760
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18983
46235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1898346235
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1683045361
Short name T463
Test name
Test status
Simulation time 1384512542 ps
CPU time 30.47 seconds
Started Mar 10 01:26:34 PM PDT 24
Finished Mar 10 01:27:04 PM PDT 24
Peak memory 247444 kb
Host smart-e67840c9-e3a4-4ddc-afc2-0fd16aefc11d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16830
45361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1683045361
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3437947987
Short name T577
Test name
Test status
Simulation time 706260634 ps
CPU time 31.26 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 01:27:14 PM PDT 24
Peak memory 248948 kb
Host smart-27b619ae-5102-4874-a988-16c5db368546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
47987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3437947987
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2691841800
Short name T124
Test name
Test status
Simulation time 12093243276 ps
CPU time 884.67 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:41:23 PM PDT 24
Peak memory 273640 kb
Host smart-30c1761d-2029-49e3-9b36-0e9effaa2faa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691841800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2691841800
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.481378725
Short name T681
Test name
Test status
Simulation time 23522873577 ps
CPU time 535.67 seconds
Started Mar 10 01:26:48 PM PDT 24
Finished Mar 10 01:35:44 PM PDT 24
Peak memory 273392 kb
Host smart-ee0f37ae-d65a-4c02-b17e-a74a9b5ca069
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481378725 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.481378725
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3386932373
Short name T291
Test name
Test status
Simulation time 170929683714 ps
CPU time 2917.93 seconds
Started Mar 10 01:26:48 PM PDT 24
Finished Mar 10 02:15:26 PM PDT 24
Peak memory 289404 kb
Host smart-878bd388-41b9-405f-a15c-f28d53952b7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386932373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3386932373
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2240901074
Short name T466
Test name
Test status
Simulation time 6005877566 ps
CPU time 78.04 seconds
Started Mar 10 01:26:44 PM PDT 24
Finished Mar 10 01:28:02 PM PDT 24
Peak memory 256316 kb
Host smart-00f5627c-524a-465f-80b3-896c6e92acc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
01074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2240901074
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2541614502
Short name T78
Test name
Test status
Simulation time 937186090 ps
CPU time 54.86 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:27:37 PM PDT 24
Peak memory 255612 kb
Host smart-234a670f-bbde-42f8-9d8b-34305c646851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25416
14502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2541614502
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2376854873
Short name T336
Test name
Test status
Simulation time 14767426895 ps
CPU time 1204.72 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 01:46:42 PM PDT 24
Peak memory 286532 kb
Host smart-fb465b85-88ed-4a01-95e5-924b58e87f4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376854873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2376854873
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.1754003392
Short name T237
Test name
Test status
Simulation time 111322937507 ps
CPU time 1365.42 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:49:24 PM PDT 24
Peak memory 289716 kb
Host smart-2b52072b-5deb-4db0-a698-2a7545a0f58f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754003392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.1754003392
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3904166826
Short name T678
Test name
Test status
Simulation time 9627937088 ps
CPU time 402.58 seconds
Started Mar 10 01:26:43 PM PDT 24
Finished Mar 10 01:33:25 PM PDT 24
Peak memory 247944 kb
Host smart-39d4c872-7bbe-4abc-b040-3d8bf7f4da26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904166826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3904166826
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1155560415
Short name T453
Test name
Test status
Simulation time 57489575 ps
CPU time 6.47 seconds
Started Mar 10 01:26:39 PM PDT 24
Finished Mar 10 01:26:46 PM PDT 24
Peak memory 248952 kb
Host smart-4e2ea4e2-5068-40de-a160-ff0c762cc886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11555
60415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1155560415
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.485458510
Short name T497
Test name
Test status
Simulation time 5591482152 ps
CPU time 57.04 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:27:39 PM PDT 24
Peak memory 256508 kb
Host smart-c8b32b39-e56d-42ea-8495-4013542d0759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48545
8510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.485458510
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.327564156
Short name T274
Test name
Test status
Simulation time 9328459543 ps
CPU time 35.3 seconds
Started Mar 10 01:26:35 PM PDT 24
Finished Mar 10 01:27:11 PM PDT 24
Peak memory 249364 kb
Host smart-99fac96f-9818-4d96-b22b-97ca84a0123a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32756
4156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.327564156
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3716095736
Short name T382
Test name
Test status
Simulation time 51549490 ps
CPU time 6.53 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 01:26:43 PM PDT 24
Peak memory 252800 kb
Host smart-ab1d405a-7fc1-4c46-9d09-28c762af2746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37160
95736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3716095736
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4100115607
Short name T51
Test name
Test status
Simulation time 55194917866 ps
CPU time 1234.26 seconds
Started Mar 10 01:26:38 PM PDT 24
Finished Mar 10 01:47:12 PM PDT 24
Peak memory 289204 kb
Host smart-da3ed653-2e0a-4b3c-ab78-0b405ed6332c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100115607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4100115607
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3506462193
Short name T211
Test name
Test status
Simulation time 343416689896 ps
CPU time 3465.63 seconds
Started Mar 10 01:26:37 PM PDT 24
Finished Mar 10 02:24:23 PM PDT 24
Peak memory 338756 kb
Host smart-836e91b5-ece4-4625-9a02-161daa6b68c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506462193 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3506462193
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3294142327
Short name T469
Test name
Test status
Simulation time 23235370712 ps
CPU time 1061.97 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:44:25 PM PDT 24
Peak memory 273424 kb
Host smart-6e2f6f3d-9ca1-45be-9cbd-e5f62fd1c4ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294142327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3294142327
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3721336643
Short name T372
Test name
Test status
Simulation time 1262232475 ps
CPU time 76.07 seconds
Started Mar 10 01:26:47 PM PDT 24
Finished Mar 10 01:28:03 PM PDT 24
Peak memory 256608 kb
Host smart-44152933-509f-448c-abba-2b853dcd63b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37213
36643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3721336643
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3117332929
Short name T451
Test name
Test status
Simulation time 982639178 ps
CPU time 57.5 seconds
Started Mar 10 01:26:50 PM PDT 24
Finished Mar 10 01:27:48 PM PDT 24
Peak memory 255320 kb
Host smart-4e6db870-5ebb-4a40-933a-cd06588c5eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31173
32929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3117332929
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.295781263
Short name T484
Test name
Test status
Simulation time 82794722400 ps
CPU time 2317.06 seconds
Started Mar 10 01:26:50 PM PDT 24
Finished Mar 10 02:05:27 PM PDT 24
Peak memory 273272 kb
Host smart-43e2e6e8-d607-4246-aaeb-039a6b5ce984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295781263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.295781263
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2920710130
Short name T655
Test name
Test status
Simulation time 182696496656 ps
CPU time 2348.75 seconds
Started Mar 10 01:26:48 PM PDT 24
Finished Mar 10 02:05:57 PM PDT 24
Peak memory 289408 kb
Host smart-20e433c7-96f5-44d2-a744-e37f1ab3dcf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920710130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2920710130
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4053229466
Short name T43
Test name
Test status
Simulation time 3409593623 ps
CPU time 55.04 seconds
Started Mar 10 01:26:47 PM PDT 24
Finished Mar 10 01:27:42 PM PDT 24
Peak memory 249064 kb
Host smart-845c4664-7ae0-4db8-b916-c130b7f4341c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40532
29466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4053229466
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2079372430
Short name T661
Test name
Test status
Simulation time 548283963 ps
CPU time 10.32 seconds
Started Mar 10 01:26:44 PM PDT 24
Finished Mar 10 01:26:54 PM PDT 24
Peak memory 251032 kb
Host smart-a6b7ec34-fd20-4d4d-ae82-137d139ff4c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20793
72430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2079372430
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.1011718688
Short name T258
Test name
Test status
Simulation time 1201397591 ps
CPU time 40.77 seconds
Started Mar 10 01:26:45 PM PDT 24
Finished Mar 10 01:27:26 PM PDT 24
Peak memory 255392 kb
Host smart-4a2dfc5d-7b95-4f30-ba28-62aa9d91f20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10117
18688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1011718688
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4216678838
Short name T602
Test name
Test status
Simulation time 128463687 ps
CPU time 11.12 seconds
Started Mar 10 01:26:42 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 249108 kb
Host smart-c4219860-fe0f-4e9e-a64a-0573e9116313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42166
78838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4216678838
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.399287109
Short name T114
Test name
Test status
Simulation time 92516752326 ps
CPU time 1539.37 seconds
Started Mar 10 01:26:48 PM PDT 24
Finished Mar 10 01:52:28 PM PDT 24
Peak memory 290060 kb
Host smart-97d0abbd-de3d-49e3-a28d-a9b1bdc6abfe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399287109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.399287109
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.3233293433
Short name T127
Test name
Test status
Simulation time 50968351769 ps
CPU time 5229.34 seconds
Started Mar 10 01:26:55 PM PDT 24
Finished Mar 10 02:54:06 PM PDT 24
Peak memory 331056 kb
Host smart-22d29889-2927-4c08-8f8b-eae7eef54ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233293433 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.3233293433
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.198626016
Short name T468
Test name
Test status
Simulation time 66403910124 ps
CPU time 1613.16 seconds
Started Mar 10 01:26:51 PM PDT 24
Finished Mar 10 01:53:45 PM PDT 24
Peak memory 289824 kb
Host smart-2c66d3d3-24e2-42f1-917d-49758010210c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198626016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.198626016
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1463873543
Short name T352
Test name
Test status
Simulation time 8891591711 ps
CPU time 222.26 seconds
Started Mar 10 01:26:49 PM PDT 24
Finished Mar 10 01:30:32 PM PDT 24
Peak memory 256748 kb
Host smart-7442586f-81fb-47d0-84e6-ee265d53268e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14638
73543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1463873543
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.2083719216
Short name T387
Test name
Test status
Simulation time 3187250101 ps
CPU time 33.44 seconds
Started Mar 10 01:26:52 PM PDT 24
Finished Mar 10 01:27:26 PM PDT 24
Peak memory 255928 kb
Host smart-0e786821-7eb6-4078-97ef-cd75bcd608a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20837
19216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.2083719216
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2741160369
Short name T334
Test name
Test status
Simulation time 5759188112 ps
CPU time 606.14 seconds
Started Mar 10 01:26:54 PM PDT 24
Finished Mar 10 01:37:00 PM PDT 24
Peak memory 271112 kb
Host smart-92ea981e-c440-48b8-afa9-0315f3329881
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741160369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2741160369
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.614003847
Short name T690
Test name
Test status
Simulation time 13182862557 ps
CPU time 804.21 seconds
Started Mar 10 01:26:50 PM PDT 24
Finished Mar 10 01:40:15 PM PDT 24
Peak memory 272616 kb
Host smart-cd08e080-40c6-4cf6-a972-d5f185ec184b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614003847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.614003847
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2751370499
Short name T249
Test name
Test status
Simulation time 33062935428 ps
CPU time 371.68 seconds
Started Mar 10 01:26:53 PM PDT 24
Finished Mar 10 01:33:05 PM PDT 24
Peak memory 246996 kb
Host smart-8f47a096-1142-4401-ac50-6fa7914de4e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751370499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2751370499
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.342748746
Short name T592
Test name
Test status
Simulation time 432934445 ps
CPU time 20.59 seconds
Started Mar 10 01:26:49 PM PDT 24
Finished Mar 10 01:27:10 PM PDT 24
Peak memory 255804 kb
Host smart-bae5e6b6-226c-4978-b690-b6c7eae4c3d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34274
8746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.342748746
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2475190177
Short name T660
Test name
Test status
Simulation time 1357882493 ps
CPU time 22.78 seconds
Started Mar 10 01:26:52 PM PDT 24
Finished Mar 10 01:27:15 PM PDT 24
Peak memory 255560 kb
Host smart-d03b0d01-d71f-428a-b024-4b6464d7ff2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24751
90177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2475190177
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3427366968
Short name T703
Test name
Test status
Simulation time 270233029 ps
CPU time 19.08 seconds
Started Mar 10 01:26:49 PM PDT 24
Finished Mar 10 01:27:08 PM PDT 24
Peak memory 249036 kb
Host smart-3895b1d5-ac67-4170-b9a1-d0cb2582a09a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34273
66968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3427366968
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2087392256
Short name T126
Test name
Test status
Simulation time 16476053713 ps
CPU time 1324.53 seconds
Started Mar 10 01:26:54 PM PDT 24
Finished Mar 10 01:48:59 PM PDT 24
Peak memory 290008 kb
Host smart-7918eda1-d869-4dcb-9b2a-cc5bd6a9f7e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087392256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2087392256
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.611663111
Short name T398
Test name
Test status
Simulation time 59563749222 ps
CPU time 1623.72 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:54:07 PM PDT 24
Peak memory 289168 kb
Host smart-273fec8a-b346-46bd-aeaa-3b83ffb39ba2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611663111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.611663111
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1935110064
Short name T83
Test name
Test status
Simulation time 1487452692 ps
CPU time 18.64 seconds
Started Mar 10 01:26:58 PM PDT 24
Finished Mar 10 01:27:17 PM PDT 24
Peak memory 254952 kb
Host smart-0f98940a-05b0-4270-a9ec-9a813985b103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19351
10064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1935110064
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2416172790
Short name T247
Test name
Test status
Simulation time 28688201 ps
CPU time 4.53 seconds
Started Mar 10 01:26:57 PM PDT 24
Finished Mar 10 01:27:02 PM PDT 24
Peak memory 249860 kb
Host smart-dbd00432-31cd-4caf-9ff3-bfde5bbb1b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24161
72790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2416172790
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2922710952
Short name T327
Test name
Test status
Simulation time 34826414693 ps
CPU time 2104.9 seconds
Started Mar 10 01:27:02 PM PDT 24
Finished Mar 10 02:02:07 PM PDT 24
Peak memory 272944 kb
Host smart-0410d48e-ae31-4522-ad9d-fdc32dd409e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922710952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2922710952
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.1118522294
Short name T420
Test name
Test status
Simulation time 266795228798 ps
CPU time 3191.23 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 02:20:15 PM PDT 24
Peak memory 289200 kb
Host smart-d8d8b9dd-e08c-4ad6-868e-adb89144be72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118522294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.1118522294
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4051067840
Short name T209
Test name
Test status
Simulation time 2063792260 ps
CPU time 85.34 seconds
Started Mar 10 01:27:00 PM PDT 24
Finished Mar 10 01:28:26 PM PDT 24
Peak memory 247644 kb
Host smart-e01429d9-cdb0-4638-a840-50406a5c2464
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051067840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4051067840
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.880336454
Short name T449
Test name
Test status
Simulation time 133393299 ps
CPU time 23.18 seconds
Started Mar 10 01:26:51 PM PDT 24
Finished Mar 10 01:27:15 PM PDT 24
Peak memory 248952 kb
Host smart-29ac4822-5963-4c62-8457-f61dff314215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88033
6454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.880336454
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.3103124571
Short name T695
Test name
Test status
Simulation time 1429059335 ps
CPU time 35.73 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:27:39 PM PDT 24
Peak memory 255056 kb
Host smart-e5be6af5-f2b2-4732-86e3-591fcef8e686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31031
24571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.3103124571
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1748203873
Short name T587
Test name
Test status
Simulation time 317703045 ps
CPU time 20.82 seconds
Started Mar 10 01:26:57 PM PDT 24
Finished Mar 10 01:27:18 PM PDT 24
Peak memory 249036 kb
Host smart-ba7d012e-e864-403d-ab1d-88134a3d4f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17482
03873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1748203873
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2553006327
Short name T486
Test name
Test status
Simulation time 1521335476 ps
CPU time 15.01 seconds
Started Mar 10 01:26:54 PM PDT 24
Finished Mar 10 01:27:09 PM PDT 24
Peak memory 254824 kb
Host smart-52016733-692a-4096-b13e-7c4372c09281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25530
06327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2553006327
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3348813569
Short name T242
Test name
Test status
Simulation time 25090394952 ps
CPU time 1593.41 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:53:36 PM PDT 24
Peak memory 265432 kb
Host smart-b34c97d0-d487-41cd-a0c5-5976917600c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348813569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3348813569
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.400788366
Short name T423
Test name
Test status
Simulation time 230306208 ps
CPU time 4.73 seconds
Started Mar 10 01:26:59 PM PDT 24
Finished Mar 10 01:27:03 PM PDT 24
Peak memory 240800 kb
Host smart-73eeda1e-b18d-4b32-b923-a633fdd2214c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40078
8366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.400788366
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3353854957
Short name T620
Test name
Test status
Simulation time 1056706587 ps
CPU time 61.47 seconds
Started Mar 10 01:27:00 PM PDT 24
Finished Mar 10 01:28:02 PM PDT 24
Peak memory 255252 kb
Host smart-bee3a7cf-ba02-4e83-9555-4e04571855f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33538
54957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3353854957
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.621622041
Short name T111
Test name
Test status
Simulation time 94631536437 ps
CPU time 1381.78 seconds
Started Mar 10 01:27:02 PM PDT 24
Finished Mar 10 01:50:04 PM PDT 24
Peak memory 289808 kb
Host smart-d4d3a5e1-b533-4639-8908-9e04db1b59be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621622041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.621622041
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3389604123
Short name T316
Test name
Test status
Simulation time 12665746492 ps
CPU time 136.23 seconds
Started Mar 10 01:27:00 PM PDT 24
Finished Mar 10 01:29:17 PM PDT 24
Peak memory 246928 kb
Host smart-8f4650a9-7f3b-4599-83cb-dd25c3802f4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389604123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3389604123
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2137673113
Short name T279
Test name
Test status
Simulation time 802892910 ps
CPU time 31.92 seconds
Started Mar 10 01:26:58 PM PDT 24
Finished Mar 10 01:27:31 PM PDT 24
Peak memory 248992 kb
Host smart-3234c42f-75fc-42b9-aec8-a5b02c81d011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
73113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2137673113
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3713885510
Short name T406
Test name
Test status
Simulation time 23513103 ps
CPU time 3.33 seconds
Started Mar 10 01:26:57 PM PDT 24
Finished Mar 10 01:27:01 PM PDT 24
Peak memory 239056 kb
Host smart-9dba1887-ff5e-4562-8fd5-461cd5d7afa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
85510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3713885510
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.368170373
Short name T261
Test name
Test status
Simulation time 358040005 ps
CPU time 24.44 seconds
Started Mar 10 01:27:00 PM PDT 24
Finished Mar 10 01:27:25 PM PDT 24
Peak memory 249012 kb
Host smart-aad9057b-c119-4517-8693-7443c5971951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36817
0373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.368170373
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1498488590
Short name T518
Test name
Test status
Simulation time 461176409 ps
CPU time 30.8 seconds
Started Mar 10 01:26:57 PM PDT 24
Finished Mar 10 01:27:28 PM PDT 24
Peak memory 248996 kb
Host smart-3f06d968-5d00-4bac-b4e7-f07004b6a2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14984
88590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1498488590
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1291826526
Short name T113
Test name
Test status
Simulation time 92906486342 ps
CPU time 1932.72 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:59:16 PM PDT 24
Peak memory 297932 kb
Host smart-045d5e65-4bf6-403d-844c-395616b77139
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291826526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1291826526
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2969003747
Short name T99
Test name
Test status
Simulation time 166876542725 ps
CPU time 1744.59 seconds
Started Mar 10 01:27:02 PM PDT 24
Finished Mar 10 01:56:07 PM PDT 24
Peak memory 273296 kb
Host smart-1f93c088-d9d5-47f6-a5eb-9e6167bcd993
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969003747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2969003747
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1365060450
Short name T351
Test name
Test status
Simulation time 6611925180 ps
CPU time 39.52 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:27:43 PM PDT 24
Peak memory 256012 kb
Host smart-2fd4b852-34e2-43f7-b415-7ec6aa551c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13650
60450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1365060450
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1601195265
Short name T534
Test name
Test status
Simulation time 1208125952 ps
CPU time 13.55 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:27:16 PM PDT 24
Peak memory 248984 kb
Host smart-8ebc1211-8f14-4fda-9fdc-bc8fb529d951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
95265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1601195265
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.214435595
Short name T337
Test name
Test status
Simulation time 13436147621 ps
CPU time 1058.2 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 01:44:48 PM PDT 24
Peak memory 289912 kb
Host smart-1ca0db6b-4084-4e0e-b790-ff1ed2896f44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214435595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.214435595
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3266462575
Short name T428
Test name
Test status
Simulation time 38101199019 ps
CPU time 2588.21 seconds
Started Mar 10 01:27:08 PM PDT 24
Finished Mar 10 02:10:17 PM PDT 24
Peak memory 289556 kb
Host smart-3be775a1-a818-40d9-904e-3253ca11ecc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266462575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3266462575
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1397892253
Short name T321
Test name
Test status
Simulation time 25551197775 ps
CPU time 185.73 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:30:09 PM PDT 24
Peak memory 247116 kb
Host smart-53d0a34d-a590-4276-bda1-0c5852e65832
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397892253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1397892253
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.2734760232
Short name T603
Test name
Test status
Simulation time 715662386 ps
CPU time 35.13 seconds
Started Mar 10 01:27:03 PM PDT 24
Finished Mar 10 01:27:38 PM PDT 24
Peak memory 255644 kb
Host smart-c4b80ae1-bd55-45d2-a445-ba730e232bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27347
60232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.2734760232
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3321660673
Short name T644
Test name
Test status
Simulation time 259378469 ps
CPU time 30.27 seconds
Started Mar 10 01:27:04 PM PDT 24
Finished Mar 10 01:27:35 PM PDT 24
Peak memory 255632 kb
Host smart-111dc503-8027-45c0-8b6c-9836012907a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33216
60673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3321660673
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2391638228
Short name T426
Test name
Test status
Simulation time 891362727 ps
CPU time 56.79 seconds
Started Mar 10 01:27:04 PM PDT 24
Finished Mar 10 01:28:01 PM PDT 24
Peak memory 255748 kb
Host smart-8ce97f33-1773-46c1-89fb-ddb7505a9bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23916
38228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2391638228
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1127386237
Short name T499
Test name
Test status
Simulation time 139794316630 ps
CPU time 2288.47 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 02:05:18 PM PDT 24
Peak memory 289812 kb
Host smart-c61f4001-d440-4565-ad5a-ef97675ca879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127386237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1127386237
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1264644345
Short name T196
Test name
Test status
Simulation time 664466335 ps
CPU time 37.05 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 01:27:46 PM PDT 24
Peak memory 255756 kb
Host smart-eb5d151e-2d91-4be2-82e0-425be6a55de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12646
44345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1264644345
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1852120657
Short name T434
Test name
Test status
Simulation time 911401165 ps
CPU time 60.32 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 01:28:09 PM PDT 24
Peak memory 255508 kb
Host smart-824c48d0-bd9f-4993-ada7-a20f37bb0a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18521
20657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1852120657
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2627227585
Short name T630
Test name
Test status
Simulation time 19114643288 ps
CPU time 1081.11 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 01:45:08 PM PDT 24
Peak memory 265560 kb
Host smart-4d7c38ac-c6d4-4132-826d-ef35fc44767f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627227585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2627227585
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3382873740
Short name T657
Test name
Test status
Simulation time 35686538572 ps
CPU time 2254.4 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 02:04:44 PM PDT 24
Peak memory 289656 kb
Host smart-8c730f9e-fbb7-48e7-b129-ffe9931b3fd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382873740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3382873740
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1160931161
Short name T302
Test name
Test status
Simulation time 32996267901 ps
CPU time 663.44 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 01:38:11 PM PDT 24
Peak memory 246932 kb
Host smart-de4a88ea-b495-4289-a88f-2227af60a2ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160931161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1160931161
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.861008729
Short name T558
Test name
Test status
Simulation time 761129765 ps
CPU time 57.98 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 01:28:05 PM PDT 24
Peak memory 249000 kb
Host smart-923a34b2-b482-4534-93c2-90341256b7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86100
8729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.861008729
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.295887398
Short name T62
Test name
Test status
Simulation time 1147928721 ps
CPU time 32.46 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 01:27:40 PM PDT 24
Peak memory 255276 kb
Host smart-bf57f889-7a2a-40ff-9ede-880495fa630c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29588
7398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.295887398
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3494678188
Short name T53
Test name
Test status
Simulation time 554070689 ps
CPU time 38.05 seconds
Started Mar 10 01:27:09 PM PDT 24
Finished Mar 10 01:27:47 PM PDT 24
Peak memory 254348 kb
Host smart-94057c6e-5f8e-4807-8dce-8158d186a453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34946
78188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3494678188
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.129965361
Short name T527
Test name
Test status
Simulation time 560278044 ps
CPU time 20.8 seconds
Started Mar 10 01:27:07 PM PDT 24
Finished Mar 10 01:27:28 PM PDT 24
Peak memory 248980 kb
Host smart-73ef135d-b55f-4e10-9bee-8ec9e16bfeba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12996
5361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.129965361
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.4150181318
Short name T568
Test name
Test status
Simulation time 34764712173 ps
CPU time 2373.13 seconds
Started Mar 10 01:27:14 PM PDT 24
Finished Mar 10 02:06:48 PM PDT 24
Peak memory 281772 kb
Host smart-1beba08b-0e45-4f5e-b351-148514b15446
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150181318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.4150181318
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3324647212
Short name T648
Test name
Test status
Simulation time 16669522079 ps
CPU time 124.99 seconds
Started Mar 10 01:27:13 PM PDT 24
Finished Mar 10 01:29:18 PM PDT 24
Peak memory 256408 kb
Host smart-abe2996a-e0d4-463b-b43f-e8765fef9092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33246
47212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3324647212
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.4230992655
Short name T553
Test name
Test status
Simulation time 2087158424 ps
CPU time 32.91 seconds
Started Mar 10 01:27:14 PM PDT 24
Finished Mar 10 01:27:48 PM PDT 24
Peak memory 254612 kb
Host smart-2e0b9f7d-03bf-4767-8ac8-36ea239f4dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42309
92655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.4230992655
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3646155647
Short name T295
Test name
Test status
Simulation time 124162973109 ps
CPU time 1811.99 seconds
Started Mar 10 01:27:14 PM PDT 24
Finished Mar 10 01:57:27 PM PDT 24
Peak memory 272964 kb
Host smart-4a40f8e8-b4c3-4e91-87ae-3f152be0f5da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646155647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3646155647
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2451894557
Short name T20
Test name
Test status
Simulation time 29727020535 ps
CPU time 2172.61 seconds
Started Mar 10 01:27:16 PM PDT 24
Finished Mar 10 02:03:30 PM PDT 24
Peak memory 285160 kb
Host smart-369afee4-e624-483c-8650-b349feca3ba3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451894557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2451894557
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3929505168
Short name T236
Test name
Test status
Simulation time 30181026064 ps
CPU time 304.66 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:32:20 PM PDT 24
Peak memory 247740 kb
Host smart-77b19d9f-72c8-4473-9101-4339fe29ede2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929505168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3929505168
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1991896561
Short name T616
Test name
Test status
Simulation time 1208255789 ps
CPU time 20.75 seconds
Started Mar 10 01:27:16 PM PDT 24
Finished Mar 10 01:27:37 PM PDT 24
Peak memory 254896 kb
Host smart-7d800ee5-daf9-4fb0-8b25-66ce940d381a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19918
96561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1991896561
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1326052222
Short name T285
Test name
Test status
Simulation time 305924318 ps
CPU time 21.45 seconds
Started Mar 10 01:27:13 PM PDT 24
Finished Mar 10 01:27:35 PM PDT 24
Peak memory 255144 kb
Host smart-13188873-095e-4fd9-8c93-3fef4e7301b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13260
52222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1326052222
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.380347157
Short name T687
Test name
Test status
Simulation time 241445560 ps
CPU time 26.19 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:27:42 PM PDT 24
Peak memory 247476 kb
Host smart-85ab1bb5-e9ab-4054-9653-13057f7e1ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38034
7157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.380347157
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3431471036
Short name T384
Test name
Test status
Simulation time 337729538 ps
CPU time 34.52 seconds
Started Mar 10 01:27:17 PM PDT 24
Finished Mar 10 01:27:53 PM PDT 24
Peak memory 249012 kb
Host smart-3e130a54-3bd0-4fe1-a48b-fe71b9705daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34314
71036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3431471036
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3454416789
Short name T36
Test name
Test status
Simulation time 498328315 ps
CPU time 33.49 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:27:49 PM PDT 24
Peak memory 248988 kb
Host smart-c6bd46d8-de1c-4839-89b3-921df85bd644
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454416789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3454416789
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2969936566
Short name T282
Test name
Test status
Simulation time 101041435953 ps
CPU time 1576.49 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 01:53:36 PM PDT 24
Peak memory 266464 kb
Host smart-48d98999-1816-4c07-a8fb-25d10137bb6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969936566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2969936566
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.949661968
Short name T519
Test name
Test status
Simulation time 81633032007 ps
CPU time 270.91 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:31:51 PM PDT 24
Peak memory 256236 kb
Host smart-c5ae59c3-989c-4eca-a422-428d67b50b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94966
1968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.949661968
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4134118560
Short name T509
Test name
Test status
Simulation time 593523209 ps
CPU time 14.62 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:27:30 PM PDT 24
Peak memory 255304 kb
Host smart-397f77fb-8154-48cb-8339-80e1c6d3174f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41341
18560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4134118560
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2832111384
Short name T338
Test name
Test status
Simulation time 45427237376 ps
CPU time 677.49 seconds
Started Mar 10 01:27:17 PM PDT 24
Finished Mar 10 01:38:35 PM PDT 24
Peak memory 265504 kb
Host smart-3cb0d5b8-0ff3-4ce8-84e6-f463038aa6a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832111384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2832111384
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.2542143465
Short name T281
Test name
Test status
Simulation time 125605603654 ps
CPU time 1800.8 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:57:21 PM PDT 24
Peak memory 272512 kb
Host smart-a81174fb-dee0-488d-b7d4-c412d348898a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542143465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.2542143465
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.114919094
Short name T318
Test name
Test status
Simulation time 40425798137 ps
CPU time 369.12 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 01:33:28 PM PDT 24
Peak memory 247664 kb
Host smart-8a4d27e7-5f23-40d4-a96b-a9ba7c4f7f77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114919094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.114919094
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4067296284
Short name T674
Test name
Test status
Simulation time 440592099 ps
CPU time 14.66 seconds
Started Mar 10 01:27:14 PM PDT 24
Finished Mar 10 01:27:28 PM PDT 24
Peak memory 248952 kb
Host smart-365119dc-922b-4e02-be5f-6b741614120d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
96284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4067296284
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1677793396
Short name T578
Test name
Test status
Simulation time 520021472 ps
CPU time 32.08 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:27:48 PM PDT 24
Peak memory 255516 kb
Host smart-6530a2ef-37d0-4df9-aa65-65e3ce8b6c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16777
93396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1677793396
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2734926088
Short name T576
Test name
Test status
Simulation time 86426166 ps
CPU time 4.11 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 01:27:24 PM PDT 24
Peak memory 250584 kb
Host smart-54985f93-7778-40e5-8957-f3b2b38cf04b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27349
26088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2734926088
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2240281051
Short name T71
Test name
Test status
Simulation time 992769332 ps
CPU time 12.82 seconds
Started Mar 10 01:27:15 PM PDT 24
Finished Mar 10 01:27:28 PM PDT 24
Peak memory 248988 kb
Host smart-27a51fd9-f628-4049-888a-308426d4da1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22402
81051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2240281051
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2117478713
Short name T225
Test name
Test status
Simulation time 16938610 ps
CPU time 2.64 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:08 PM PDT 24
Peak memory 249156 kb
Host smart-7680ecfc-48be-4ac9-98bb-b80137afdfbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2117478713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2117478713
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3584670900
Short name T575
Test name
Test status
Simulation time 53455582772 ps
CPU time 921.91 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:41:41 PM PDT 24
Peak memory 273492 kb
Host smart-63ab422e-17ed-4a92-97eb-4920641fb15b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584670900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3584670900
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.239722250
Short name T192
Test name
Test status
Simulation time 757727349 ps
CPU time 23.87 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 240772 kb
Host smart-19142647-0a64-4d67-b7d1-8e5b4b3f4413
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=239722250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.239722250
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3880623473
Short name T579
Test name
Test status
Simulation time 3337426125 ps
CPU time 142.6 seconds
Started Mar 10 01:26:08 PM PDT 24
Finished Mar 10 01:28:31 PM PDT 24
Peak memory 256684 kb
Host smart-616401d4-27fc-4199-a1b9-c668daabff09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
23473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3880623473
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1569085461
Short name T594
Test name
Test status
Simulation time 1441684522 ps
CPU time 24.86 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:43 PM PDT 24
Peak memory 255420 kb
Host smart-f753f8eb-0ffe-4ebf-9eb0-d97d7635ef5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15690
85461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1569085461
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4224338759
Short name T686
Test name
Test status
Simulation time 20007404769 ps
CPU time 1599.32 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:52:51 PM PDT 24
Peak memory 288100 kb
Host smart-ac87e224-ac66-4306-8d85-d761a8a29d16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224338759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4224338759
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3725983281
Short name T563
Test name
Test status
Simulation time 33131107334 ps
CPU time 1205.73 seconds
Started Mar 10 01:26:08 PM PDT 24
Finished Mar 10 01:46:15 PM PDT 24
Peak memory 286800 kb
Host smart-678706e4-2c87-445e-ac01-f00e97a28263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725983281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3725983281
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2806989409
Short name T467
Test name
Test status
Simulation time 160428546 ps
CPU time 4.02 seconds
Started Mar 10 01:26:09 PM PDT 24
Finished Mar 10 01:26:14 PM PDT 24
Peak memory 240820 kb
Host smart-c2773554-05c8-41af-9b09-f744a4c5b72a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28069
89409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2806989409
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2220530574
Short name T22
Test name
Test status
Simulation time 741885530 ps
CPU time 20.64 seconds
Started Mar 10 01:26:02 PM PDT 24
Finished Mar 10 01:26:23 PM PDT 24
Peak memory 253888 kb
Host smart-76c3ce21-890a-4a22-8615-c22a37b695d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22205
30574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2220530574
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2229812043
Short name T7
Test name
Test status
Simulation time 1756383624 ps
CPU time 27.14 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 277708 kb
Host smart-a4c96e0c-273f-49ed-a181-e6e73267de0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2229812043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2229812043
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3708162296
Short name T266
Test name
Test status
Simulation time 129514886 ps
CPU time 8.1 seconds
Started Mar 10 01:26:15 PM PDT 24
Finished Mar 10 01:26:24 PM PDT 24
Peak memory 253144 kb
Host smart-768dd8f1-6bf8-4120-a81c-8fd11748ce1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37081
62296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3708162296
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.500232566
Short name T193
Test name
Test status
Simulation time 940867433 ps
CPU time 55.65 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 01:27:01 PM PDT 24
Peak memory 248988 kb
Host smart-dbb5d4e7-3445-4d97-8260-fc1c97b1c949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50023
2566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.500232566
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.738712013
Short name T122
Test name
Test status
Simulation time 70111458390 ps
CPU time 4198.48 seconds
Started Mar 10 01:26:03 PM PDT 24
Finished Mar 10 02:36:04 PM PDT 24
Peak memory 305996 kb
Host smart-843b803a-45a7-44ec-8935-67ea8875d3e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738712013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.738712013
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.864391480
Short name T702
Test name
Test status
Simulation time 97621188522 ps
CPU time 2546.19 seconds
Started Mar 10 01:27:20 PM PDT 24
Finished Mar 10 02:09:47 PM PDT 24
Peak memory 284516 kb
Host smart-a8326de7-36b8-408d-95f1-5b992b236f95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864391480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.864391480
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.935782346
Short name T235
Test name
Test status
Simulation time 606597283 ps
CPU time 18.2 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:27:38 PM PDT 24
Peak memory 256332 kb
Host smart-57b537e2-7dad-4cc1-871c-48bd051c287c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93578
2346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.935782346
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1802195878
Short name T624
Test name
Test status
Simulation time 229154209233 ps
CPU time 3219.49 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 02:21:00 PM PDT 24
Peak memory 288856 kb
Host smart-bc397006-75a3-47af-8409-09cdd732a406
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802195878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1802195878
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3156242658
Short name T385
Test name
Test status
Simulation time 168534855012 ps
CPU time 2860.56 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 02:15:01 PM PDT 24
Peak memory 286424 kb
Host smart-b66c1bb1-15d5-4cb4-bc1d-04f7fd3d908f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156242658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3156242658
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3155712721
Short name T691
Test name
Test status
Simulation time 3126345270 ps
CPU time 125.31 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:29:25 PM PDT 24
Peak memory 246936 kb
Host smart-a65d2fdb-8b1e-4f2c-9135-5ed44090ca34
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155712721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3155712721
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2710832010
Short name T437
Test name
Test status
Simulation time 2867269658 ps
CPU time 38.74 seconds
Started Mar 10 01:27:17 PM PDT 24
Finished Mar 10 01:27:56 PM PDT 24
Peak memory 248984 kb
Host smart-47e7b4e8-cb9e-4310-969a-162b6bc9e5dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27108
32010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2710832010
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.829392432
Short name T87
Test name
Test status
Simulation time 471190890 ps
CPU time 35.28 seconds
Started Mar 10 01:27:18 PM PDT 24
Finished Mar 10 01:27:55 PM PDT 24
Peak memory 255640 kb
Host smart-1e59aae1-dd25-46f2-a52d-ca8c648bf4fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82939
2432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.829392432
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.984917790
Short name T628
Test name
Test status
Simulation time 141727568 ps
CPU time 11.87 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:27:32 PM PDT 24
Peak memory 253836 kb
Host smart-4aff58b0-269d-4c7e-acc8-6b9e3b75b16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98491
7790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.984917790
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.4250739189
Short name T548
Test name
Test status
Simulation time 6998567358 ps
CPU time 59.44 seconds
Started Mar 10 01:27:17 PM PDT 24
Finished Mar 10 01:28:18 PM PDT 24
Peak memory 249008 kb
Host smart-be80aa8c-bcab-4c05-a2ed-35cf09670847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42507
39189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.4250739189
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.507611369
Short name T56
Test name
Test status
Simulation time 12205211419 ps
CPU time 250.09 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:31:30 PM PDT 24
Peak memory 253180 kb
Host smart-d5c6f18d-1532-411f-8a41-21f2eea1ece9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507611369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.507611369
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3084252197
Short name T383
Test name
Test status
Simulation time 40455749517 ps
CPU time 2397.1 seconds
Started Mar 10 01:27:22 PM PDT 24
Finished Mar 10 02:07:20 PM PDT 24
Peak memory 273632 kb
Host smart-a1c6338e-9d52-463d-951f-e0529978ab02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084252197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3084252197
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1461497521
Short name T682
Test name
Test status
Simulation time 12210125731 ps
CPU time 178.24 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:30:19 PM PDT 24
Peak memory 257220 kb
Host smart-ad85b7ab-1438-437b-8c5c-fe4b4a217a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14614
97521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1461497521
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.191054906
Short name T646
Test name
Test status
Simulation time 751932357 ps
CPU time 27.78 seconds
Started Mar 10 01:27:17 PM PDT 24
Finished Mar 10 01:27:47 PM PDT 24
Peak memory 247588 kb
Host smart-4f154a23-a780-4301-ac01-d93722ecbd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19105
4906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.191054906
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1005860163
Short name T424
Test name
Test status
Simulation time 229169951928 ps
CPU time 3161.83 seconds
Started Mar 10 01:27:22 PM PDT 24
Finished Mar 10 02:20:04 PM PDT 24
Peak memory 288288 kb
Host smart-8917abbb-97c9-41db-9552-cb31084841ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005860163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1005860163
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1610940481
Short name T239
Test name
Test status
Simulation time 59110813649 ps
CPU time 659.22 seconds
Started Mar 10 01:27:23 PM PDT 24
Finished Mar 10 01:38:23 PM PDT 24
Peak memory 247936 kb
Host smart-a43f479d-693f-4ecc-9cbe-fcfefa22189d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610940481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1610940481
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2931833109
Short name T85
Test name
Test status
Simulation time 355352014 ps
CPU time 8.11 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:27:29 PM PDT 24
Peak memory 257160 kb
Host smart-98e0f5ec-0c08-4eb4-afa1-bca335daf6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
33109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2931833109
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4230099711
Short name T619
Test name
Test status
Simulation time 15915107 ps
CPU time 2.88 seconds
Started Mar 10 01:27:22 PM PDT 24
Finished Mar 10 01:27:26 PM PDT 24
Peak memory 239108 kb
Host smart-8325c28a-5b57-495a-815f-3c6e39d6173c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42300
99711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4230099711
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1131682733
Short name T432
Test name
Test status
Simulation time 80130111 ps
CPU time 4.64 seconds
Started Mar 10 01:27:21 PM PDT 24
Finished Mar 10 01:27:26 PM PDT 24
Peak memory 248940 kb
Host smart-0ed0aac8-4b77-472e-add6-7a6d6273e077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11316
82733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1131682733
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3855675055
Short name T354
Test name
Test status
Simulation time 315515327 ps
CPU time 19.72 seconds
Started Mar 10 01:27:19 PM PDT 24
Finished Mar 10 01:27:40 PM PDT 24
Peak memory 255716 kb
Host smart-a7aca733-efd5-4455-b11f-0012fc5e5fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
75055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3855675055
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2799683249
Short name T27
Test name
Test status
Simulation time 41711866407 ps
CPU time 340.94 seconds
Started Mar 10 01:27:22 PM PDT 24
Finished Mar 10 01:33:04 PM PDT 24
Peak memory 257248 kb
Host smart-e727cce4-7e6d-4583-857f-5aedb32099bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799683249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2799683249
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3824680278
Short name T654
Test name
Test status
Simulation time 30204609405 ps
CPU time 2025.72 seconds
Started Mar 10 01:27:25 PM PDT 24
Finished Mar 10 02:01:12 PM PDT 24
Peak memory 281840 kb
Host smart-d93e0ba6-9d1d-4e3e-87cf-c9baae2e2bea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824680278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3824680278
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1592501884
Short name T672
Test name
Test status
Simulation time 17483816422 ps
CPU time 239.29 seconds
Started Mar 10 01:27:26 PM PDT 24
Finished Mar 10 01:31:25 PM PDT 24
Peak memory 256396 kb
Host smart-0c55efc6-d549-4038-804f-36c48304f021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15925
01884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1592501884
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2461458101
Short name T502
Test name
Test status
Simulation time 2455506829 ps
CPU time 34.66 seconds
Started Mar 10 01:27:26 PM PDT 24
Finished Mar 10 01:28:01 PM PDT 24
Peak memory 248772 kb
Host smart-4dd574e0-bbf8-4686-9579-7bcaf7e66a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24614
58101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2461458101
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4138555704
Short name T339
Test name
Test status
Simulation time 16271881162 ps
CPU time 855.07 seconds
Started Mar 10 01:27:23 PM PDT 24
Finished Mar 10 01:41:38 PM PDT 24
Peak memory 273312 kb
Host smart-ab381284-1d70-44eb-b714-4826e2ca2735
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138555704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4138555704
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1647741131
Short name T665
Test name
Test status
Simulation time 62929792709 ps
CPU time 1482.43 seconds
Started Mar 10 01:27:25 PM PDT 24
Finished Mar 10 01:52:08 PM PDT 24
Peak memory 288504 kb
Host smart-46a75a13-5735-4a90-b29d-8d5dfd0303c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647741131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1647741131
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2761090040
Short name T307
Test name
Test status
Simulation time 12982723646 ps
CPU time 524.51 seconds
Started Mar 10 01:27:24 PM PDT 24
Finished Mar 10 01:36:09 PM PDT 24
Peak memory 246956 kb
Host smart-d0100267-4f13-4aac-b89d-5c887f7ef514
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761090040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2761090040
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3624078386
Short name T44
Test name
Test status
Simulation time 333240959 ps
CPU time 32.08 seconds
Started Mar 10 01:27:24 PM PDT 24
Finished Mar 10 01:27:57 PM PDT 24
Peak memory 256012 kb
Host smart-867ad828-4723-4702-90c0-f6526ad6ddfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36240
78386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3624078386
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3446384553
Short name T455
Test name
Test status
Simulation time 77363890 ps
CPU time 5.61 seconds
Started Mar 10 01:27:22 PM PDT 24
Finished Mar 10 01:27:28 PM PDT 24
Peak memory 238940 kb
Host smart-666c3ed0-0b7a-484f-9eb9-d4b29d1283b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34463
84553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3446384553
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4133608551
Short name T379
Test name
Test status
Simulation time 33464622 ps
CPU time 4.65 seconds
Started Mar 10 01:27:26 PM PDT 24
Finished Mar 10 01:27:31 PM PDT 24
Peak memory 250836 kb
Host smart-94319493-c5b1-40e3-82ef-1497a21d8a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41336
08551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4133608551
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.46861939
Short name T394
Test name
Test status
Simulation time 1233310888 ps
CPU time 74.07 seconds
Started Mar 10 01:27:23 PM PDT 24
Finished Mar 10 01:28:37 PM PDT 24
Peak memory 249016 kb
Host smart-4da9677b-8ccd-419c-befd-e93ff65f2d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46861
939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.46861939
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3125219814
Short name T693
Test name
Test status
Simulation time 78594872863 ps
CPU time 1321.86 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 01:49:30 PM PDT 24
Peak memory 285404 kb
Host smart-6f73088c-c672-4b03-8aff-d73b03ad423c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125219814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3125219814
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2621077914
Short name T632
Test name
Test status
Simulation time 1044829369 ps
CPU time 82.89 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:28:52 PM PDT 24
Peak memory 249900 kb
Host smart-37f3aaac-9dd1-46a7-9ba3-13f59ae73161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26210
77914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2621077914
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4246326712
Short name T631
Test name
Test status
Simulation time 416735574 ps
CPU time 19.05 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:27:48 PM PDT 24
Peak memory 248668 kb
Host smart-33f06bd4-1979-4125-b463-a77c57296eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42463
26712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4246326712
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3501767008
Short name T329
Test name
Test status
Simulation time 187360576869 ps
CPU time 2776.28 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 02:13:44 PM PDT 24
Peak memory 281776 kb
Host smart-ab7976bc-a043-46a1-ae76-1978a9325ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501767008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3501767008
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.796149153
Short name T501
Test name
Test status
Simulation time 148432027799 ps
CPU time 1318.74 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:49:28 PM PDT 24
Peak memory 288060 kb
Host smart-e238ea90-730c-4ad2-a59d-4be1487c2840
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796149153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.796149153
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2144922558
Short name T557
Test name
Test status
Simulation time 26862169107 ps
CPU time 280.31 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:32:08 PM PDT 24
Peak memory 247852 kb
Host smart-e1cb369d-e089-449b-9544-55df7d1b1606
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144922558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2144922558
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.995595401
Short name T290
Test name
Test status
Simulation time 299417612 ps
CPU time 27.67 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:27:56 PM PDT 24
Peak memory 255752 kb
Host smart-47cf8610-bfcd-4fed-a2c0-c273832dea04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99559
5401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.995595401
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.515653473
Short name T48
Test name
Test status
Simulation time 171008186 ps
CPU time 8.13 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 01:27:36 PM PDT 24
Peak memory 252328 kb
Host smart-ac2ad03c-b07e-4673-94a8-f2355ba23a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51565
3473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.515653473
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1626603690
Short name T284
Test name
Test status
Simulation time 1346671957 ps
CPU time 31.94 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:28:01 PM PDT 24
Peak memory 249008 kb
Host smart-b9377eac-ba76-4ece-8f7a-8cc28ae12200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16266
03690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1626603690
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2431199280
Short name T601
Test name
Test status
Simulation time 1042358502 ps
CPU time 50.04 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:28:18 PM PDT 24
Peak memory 255840 kb
Host smart-947e7c32-44df-4f9f-9e03-104cdd4e8c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24311
99280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2431199280
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.4020834559
Short name T503
Test name
Test status
Simulation time 46529610003 ps
CPU time 1223.96 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 01:47:51 PM PDT 24
Peak memory 285536 kb
Host smart-8c3b103f-0114-46a1-b9db-776a4fe378aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020834559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.4020834559
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.488995679
Short name T88
Test name
Test status
Simulation time 114749170903 ps
CPU time 6165.15 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 03:10:15 PM PDT 24
Peak memory 355236 kb
Host smart-ff64b607-dc43-4ea6-9afb-b30cf3d9646c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488995679 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.488995679
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.842199102
Short name T205
Test name
Test status
Simulation time 26827314683 ps
CPU time 1326.85 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:49:37 PM PDT 24
Peak memory 284436 kb
Host smart-3336832d-bb92-4de1-9553-09ca583d2a93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842199102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.842199102
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1978229566
Short name T585
Test name
Test status
Simulation time 4584269914 ps
CPU time 277.65 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:32:07 PM PDT 24
Peak memory 256400 kb
Host smart-38285794-300f-48a0-b9fa-fd3b0f37d246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19782
29566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1978229566
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3623402948
Short name T77
Test name
Test status
Simulation time 7280763475 ps
CPU time 38.33 seconds
Started Mar 10 01:27:29 PM PDT 24
Finished Mar 10 01:28:08 PM PDT 24
Peak memory 254788 kb
Host smart-8caad0a2-e653-4b37-b516-0e41deeecce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36234
02948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3623402948
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4009146356
Short name T374
Test name
Test status
Simulation time 72513729456 ps
CPU time 1823.41 seconds
Started Mar 10 01:27:33 PM PDT 24
Finished Mar 10 01:57:57 PM PDT 24
Peak memory 273164 kb
Host smart-b7dec368-b49c-4df3-8bd4-7ad8af1d7784
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009146356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4009146356
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.90130308
Short name T301
Test name
Test status
Simulation time 9158034463 ps
CPU time 344.71 seconds
Started Mar 10 01:27:30 PM PDT 24
Finished Mar 10 01:33:15 PM PDT 24
Peak memory 247720 kb
Host smart-906f2e1b-00d9-4bf5-b186-a0b60043b45a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90130308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.90130308
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1565935228
Short name T39
Test name
Test status
Simulation time 862236327 ps
CPU time 60.36 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:28:28 PM PDT 24
Peak memory 255800 kb
Host smart-0fe80f73-fe35-4616-9d49-f88e5a97d74e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15659
35228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1565935228
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3219260624
Short name T617
Test name
Test status
Simulation time 242241280 ps
CPU time 16.2 seconds
Started Mar 10 01:27:26 PM PDT 24
Finished Mar 10 01:27:43 PM PDT 24
Peak memory 255472 kb
Host smart-62b4569f-8f5e-4334-b294-49cf8506f95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32192
60624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3219260624
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1297168843
Short name T696
Test name
Test status
Simulation time 467622284 ps
CPU time 8.54 seconds
Started Mar 10 01:27:27 PM PDT 24
Finished Mar 10 01:27:36 PM PDT 24
Peak memory 252360 kb
Host smart-8b35c06a-4d8f-4969-a9e5-7e3823f53172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12971
68843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1297168843
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1962695380
Short name T567
Test name
Test status
Simulation time 4586391761 ps
CPU time 60.91 seconds
Started Mar 10 01:27:28 PM PDT 24
Finished Mar 10 01:28:29 PM PDT 24
Peak memory 255820 kb
Host smart-389dac93-d4fb-4082-9eb6-d894673409a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19626
95380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1962695380
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1963303102
Short name T246
Test name
Test status
Simulation time 957836659 ps
CPU time 31.09 seconds
Started Mar 10 01:27:35 PM PDT 24
Finished Mar 10 01:28:06 PM PDT 24
Peak memory 248988 kb
Host smart-0edddc27-2312-4ad5-8147-889b4b5382fb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963303102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1963303102
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.4033043451
Short name T63
Test name
Test status
Simulation time 248327879950 ps
CPU time 6969.2 seconds
Started Mar 10 01:27:35 PM PDT 24
Finished Mar 10 03:23:45 PM PDT 24
Peak memory 354956 kb
Host smart-45e0f86c-a8f2-4f98-921a-de45475ad777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033043451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.4033043451
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.684423780
Short name T438
Test name
Test status
Simulation time 150536275907 ps
CPU time 2048.46 seconds
Started Mar 10 01:27:32 PM PDT 24
Finished Mar 10 02:01:41 PM PDT 24
Peak memory 281496 kb
Host smart-8fca3158-2623-43a1-bf4f-d7f375993184
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684423780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.684423780
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1300485959
Short name T589
Test name
Test status
Simulation time 15893762431 ps
CPU time 244.18 seconds
Started Mar 10 01:27:32 PM PDT 24
Finished Mar 10 01:31:37 PM PDT 24
Peak memory 257164 kb
Host smart-db657cdc-2f42-4752-aa7e-5bc566f7fb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13004
85959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1300485959
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.994012504
Short name T243
Test name
Test status
Simulation time 276314391 ps
CPU time 23.52 seconds
Started Mar 10 01:27:34 PM PDT 24
Finished Mar 10 01:27:57 PM PDT 24
Peak memory 254624 kb
Host smart-18350f30-8448-4ca1-ac25-587d1c971f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99401
2504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.994012504
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4148090019
Short name T298
Test name
Test status
Simulation time 83431269845 ps
CPU time 1424.96 seconds
Started Mar 10 01:27:36 PM PDT 24
Finished Mar 10 01:51:21 PM PDT 24
Peak memory 272652 kb
Host smart-f2157536-cfac-4bef-8dc4-504eb4f0e272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148090019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4148090019
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3689454917
Short name T564
Test name
Test status
Simulation time 40218455664 ps
CPU time 2194.63 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 02:04:14 PM PDT 24
Peak memory 282548 kb
Host smart-5159dac4-0180-42ca-99c5-fed6fd4d935e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689454917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3689454917
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1419875405
Short name T306
Test name
Test status
Simulation time 6095296505 ps
CPU time 265.91 seconds
Started Mar 10 01:27:32 PM PDT 24
Finished Mar 10 01:31:58 PM PDT 24
Peak memory 247880 kb
Host smart-7e3ee1aa-bb1a-49f6-bf7b-411a2b89b39f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419875405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1419875405
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3837589000
Short name T522
Test name
Test status
Simulation time 2332111788 ps
CPU time 72.83 seconds
Started Mar 10 01:27:33 PM PDT 24
Finished Mar 10 01:28:46 PM PDT 24
Peak memory 248988 kb
Host smart-e4099c0c-e5f5-4365-bca9-9273fe44bee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375
89000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3837589000
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2440454568
Short name T640
Test name
Test status
Simulation time 344828639 ps
CPU time 34.57 seconds
Started Mar 10 01:27:34 PM PDT 24
Finished Mar 10 01:28:08 PM PDT 24
Peak memory 255212 kb
Host smart-09147079-2787-40f2-b7b3-b654de942a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24404
54568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2440454568
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.1424030047
Short name T659
Test name
Test status
Simulation time 306073373 ps
CPU time 40.64 seconds
Started Mar 10 01:27:35 PM PDT 24
Finished Mar 10 01:28:15 PM PDT 24
Peak memory 247304 kb
Host smart-2d8a796f-4d6d-4166-9273-3dd10c4ed423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14240
30047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.1424030047
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2720230822
Short name T356
Test name
Test status
Simulation time 153028104 ps
CPU time 9.64 seconds
Started Mar 10 01:27:35 PM PDT 24
Finished Mar 10 01:27:45 PM PDT 24
Peak memory 252668 kb
Host smart-7272994e-7d68-447c-9c88-784fc20027a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
30822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2720230822
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.366421122
Short name T102
Test name
Test status
Simulation time 97774642252 ps
CPU time 4450.43 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 02:41:50 PM PDT 24
Peak memory 298216 kb
Host smart-8527be16-b298-49ff-bd73-345a9ff0fa6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366421122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.366421122
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.233206349
Short name T415
Test name
Test status
Simulation time 45190435872 ps
CPU time 1520.32 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 01:53:00 PM PDT 24
Peak memory 289760 kb
Host smart-5ec71437-ba02-44d5-ac1f-7b5b06acbfce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233206349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.233206349
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1325039690
Short name T363
Test name
Test status
Simulation time 1195442830 ps
CPU time 113.47 seconds
Started Mar 10 01:27:42 PM PDT 24
Finished Mar 10 01:29:36 PM PDT 24
Peak memory 249880 kb
Host smart-3f271c7a-d273-4117-b6bf-066abd3167e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13250
39690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1325039690
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3266955964
Short name T2
Test name
Test status
Simulation time 203862433 ps
CPU time 21.15 seconds
Started Mar 10 01:27:38 PM PDT 24
Finished Mar 10 01:27:59 PM PDT 24
Peak memory 255780 kb
Host smart-ee04e730-eda6-4d87-a92c-1462ecbeaf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32669
55964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3266955964
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.1556172937
Short name T210
Test name
Test status
Simulation time 90169430957 ps
CPU time 1637.52 seconds
Started Mar 10 01:27:45 PM PDT 24
Finished Mar 10 01:55:03 PM PDT 24
Peak memory 273568 kb
Host smart-303d0c7c-5154-41bf-9af7-67380136c0ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556172937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1556172937
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.853310025
Short name T436
Test name
Test status
Simulation time 200617859 ps
CPU time 17.42 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 01:27:56 PM PDT 24
Peak memory 249008 kb
Host smart-53497142-5c27-426a-a192-76ac0d72660f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85331
0025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.853310025
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.735738306
Short name T60
Test name
Test status
Simulation time 2601067532 ps
CPU time 41.15 seconds
Started Mar 10 01:27:41 PM PDT 24
Finished Mar 10 01:28:22 PM PDT 24
Peak memory 247864 kb
Host smart-a258f815-4b94-4421-87a7-551ed500d628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73573
8306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.735738306
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1368283696
Short name T378
Test name
Test status
Simulation time 127084225 ps
CPU time 14.83 seconds
Started Mar 10 01:27:39 PM PDT 24
Finished Mar 10 01:27:54 PM PDT 24
Peak memory 249000 kb
Host smart-11674eea-e8ac-439d-b64e-a3ab15bd16f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13682
83696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1368283696
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.51561169
Short name T544
Test name
Test status
Simulation time 940350955 ps
CPU time 17.22 seconds
Started Mar 10 01:27:41 PM PDT 24
Finished Mar 10 01:27:58 PM PDT 24
Peak memory 257176 kb
Host smart-512b5fb2-30ab-484b-8c77-ad98732173a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51561
169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.51561169
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1633304652
Short name T489
Test name
Test status
Simulation time 149771730688 ps
CPU time 2543.29 seconds
Started Mar 10 01:27:43 PM PDT 24
Finished Mar 10 02:10:07 PM PDT 24
Peak memory 290024 kb
Host smart-5902e8a2-8bf4-4d0a-83e9-0a20413c28ca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633304652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1633304652
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1721020807
Short name T526
Test name
Test status
Simulation time 50032383495 ps
CPU time 4375.12 seconds
Started Mar 10 01:27:45 PM PDT 24
Finished Mar 10 02:40:41 PM PDT 24
Peak memory 319684 kb
Host smart-628aded3-bd5d-4e89-9376-30c948c7242a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721020807 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1721020807
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2963344910
Short name T473
Test name
Test status
Simulation time 14062274883 ps
CPU time 985.34 seconds
Started Mar 10 01:27:46 PM PDT 24
Finished Mar 10 01:44:11 PM PDT 24
Peak memory 273616 kb
Host smart-f7a01586-d4bd-4724-b90f-9a29f4833444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963344910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2963344910
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2742700800
Short name T561
Test name
Test status
Simulation time 60934759 ps
CPU time 5.64 seconds
Started Mar 10 01:27:45 PM PDT 24
Finished Mar 10 01:27:52 PM PDT 24
Peak memory 250672 kb
Host smart-404d1c38-48a1-4169-9a4f-dfbf19f8ce52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27427
00800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2742700800
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3687002420
Short name T11
Test name
Test status
Simulation time 411305073 ps
CPU time 21.18 seconds
Started Mar 10 01:27:43 PM PDT 24
Finished Mar 10 01:28:04 PM PDT 24
Peak memory 255320 kb
Host smart-cce77468-8824-4367-86c8-618645f76597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36870
02420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3687002420
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4280337542
Short name T596
Test name
Test status
Simulation time 41031746566 ps
CPU time 2498.46 seconds
Started Mar 10 01:27:44 PM PDT 24
Finished Mar 10 02:09:23 PM PDT 24
Peak memory 288024 kb
Host smart-bb2b870a-9f78-480f-8631-4232298e1c08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280337542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4280337542
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2184067053
Short name T683
Test name
Test status
Simulation time 17545488046 ps
CPU time 1268.06 seconds
Started Mar 10 01:27:47 PM PDT 24
Finished Mar 10 01:48:56 PM PDT 24
Peak memory 289060 kb
Host smart-37ad403d-6fea-4dda-8c60-1ab191db4de9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184067053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2184067053
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3656508608
Short name T600
Test name
Test status
Simulation time 5358910377 ps
CPU time 231.64 seconds
Started Mar 10 01:27:45 PM PDT 24
Finished Mar 10 01:31:37 PM PDT 24
Peak memory 247800 kb
Host smart-6fc30af9-5a8c-4d7f-a2e0-49ea19f8c5c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656508608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3656508608
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.940166694
Short name T368
Test name
Test status
Simulation time 545262403 ps
CPU time 10.29 seconds
Started Mar 10 01:27:43 PM PDT 24
Finished Mar 10 01:27:54 PM PDT 24
Peak memory 248948 kb
Host smart-466c15f9-6c7e-4a50-acb3-6400f77635d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94016
6694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.940166694
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.940220447
Short name T658
Test name
Test status
Simulation time 651833740 ps
CPU time 37.72 seconds
Started Mar 10 01:27:43 PM PDT 24
Finished Mar 10 01:28:22 PM PDT 24
Peak memory 255768 kb
Host smart-1a9a6dac-976a-4fda-b107-8f88cbedd4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94022
0447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.940220447
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1925064452
Short name T504
Test name
Test status
Simulation time 90062274 ps
CPU time 3.13 seconds
Started Mar 10 01:27:48 PM PDT 24
Finished Mar 10 01:27:51 PM PDT 24
Peak memory 239072 kb
Host smart-5a004ccb-bf2a-4d39-bed7-1fbd6b102fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19250
64452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1925064452
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.465334012
Short name T462
Test name
Test status
Simulation time 551817281 ps
CPU time 30.19 seconds
Started Mar 10 01:27:44 PM PDT 24
Finished Mar 10 01:28:14 PM PDT 24
Peak memory 249052 kb
Host smart-28414757-0952-468a-9d12-27f7a1aefc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46533
4012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.465334012
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3132378997
Short name T92
Test name
Test status
Simulation time 18318573328 ps
CPU time 506.29 seconds
Started Mar 10 01:27:49 PM PDT 24
Finished Mar 10 01:36:15 PM PDT 24
Peak memory 265456 kb
Host smart-ec2c5c9b-0fed-47e9-ad9b-b064589161df
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132378997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3132378997
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1560999092
Short name T73
Test name
Test status
Simulation time 195729865571 ps
CPU time 2876.99 seconds
Started Mar 10 01:27:53 PM PDT 24
Finished Mar 10 02:15:51 PM PDT 24
Peak memory 289508 kb
Host smart-4fb140f9-a6cf-4353-90b6-116c1c06b11f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560999092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1560999092
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1284891366
Short name T565
Test name
Test status
Simulation time 2890564725 ps
CPU time 125.37 seconds
Started Mar 10 01:27:53 PM PDT 24
Finished Mar 10 01:29:59 PM PDT 24
Peak memory 256288 kb
Host smart-8754276e-0e28-42d7-a4bf-fb795189d6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12848
91366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1284891366
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1562847394
Short name T248
Test name
Test status
Simulation time 2018294657 ps
CPU time 21.25 seconds
Started Mar 10 01:27:51 PM PDT 24
Finished Mar 10 01:28:12 PM PDT 24
Peak memory 253436 kb
Host smart-71cdb99e-fa79-4c46-88a0-fbdfd358960e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15628
47394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1562847394
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1427998634
Short name T641
Test name
Test status
Simulation time 169340565567 ps
CPU time 3289.75 seconds
Started Mar 10 01:27:53 PM PDT 24
Finished Mar 10 02:22:43 PM PDT 24
Peak memory 289548 kb
Host smart-7c06bded-a6dc-493b-8f9f-ba7d99ed018b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427998634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1427998634
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1934978792
Short name T30
Test name
Test status
Simulation time 28166398919 ps
CPU time 1551.72 seconds
Started Mar 10 01:27:53 PM PDT 24
Finished Mar 10 01:53:45 PM PDT 24
Peak memory 281852 kb
Host smart-57603e84-ffd6-4415-be21-66d8c344d550
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934978792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1934978792
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.11157299
Short name T457
Test name
Test status
Simulation time 2949819287 ps
CPU time 138.14 seconds
Started Mar 10 01:27:54 PM PDT 24
Finished Mar 10 01:30:13 PM PDT 24
Peak memory 247940 kb
Host smart-fd5429f1-687c-4dc3-b066-e0b00b76f026
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11157299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.11157299
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1918760143
Short name T404
Test name
Test status
Simulation time 1580200856 ps
CPU time 36.52 seconds
Started Mar 10 01:27:50 PM PDT 24
Finished Mar 10 01:28:27 PM PDT 24
Peak memory 248984 kb
Host smart-cfbbca30-f5ac-496f-94ff-e0f471a89da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19187
60143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1918760143
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.264086853
Short name T441
Test name
Test status
Simulation time 1019782456 ps
CPU time 61.73 seconds
Started Mar 10 01:27:49 PM PDT 24
Finished Mar 10 01:28:50 PM PDT 24
Peak memory 255284 kb
Host smart-788cf7a1-91f9-4718-8641-3b0d02bbcd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408
6853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.264086853
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3313954990
Short name T104
Test name
Test status
Simulation time 824974071 ps
CPU time 24.13 seconds
Started Mar 10 01:27:53 PM PDT 24
Finished Mar 10 01:28:18 PM PDT 24
Peak memory 249036 kb
Host smart-8070f6a0-d169-4205-9a42-41e706a412f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33139
54990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3313954990
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1072160089
Short name T685
Test name
Test status
Simulation time 261486912 ps
CPU time 22.42 seconds
Started Mar 10 01:27:51 PM PDT 24
Finished Mar 10 01:28:13 PM PDT 24
Peak memory 248944 kb
Host smart-dbbae6b3-f151-4f2f-aeb6-e821e99974d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
60089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1072160089
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.459341641
Short name T109
Test name
Test status
Simulation time 134199757682 ps
CPU time 4066.69 seconds
Started Mar 10 01:27:54 PM PDT 24
Finished Mar 10 02:35:41 PM PDT 24
Peak memory 300212 kb
Host smart-fb95dab7-abcd-4aaa-b740-9b35efd01113
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459341641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.459341641
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2354898952
Short name T129
Test name
Test status
Simulation time 40470902249 ps
CPU time 4085.6 seconds
Started Mar 10 01:27:54 PM PDT 24
Finished Mar 10 02:36:00 PM PDT 24
Peak memory 338700 kb
Host smart-e6807493-4573-4cf3-b9fe-6480aa4e776e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354898952 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2354898952
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2970484151
Short name T491
Test name
Test status
Simulation time 27760163590 ps
CPU time 1329.83 seconds
Started Mar 10 01:27:59 PM PDT 24
Finished Mar 10 01:50:09 PM PDT 24
Peak memory 288468 kb
Host smart-08999ef9-70c1-469d-b3fc-5d4484f9c3e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970484151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2970484151
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2653833134
Short name T448
Test name
Test status
Simulation time 978359289 ps
CPU time 28.96 seconds
Started Mar 10 01:27:59 PM PDT 24
Finished Mar 10 01:28:28 PM PDT 24
Peak memory 248412 kb
Host smart-bb2e9660-c0a9-45c6-8bf8-17af95cadc64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26538
33134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2653833134
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.587146568
Short name T459
Test name
Test status
Simulation time 451998321 ps
CPU time 11.86 seconds
Started Mar 10 01:27:59 PM PDT 24
Finished Mar 10 01:28:11 PM PDT 24
Peak memory 254196 kb
Host smart-e46fcab3-403d-4c91-9ce9-529d734c8b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58714
6568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.587146568
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3150269404
Short name T552
Test name
Test status
Simulation time 70184524877 ps
CPU time 1732.15 seconds
Started Mar 10 01:28:00 PM PDT 24
Finished Mar 10 01:56:53 PM PDT 24
Peak memory 289484 kb
Host smart-bfddf3ac-887d-452e-90d8-4240db663dc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150269404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3150269404
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.865726923
Short name T543
Test name
Test status
Simulation time 69261192817 ps
CPU time 3175.62 seconds
Started Mar 10 01:28:00 PM PDT 24
Finished Mar 10 02:20:56 PM PDT 24
Peak memory 289596 kb
Host smart-a2034fd3-ba54-43e9-8500-20624ce5069c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865726923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.865726923
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2467659830
Short name T194
Test name
Test status
Simulation time 203691764 ps
CPU time 21.92 seconds
Started Mar 10 01:27:56 PM PDT 24
Finished Mar 10 01:28:18 PM PDT 24
Peak memory 249016 kb
Host smart-7b731093-a9ce-40a5-a31d-ca7bb3c2c892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
59830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2467659830
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.896406974
Short name T390
Test name
Test status
Simulation time 77817678 ps
CPU time 4.05 seconds
Started Mar 10 01:27:54 PM PDT 24
Finished Mar 10 01:27:58 PM PDT 24
Peak memory 239012 kb
Host smart-54117889-0d03-4302-a667-49722e0f2035
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89640
6974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.896406974
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3214620520
Short name T442
Test name
Test status
Simulation time 685583077 ps
CPU time 43.6 seconds
Started Mar 10 01:27:59 PM PDT 24
Finished Mar 10 01:28:42 PM PDT 24
Peak memory 255592 kb
Host smart-97735dd3-a7cd-40b9-b7cb-9ade35a15cab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32146
20520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3214620520
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.660958873
Short name T529
Test name
Test status
Simulation time 619948407 ps
CPU time 38.56 seconds
Started Mar 10 01:27:55 PM PDT 24
Finished Mar 10 01:28:34 PM PDT 24
Peak memory 249132 kb
Host smart-dadcada2-6c2c-4694-bcdc-172eabd2e54a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66095
8873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.660958873
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1621158054
Short name T231
Test name
Test status
Simulation time 104291426 ps
CPU time 2.6 seconds
Started Mar 10 01:26:12 PM PDT 24
Finished Mar 10 01:26:15 PM PDT 24
Peak memory 249128 kb
Host smart-ce94ae73-fdac-4c67-9f6b-98b7f03abee1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1621158054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1621158054
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.3938132535
Short name T500
Test name
Test status
Simulation time 10373715429 ps
CPU time 1182.51 seconds
Started Mar 10 01:26:03 PM PDT 24
Finished Mar 10 01:45:47 PM PDT 24
Peak memory 284856 kb
Host smart-a4bb4ecf-7ca2-4d21-b254-7d56710bc390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938132535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.3938132535
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3715424596
Short name T411
Test name
Test status
Simulation time 106809416 ps
CPU time 7.04 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:13 PM PDT 24
Peak memory 240780 kb
Host smart-a491c46e-0044-4b35-ae1a-aea52afc7550
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3715424596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3715424596
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2408823024
Short name T128
Test name
Test status
Simulation time 3451189651 ps
CPU time 189.58 seconds
Started Mar 10 01:26:03 PM PDT 24
Finished Mar 10 01:29:15 PM PDT 24
Peak memory 256684 kb
Host smart-ec0a5e30-3216-487e-bd56-09ce2ab6227a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24088
23024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2408823024
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2494031998
Short name T675
Test name
Test status
Simulation time 325315102 ps
CPU time 11.69 seconds
Started Mar 10 01:26:02 PM PDT 24
Finished Mar 10 01:26:14 PM PDT 24
Peak memory 252840 kb
Host smart-d739e113-d83d-45b1-8344-9dfb07b606ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24940
31998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2494031998
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2859716257
Short name T584
Test name
Test status
Simulation time 29001821966 ps
CPU time 2030.84 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 02:00:05 PM PDT 24
Peak memory 289836 kb
Host smart-6978937f-22d1-4f29-8013-9aeb4e4a4372
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859716257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2859716257
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3463558163
Short name T664
Test name
Test status
Simulation time 63716050630 ps
CPU time 2202.51 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 02:02:48 PM PDT 24
Peak memory 285588 kb
Host smart-1a23d928-d962-406a-964b-43f51db7af68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463558163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3463558163
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4181336522
Short name T311
Test name
Test status
Simulation time 41706021469 ps
CPU time 487.61 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:34:19 PM PDT 24
Peak memory 247456 kb
Host smart-66cdff33-213a-4c83-bed0-464f776dce77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181336522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4181336522
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1136024456
Short name T355
Test name
Test status
Simulation time 554535571 ps
CPU time 21.36 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 248992 kb
Host smart-0d6753f2-7122-42bf-b6ad-e4792ab29e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11360
24456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1136024456
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.781818743
Short name T107
Test name
Test status
Simulation time 1599034508 ps
CPU time 48.02 seconds
Started Mar 10 01:26:03 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 256456 kb
Host smart-9085a12d-977a-44c7-9ab2-bab461b78d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78181
8743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.781818743
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3385871447
Short name T269
Test name
Test status
Simulation time 562990339 ps
CPU time 31.74 seconds
Started Mar 10 01:26:06 PM PDT 24
Finished Mar 10 01:26:38 PM PDT 24
Peak memory 248300 kb
Host smart-6f375b65-b67e-44a4-98bf-2108084651e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33858
71447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3385871447
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3968368225
Short name T234
Test name
Test status
Simulation time 442661951 ps
CPU time 9.64 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:28 PM PDT 24
Peak memory 248960 kb
Host smart-602c21ab-909b-4fb2-8714-1743047d1528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39683
68225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3968368225
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.674626022
Short name T465
Test name
Test status
Simulation time 318771811 ps
CPU time 10.53 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:16 PM PDT 24
Peak memory 249000 kb
Host smart-84100029-72d4-46d6-9c2f-55e05b82f930
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674626022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.674626022
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3256780056
Short name T252
Test name
Test status
Simulation time 518590817653 ps
CPU time 2027.56 seconds
Started Mar 10 01:26:09 PM PDT 24
Finished Mar 10 01:59:58 PM PDT 24
Peak memory 290064 kb
Host smart-887a54a1-8bfe-4b91-a82c-ffdd8a7cc50d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256780056 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3256780056
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2695866462
Short name T512
Test name
Test status
Simulation time 12723536963 ps
CPU time 1637.17 seconds
Started Mar 10 01:28:05 PM PDT 24
Finished Mar 10 01:55:22 PM PDT 24
Peak memory 289112 kb
Host smart-0ccab4fe-77a8-41da-9fde-04d3f3e93057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695866462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2695866462
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.310694112
Short name T570
Test name
Test status
Simulation time 1999195391 ps
CPU time 121.1 seconds
Started Mar 10 01:28:03 PM PDT 24
Finished Mar 10 01:30:04 PM PDT 24
Peak memory 256428 kb
Host smart-ecbd7da2-e78d-4783-aac2-3ce481e6e600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31069
4112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.310694112
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1493938835
Short name T23
Test name
Test status
Simulation time 174354807 ps
CPU time 19.48 seconds
Started Mar 10 01:28:04 PM PDT 24
Finished Mar 10 01:28:24 PM PDT 24
Peak memory 254460 kb
Host smart-8e6b5e72-ccc4-4381-9f84-98834bb71bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14939
38835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1493938835
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2794900934
Short name T332
Test name
Test status
Simulation time 504218843002 ps
CPU time 3099.4 seconds
Started Mar 10 01:28:04 PM PDT 24
Finished Mar 10 02:19:44 PM PDT 24
Peak memory 289548 kb
Host smart-0ef5c35a-f61c-41c9-a0dd-f62f5c701181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794900934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2794900934
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3988470153
Short name T525
Test name
Test status
Simulation time 12275875130 ps
CPU time 1161.83 seconds
Started Mar 10 01:28:03 PM PDT 24
Finished Mar 10 01:47:25 PM PDT 24
Peak memory 285924 kb
Host smart-dbfa4b02-899b-4c03-bfdd-42e63653f88a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988470153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3988470153
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2415095921
Short name T310
Test name
Test status
Simulation time 30028621466 ps
CPU time 371.72 seconds
Started Mar 10 01:28:05 PM PDT 24
Finished Mar 10 01:34:16 PM PDT 24
Peak memory 247728 kb
Host smart-575b4eaf-0a1e-4d6e-b758-8d3bd0cb96b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415095921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2415095921
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4077233802
Short name T650
Test name
Test status
Simulation time 370728986 ps
CPU time 17.93 seconds
Started Mar 10 01:28:03 PM PDT 24
Finished Mar 10 01:28:21 PM PDT 24
Peak memory 255336 kb
Host smart-7f57ca4e-7d51-4c0d-a469-c228ca74a588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40772
33802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4077233802
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1821501433
Short name T444
Test name
Test status
Simulation time 140718343 ps
CPU time 7.65 seconds
Started Mar 10 01:28:04 PM PDT 24
Finished Mar 10 01:28:12 PM PDT 24
Peak memory 250992 kb
Host smart-a9edea3c-5fe0-4dba-8b21-f55eac71e656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18215
01433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1821501433
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1480629639
Short name T673
Test name
Test status
Simulation time 2910164099 ps
CPU time 56.35 seconds
Started Mar 10 01:28:03 PM PDT 24
Finished Mar 10 01:29:00 PM PDT 24
Peak memory 248556 kb
Host smart-d849e44b-9976-42e5-b20b-b3a02c09c7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
29639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1480629639
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1864807080
Short name T517
Test name
Test status
Simulation time 705035965 ps
CPU time 30.4 seconds
Started Mar 10 01:28:05 PM PDT 24
Finished Mar 10 01:28:35 PM PDT 24
Peak memory 249036 kb
Host smart-c5e7d686-71b8-482a-87f8-6924b62ae285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18648
07080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1864807080
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3368227313
Short name T677
Test name
Test status
Simulation time 127206104809 ps
CPU time 1521.63 seconds
Started Mar 10 01:28:04 PM PDT 24
Finished Mar 10 01:53:26 PM PDT 24
Peak memory 290036 kb
Host smart-7114dcec-62ba-4b30-b94c-885dc1ffb23e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368227313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3368227313
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1453917545
Short name T259
Test name
Test status
Simulation time 42865077337 ps
CPU time 3639.73 seconds
Started Mar 10 01:28:03 PM PDT 24
Finished Mar 10 02:28:43 PM PDT 24
Peak memory 289724 kb
Host smart-e44ea2eb-4e22-428e-86ce-bb0e1c6dd241
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453917545 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1453917545
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.544875723
Short name T539
Test name
Test status
Simulation time 114629687528 ps
CPU time 1647.87 seconds
Started Mar 10 01:28:10 PM PDT 24
Finished Mar 10 01:55:38 PM PDT 24
Peak memory 273260 kb
Host smart-fd7b487d-5e4f-4afb-b52a-ee2729a6fc0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544875723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.544875723
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2964665792
Short name T360
Test name
Test status
Simulation time 1545147877 ps
CPU time 97.21 seconds
Started Mar 10 01:28:09 PM PDT 24
Finished Mar 10 01:29:46 PM PDT 24
Peak memory 256272 kb
Host smart-b6022a9f-2b19-4b1c-8810-1df70b4c8450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29646
65792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2964665792
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.555707314
Short name T97
Test name
Test status
Simulation time 3146455711 ps
CPU time 54.2 seconds
Started Mar 10 01:28:09 PM PDT 24
Finished Mar 10 01:29:04 PM PDT 24
Peak memory 248808 kb
Host smart-8176a006-357d-44ab-a6ed-61c1538f6675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55570
7314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.555707314
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.159698554
Short name T622
Test name
Test status
Simulation time 13576401044 ps
CPU time 1384.62 seconds
Started Mar 10 01:28:14 PM PDT 24
Finished Mar 10 01:51:19 PM PDT 24
Peak memory 289904 kb
Host smart-ca8e6ae9-5954-4510-b7ea-9f0a644b071a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159698554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.159698554
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.88491132
Short name T14
Test name
Test status
Simulation time 42139785484 ps
CPU time 1454.6 seconds
Started Mar 10 01:28:15 PM PDT 24
Finished Mar 10 01:52:30 PM PDT 24
Peak memory 281844 kb
Host smart-02c377e8-5330-43db-8486-4b3cc9810258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88491132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.88491132
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1143356115
Short name T309
Test name
Test status
Simulation time 28855504703 ps
CPU time 622.81 seconds
Started Mar 10 01:28:14 PM PDT 24
Finished Mar 10 01:38:38 PM PDT 24
Peak memory 247852 kb
Host smart-b8ff3ea8-5751-4848-a4f5-4185288e8250
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143356115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1143356115
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1909522846
Short name T508
Test name
Test status
Simulation time 17807659 ps
CPU time 2.59 seconds
Started Mar 10 01:28:09 PM PDT 24
Finished Mar 10 01:28:12 PM PDT 24
Peak memory 240784 kb
Host smart-157ba0f9-e5ec-40ba-bf4f-e4a2b27a774f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19095
22846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1909522846
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2495112863
Short name T367
Test name
Test status
Simulation time 385834588 ps
CPU time 32.67 seconds
Started Mar 10 01:28:10 PM PDT 24
Finished Mar 10 01:28:43 PM PDT 24
Peak memory 255944 kb
Host smart-2aecef34-6258-40bc-a6a0-ff272c129173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24951
12863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2495112863
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1975004535
Short name T289
Test name
Test status
Simulation time 1432315890 ps
CPU time 41 seconds
Started Mar 10 01:28:10 PM PDT 24
Finished Mar 10 01:28:52 PM PDT 24
Peak memory 248020 kb
Host smart-0f341d8e-0aa8-4053-859a-2312bddb3cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
04535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1975004535
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.1616329981
Short name T638
Test name
Test status
Simulation time 451240403 ps
CPU time 33.34 seconds
Started Mar 10 01:28:09 PM PDT 24
Finished Mar 10 01:28:43 PM PDT 24
Peak memory 248992 kb
Host smart-3e379d74-937a-44c6-963c-2f275f527119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16163
29981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.1616329981
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.41642245
Short name T260
Test name
Test status
Simulation time 32207216679 ps
CPU time 495.5 seconds
Started Mar 10 01:28:19 PM PDT 24
Finished Mar 10 01:36:34 PM PDT 24
Peak memory 257200 kb
Host smart-a38e64b3-49b8-4378-9545-057cc796409e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41642245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_hand
ler_stress_all.41642245
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2254114778
Short name T440
Test name
Test status
Simulation time 31566425645 ps
CPU time 978.36 seconds
Started Mar 10 01:28:16 PM PDT 24
Finished Mar 10 01:44:35 PM PDT 24
Peak memory 269864 kb
Host smart-c25d2770-252b-43e6-8828-d3fa2d7604d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254114778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2254114778
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.367497551
Short name T597
Test name
Test status
Simulation time 2338530737 ps
CPU time 93.89 seconds
Started Mar 10 01:28:18 PM PDT 24
Finished Mar 10 01:29:52 PM PDT 24
Peak memory 249200 kb
Host smart-6822b686-c0d5-4fe8-a12e-6592a7ad3a27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36749
7551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.367497551
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.276371026
Short name T635
Test name
Test status
Simulation time 948361879 ps
CPU time 18.18 seconds
Started Mar 10 01:28:14 PM PDT 24
Finished Mar 10 01:28:33 PM PDT 24
Peak memory 254724 kb
Host smart-fe98ce17-fff5-45e5-921d-5d07d9d0f38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27637
1026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.276371026
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.608588199
Short name T328
Test name
Test status
Simulation time 12588489110 ps
CPU time 615.09 seconds
Started Mar 10 01:28:17 PM PDT 24
Finished Mar 10 01:38:33 PM PDT 24
Peak memory 273112 kb
Host smart-7ca7a09e-6a05-4b93-b842-1a2f0e9e6e61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608588199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.608588199
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2589577570
Short name T506
Test name
Test status
Simulation time 45078026477 ps
CPU time 1058.02 seconds
Started Mar 10 01:28:18 PM PDT 24
Finished Mar 10 01:45:57 PM PDT 24
Peak memory 271600 kb
Host smart-f295a3ee-9b18-4281-a395-3f858a15b8d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589577570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2589577570
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2721576037
Short name T595
Test name
Test status
Simulation time 137735488 ps
CPU time 9.05 seconds
Started Mar 10 01:28:14 PM PDT 24
Finished Mar 10 01:28:24 PM PDT 24
Peak memory 249008 kb
Host smart-2c737da0-79de-4d8e-aa7e-5fc42d4884c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27215
76037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2721576037
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3893193456
Short name T676
Test name
Test status
Simulation time 525593585 ps
CPU time 18.48 seconds
Started Mar 10 01:28:14 PM PDT 24
Finished Mar 10 01:28:34 PM PDT 24
Peak memory 254640 kb
Host smart-0f9f3d08-72c6-4815-8d64-1a4ada3012d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38931
93456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3893193456
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.909743019
Short name T47
Test name
Test status
Simulation time 2157726931 ps
CPU time 30.38 seconds
Started Mar 10 01:28:15 PM PDT 24
Finished Mar 10 01:28:47 PM PDT 24
Peak memory 254200 kb
Host smart-80f6ee04-7529-4409-b9c8-186d458f31a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90974
3019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.909743019
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.912181103
Short name T386
Test name
Test status
Simulation time 63445912 ps
CPU time 4.46 seconds
Started Mar 10 01:28:13 PM PDT 24
Finished Mar 10 01:28:17 PM PDT 24
Peak memory 240804 kb
Host smart-5071960d-ec80-47fa-bf88-6682232ea566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91218
1103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.912181103
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.1639808879
Short name T574
Test name
Test status
Simulation time 39749054599 ps
CPU time 1675.03 seconds
Started Mar 10 01:28:20 PM PDT 24
Finished Mar 10 01:56:16 PM PDT 24
Peak memory 305600 kb
Host smart-6bca48ab-290a-4592-aff3-464a30f76a51
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639808879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.1639808879
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1562636410
Short name T611
Test name
Test status
Simulation time 27288023422 ps
CPU time 967.86 seconds
Started Mar 10 01:28:23 PM PDT 24
Finished Mar 10 01:44:31 PM PDT 24
Peak memory 269548 kb
Host smart-58a8e34f-ca05-4e42-b5bc-0cd40bc6658e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562636410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1562636410
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2528801218
Short name T388
Test name
Test status
Simulation time 2619938244 ps
CPU time 54.13 seconds
Started Mar 10 01:28:24 PM PDT 24
Finished Mar 10 01:29:18 PM PDT 24
Peak memory 248320 kb
Host smart-d808cde2-0c2f-418a-9b4a-9c45060345c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
01218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2528801218
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1935487600
Short name T581
Test name
Test status
Simulation time 259511340 ps
CPU time 18.49 seconds
Started Mar 10 01:28:20 PM PDT 24
Finished Mar 10 01:28:38 PM PDT 24
Peak memory 252580 kb
Host smart-9250acd7-6fde-4569-aff4-a9c9f20102c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19354
87600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1935487600
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.74948469
Short name T335
Test name
Test status
Simulation time 28157062853 ps
CPU time 1919.9 seconds
Started Mar 10 01:28:21 PM PDT 24
Finished Mar 10 02:00:22 PM PDT 24
Peak memory 282984 kb
Host smart-bcfbd5c4-fe89-43af-a531-4ba1928d1ce0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74948469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.74948469
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3412215044
Short name T669
Test name
Test status
Simulation time 34080187548 ps
CPU time 2062.81 seconds
Started Mar 10 01:28:24 PM PDT 24
Finished Mar 10 02:02:48 PM PDT 24
Peak memory 273220 kb
Host smart-fd2137c8-536f-48b2-879e-79e8870d9677
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412215044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3412215044
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3022802118
Short name T511
Test name
Test status
Simulation time 180367750172 ps
CPU time 567.23 seconds
Started Mar 10 01:28:24 PM PDT 24
Finished Mar 10 01:37:51 PM PDT 24
Peak memory 247572 kb
Host smart-a01c8531-af90-4966-aa75-1f14c80a2639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022802118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3022802118
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.183624299
Short name T425
Test name
Test status
Simulation time 20454225 ps
CPU time 3.87 seconds
Started Mar 10 01:28:22 PM PDT 24
Finished Mar 10 01:28:26 PM PDT 24
Peak memory 240812 kb
Host smart-9fa8cbd2-c067-4fa3-917c-d21bb394e000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18362
4299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.183624299
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2778849890
Short name T653
Test name
Test status
Simulation time 395972749 ps
CPU time 23.28 seconds
Started Mar 10 01:28:19 PM PDT 24
Finished Mar 10 01:28:42 PM PDT 24
Peak memory 255244 kb
Host smart-0fa7dddf-abf3-4921-91cb-5fddb54b40d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27788
49890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2778849890
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.261604621
Short name T625
Test name
Test status
Simulation time 577845725 ps
CPU time 21.76 seconds
Started Mar 10 01:28:25 PM PDT 24
Finished Mar 10 01:28:46 PM PDT 24
Peak memory 247608 kb
Host smart-b3ef3033-9b8e-4df8-83fc-fec7efef5292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26160
4621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.261604621
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2682940983
Short name T364
Test name
Test status
Simulation time 324559366 ps
CPU time 7.25 seconds
Started Mar 10 01:28:17 PM PDT 24
Finished Mar 10 01:28:25 PM PDT 24
Peak memory 248980 kb
Host smart-46b930fb-3b43-4240-b1ec-baf789a8f107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26829
40983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2682940983
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3994109026
Short name T419
Test name
Test status
Simulation time 9033027012 ps
CPU time 1072.11 seconds
Started Mar 10 01:28:27 PM PDT 24
Finished Mar 10 01:46:19 PM PDT 24
Peak memory 273488 kb
Host smart-73e42f3a-e571-45c5-af7b-049506a575b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994109026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3994109026
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1100014529
Short name T623
Test name
Test status
Simulation time 2931244540 ps
CPU time 163.39 seconds
Started Mar 10 01:28:30 PM PDT 24
Finished Mar 10 01:31:13 PM PDT 24
Peak memory 256704 kb
Host smart-ca287be3-fa7a-4504-88a4-9f4f95aa9cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11000
14529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1100014529
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2217950358
Short name T123
Test name
Test status
Simulation time 480427774 ps
CPU time 31.55 seconds
Started Mar 10 01:28:27 PM PDT 24
Finished Mar 10 01:28:59 PM PDT 24
Peak memory 255368 kb
Host smart-94037b59-0f43-4255-80ec-5d90b2405c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22179
50358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2217950358
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2268461546
Short name T320
Test name
Test status
Simulation time 24772044645 ps
CPU time 1435.82 seconds
Started Mar 10 01:28:28 PM PDT 24
Finished Mar 10 01:52:25 PM PDT 24
Peak memory 272440 kb
Host smart-32338656-8736-4db9-a5e8-cad6154a7dc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268461546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2268461546
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1294450697
Short name T556
Test name
Test status
Simulation time 107964319705 ps
CPU time 1749.03 seconds
Started Mar 10 01:28:29 PM PDT 24
Finished Mar 10 01:57:39 PM PDT 24
Peak memory 272720 kb
Host smart-ac7e407c-83f4-411f-a66b-a9156f6b978f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294450697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1294450697
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.2186766019
Short name T694
Test name
Test status
Simulation time 3872519805 ps
CPU time 88.73 seconds
Started Mar 10 01:28:25 PM PDT 24
Finished Mar 10 01:29:54 PM PDT 24
Peak memory 247960 kb
Host smart-14073fdd-d3bb-4468-a158-be7618787639
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186766019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.2186766019
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1738696511
Short name T588
Test name
Test status
Simulation time 1559078140 ps
CPU time 59.75 seconds
Started Mar 10 01:28:23 PM PDT 24
Finished Mar 10 01:29:23 PM PDT 24
Peak memory 257124 kb
Host smart-8322c629-2b70-4ae9-9e00-87aa2fe52cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
96511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1738696511
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.51383031
Short name T54
Test name
Test status
Simulation time 1085210564 ps
CPU time 57.37 seconds
Started Mar 10 01:28:30 PM PDT 24
Finished Mar 10 01:29:28 PM PDT 24
Peak memory 254096 kb
Host smart-93c07fa1-8a50-4c75-b13f-0ff6ed6c682e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51383
031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.51383031
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1602807130
Short name T645
Test name
Test status
Simulation time 9070350369 ps
CPU time 60.84 seconds
Started Mar 10 01:28:28 PM PDT 24
Finished Mar 10 01:29:29 PM PDT 24
Peak memory 255668 kb
Host smart-b29dce0b-7878-42da-b6ec-92452045e58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16028
07130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1602807130
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3029719847
Short name T358
Test name
Test status
Simulation time 805595594 ps
CPU time 20.73 seconds
Started Mar 10 01:28:24 PM PDT 24
Finished Mar 10 01:28:45 PM PDT 24
Peak memory 255612 kb
Host smart-64c7aaeb-0dfd-4031-b22b-38a75efc7f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30297
19847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3029719847
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.3196448283
Short name T256
Test name
Test status
Simulation time 216628109785 ps
CPU time 2169.65 seconds
Started Mar 10 01:28:30 PM PDT 24
Finished Mar 10 02:04:40 PM PDT 24
Peak memory 281788 kb
Host smart-d9a6b8eb-cb4f-46b4-9b97-a3d904ae02a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196448283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.3196448283
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.550683116
Short name T633
Test name
Test status
Simulation time 72011153797 ps
CPU time 1234.41 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 01:49:08 PM PDT 24
Peak memory 286460 kb
Host smart-ea65d4cf-f51c-4508-99f2-2e1725d464e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550683116 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.550683116
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.3863416246
Short name T288
Test name
Test status
Simulation time 11674981475 ps
CPU time 1037.91 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 01:45:51 PM PDT 24
Peak memory 289916 kb
Host smart-ac4df612-1496-4ded-86b8-930285198bed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863416246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.3863416246
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1522766817
Short name T454
Test name
Test status
Simulation time 767724105 ps
CPU time 32.51 seconds
Started Mar 10 01:28:36 PM PDT 24
Finished Mar 10 01:29:08 PM PDT 24
Peak memory 248340 kb
Host smart-6e94d97c-1e80-477d-b179-8e6cc960898b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15227
66817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1522766817
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2001126163
Short name T65
Test name
Test status
Simulation time 615920735 ps
CPU time 45.27 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 01:29:18 PM PDT 24
Peak memory 254684 kb
Host smart-252ac878-63b9-49a8-8a19-f359a78aaf8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20011
26163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2001126163
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3288773117
Short name T240
Test name
Test status
Simulation time 67045487735 ps
CPU time 1931.24 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 02:00:44 PM PDT 24
Peak memory 287512 kb
Host smart-aab9a3cb-826d-4721-8da6-8caa3f8e71db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288773117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3288773117
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2969335848
Short name T93
Test name
Test status
Simulation time 98409153891 ps
CPU time 1414.09 seconds
Started Mar 10 01:28:41 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 272792 kb
Host smart-f022aedd-2289-4b71-89e0-ae12ea4fb19f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969335848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2969335848
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2765580688
Short name T505
Test name
Test status
Simulation time 3899751475 ps
CPU time 88.38 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 01:30:02 PM PDT 24
Peak memory 247944 kb
Host smart-ee0fdb9f-6864-4bfe-bf3c-87da02aac4ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765580688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2765580688
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2716071976
Short name T612
Test name
Test status
Simulation time 442114113 ps
CPU time 37.32 seconds
Started Mar 10 01:28:35 PM PDT 24
Finished Mar 10 01:29:13 PM PDT 24
Peak memory 249008 kb
Host smart-1f36051a-b6cd-4c34-b254-119f2b1c64a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27160
71976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2716071976
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1724352215
Short name T283
Test name
Test status
Simulation time 812897694 ps
CPU time 49.02 seconds
Started Mar 10 01:28:34 PM PDT 24
Finished Mar 10 01:29:23 PM PDT 24
Peak memory 256276 kb
Host smart-412e17f7-5432-4fa9-85f7-e398a1fa26a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
52215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1724352215
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2221325957
Short name T560
Test name
Test status
Simulation time 151370263 ps
CPU time 11.18 seconds
Started Mar 10 01:28:35 PM PDT 24
Finished Mar 10 01:28:46 PM PDT 24
Peak memory 254364 kb
Host smart-819a743f-73c4-43cf-932e-3c6cbd3c776d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22213
25957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2221325957
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1612273813
Short name T698
Test name
Test status
Simulation time 403403890 ps
CPU time 28.87 seconds
Started Mar 10 01:28:33 PM PDT 24
Finished Mar 10 01:29:02 PM PDT 24
Peak memory 248948 kb
Host smart-8b83f91e-c820-45b3-b0dd-c83f5c0e5d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
73813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1612273813
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.4015088107
Short name T268
Test name
Test status
Simulation time 7728673876 ps
CPU time 921.25 seconds
Started Mar 10 01:28:37 PM PDT 24
Finished Mar 10 01:43:59 PM PDT 24
Peak memory 273472 kb
Host smart-e35bb7b6-6d4f-43cd-8551-faca56fead40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015088107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.4015088107
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2396372815
Short name T9
Test name
Test status
Simulation time 29887245071 ps
CPU time 2014.78 seconds
Started Mar 10 01:28:40 PM PDT 24
Finished Mar 10 02:02:16 PM PDT 24
Peak memory 289284 kb
Host smart-1b17d3db-a58e-4e17-b69b-5c9c912e5894
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396372815 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2396372815
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1543166074
Short name T540
Test name
Test status
Simulation time 154215886207 ps
CPU time 1508.58 seconds
Started Mar 10 01:28:40 PM PDT 24
Finished Mar 10 01:53:50 PM PDT 24
Peak memory 272496 kb
Host smart-01fe9acc-82d9-4615-90fb-5cb7a3e91eff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543166074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1543166074
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.78113386
Short name T668
Test name
Test status
Simulation time 4812880724 ps
CPU time 188.05 seconds
Started Mar 10 01:28:39 PM PDT 24
Finished Mar 10 01:31:48 PM PDT 24
Peak memory 251132 kb
Host smart-3ef34fcf-fc38-4003-bf04-8a9e900a5482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78113
386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.78113386
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3186419702
Short name T461
Test name
Test status
Simulation time 103072945 ps
CPU time 12.88 seconds
Started Mar 10 01:28:41 PM PDT 24
Finished Mar 10 01:28:56 PM PDT 24
Peak memory 254684 kb
Host smart-a9816cfa-be03-4543-adab-f669d4f05cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31864
19702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3186419702
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.4070893034
Short name T340
Test name
Test status
Simulation time 303146222971 ps
CPU time 1178.01 seconds
Started Mar 10 01:28:42 PM PDT 24
Finished Mar 10 01:48:21 PM PDT 24
Peak memory 265376 kb
Host smart-f591447b-32ef-4d83-9f46-9dbc473771f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070893034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.4070893034
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.516325322
Short name T208
Test name
Test status
Simulation time 25145940376 ps
CPU time 1260.02 seconds
Started Mar 10 01:28:43 PM PDT 24
Finished Mar 10 01:49:43 PM PDT 24
Peak memory 273572 kb
Host smart-7f71c802-b40a-4a48-9c02-00f0b666b674
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516325322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.516325322
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3838286096
Short name T662
Test name
Test status
Simulation time 43275816227 ps
CPU time 447.17 seconds
Started Mar 10 01:28:43 PM PDT 24
Finished Mar 10 01:36:10 PM PDT 24
Peak memory 247732 kb
Host smart-e328992d-b2c7-457e-8ed1-4176e1cd582b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838286096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3838286096
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.176908771
Short name T477
Test name
Test status
Simulation time 151376086 ps
CPU time 10.53 seconds
Started Mar 10 01:28:37 PM PDT 24
Finished Mar 10 01:28:48 PM PDT 24
Peak memory 248984 kb
Host smart-08a24f04-2505-4337-85f2-aede0c715e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17690
8771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.176908771
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.7867519
Short name T559
Test name
Test status
Simulation time 3510390652 ps
CPU time 51.34 seconds
Started Mar 10 01:28:39 PM PDT 24
Finished Mar 10 01:29:31 PM PDT 24
Peak memory 255476 kb
Host smart-65a47b8a-2f85-42d5-a8bc-0c49e6ab3ca9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78675
19 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.7867519
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.495501652
Short name T520
Test name
Test status
Simulation time 277084011 ps
CPU time 20.84 seconds
Started Mar 10 01:28:37 PM PDT 24
Finished Mar 10 01:28:58 PM PDT 24
Peak memory 253536 kb
Host smart-d7466f9f-f106-4ba4-87a2-752328ee7d35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49550
1652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.495501652
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1485519106
Short name T551
Test name
Test status
Simulation time 352928299 ps
CPU time 32.53 seconds
Started Mar 10 01:28:41 PM PDT 24
Finished Mar 10 01:29:14 PM PDT 24
Peak memory 255728 kb
Host smart-97054d69-59ae-43b6-81ad-d5c328b86b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14855
19106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1485519106
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2308758486
Short name T389
Test name
Test status
Simulation time 440388278534 ps
CPU time 2909.63 seconds
Started Mar 10 01:28:42 PM PDT 24
Finished Mar 10 02:17:13 PM PDT 24
Peak memory 289768 kb
Host smart-bb085344-b145-4314-be2d-bcdbba98dbee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308758486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2308758486
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3420982351
Short name T55
Test name
Test status
Simulation time 393752686121 ps
CPU time 8969.76 seconds
Started Mar 10 01:28:44 PM PDT 24
Finished Mar 10 03:58:15 PM PDT 24
Peak memory 347436 kb
Host smart-db88962b-b32c-4d0e-8f59-a3853ea9a0e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420982351 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3420982351
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.2412536155
Short name T701
Test name
Test status
Simulation time 251112730147 ps
CPU time 2354.94 seconds
Started Mar 10 01:28:48 PM PDT 24
Finished Mar 10 02:08:04 PM PDT 24
Peak memory 288996 kb
Host smart-265a9738-a30e-43e9-bf05-4d5d7f8b25e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412536155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.2412536155
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.657173397
Short name T642
Test name
Test status
Simulation time 13774634246 ps
CPU time 190.45 seconds
Started Mar 10 01:28:48 PM PDT 24
Finished Mar 10 01:31:58 PM PDT 24
Peak memory 256788 kb
Host smart-f6082591-b534-49c4-adc4-75de79545a7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65717
3397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.657173397
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3637288497
Short name T396
Test name
Test status
Simulation time 49778595 ps
CPU time 5.15 seconds
Started Mar 10 01:28:48 PM PDT 24
Finished Mar 10 01:28:54 PM PDT 24
Peak memory 249688 kb
Host smart-04243985-d75f-4a64-b64b-69a8c163ac9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36372
88497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3637288497
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2948658692
Short name T697
Test name
Test status
Simulation time 389367586933 ps
CPU time 1754.81 seconds
Started Mar 10 01:28:48 PM PDT 24
Finished Mar 10 01:58:03 PM PDT 24
Peak memory 273632 kb
Host smart-0791d764-0a29-4ab3-bfdc-cf01482daa73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948658692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2948658692
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.2142719075
Short name T531
Test name
Test status
Simulation time 29987898765 ps
CPU time 947.79 seconds
Started Mar 10 01:28:50 PM PDT 24
Finished Mar 10 01:44:38 PM PDT 24
Peak memory 272732 kb
Host smart-5dfa7a72-7cad-4075-b9a4-6954feca3b09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142719075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.2142719075
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3921604149
Short name T322
Test name
Test status
Simulation time 31021018530 ps
CPU time 428.59 seconds
Started Mar 10 01:28:49 PM PDT 24
Finished Mar 10 01:35:58 PM PDT 24
Peak memory 247872 kb
Host smart-cbeffff1-6dca-4cd2-b141-1ba352214eaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921604149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3921604149
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3465302433
Short name T362
Test name
Test status
Simulation time 767757617 ps
CPU time 47.27 seconds
Started Mar 10 01:28:47 PM PDT 24
Finished Mar 10 01:29:35 PM PDT 24
Peak memory 255752 kb
Host smart-b3798bb3-6fa5-4b8e-ae74-0bd7df769855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34653
02433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3465302433
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1825988906
Short name T470
Test name
Test status
Simulation time 752992379 ps
CPU time 42.16 seconds
Started Mar 10 01:28:50 PM PDT 24
Finished Mar 10 01:29:32 PM PDT 24
Peak memory 255268 kb
Host smart-25e897bc-5e4f-46fb-9b2f-5e9bc44376e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18259
88906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1825988906
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4001770163
Short name T422
Test name
Test status
Simulation time 3921711050 ps
CPU time 59.76 seconds
Started Mar 10 01:28:48 PM PDT 24
Finished Mar 10 01:29:48 PM PDT 24
Peak memory 256200 kb
Host smart-ed2a1cc1-4fd9-4515-aeb1-3cbd37ead8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40017
70163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4001770163
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.333908633
Short name T395
Test name
Test status
Simulation time 103335540 ps
CPU time 6.78 seconds
Started Mar 10 01:28:42 PM PDT 24
Finished Mar 10 01:28:50 PM PDT 24
Peak memory 248972 kb
Host smart-062d4a1e-edde-4846-88e0-13f2179bd4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33390
8633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.333908633
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3909095046
Short name T64
Test name
Test status
Simulation time 10417967557 ps
CPU time 192.6 seconds
Started Mar 10 01:28:53 PM PDT 24
Finished Mar 10 01:32:06 PM PDT 24
Peak memory 257268 kb
Host smart-e4a87503-4d06-4fde-b36d-b6cfd67ee331
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909095046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3909095046
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.2301256857
Short name T524
Test name
Test status
Simulation time 57651407103 ps
CPU time 6265.71 seconds
Started Mar 10 01:28:54 PM PDT 24
Finished Mar 10 03:13:20 PM PDT 24
Peak memory 338328 kb
Host smart-9fa088f8-3376-4850-ab05-c9eb352680e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301256857 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.2301256857
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3995315182
Short name T373
Test name
Test status
Simulation time 54787015536 ps
CPU time 1685.09 seconds
Started Mar 10 01:28:52 PM PDT 24
Finished Mar 10 01:56:58 PM PDT 24
Peak memory 272756 kb
Host smart-8db4b7b9-2434-4648-b9ad-749edd039e3e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995315182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3995315182
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.985615793
Short name T480
Test name
Test status
Simulation time 11291482409 ps
CPU time 218.46 seconds
Started Mar 10 01:28:52 PM PDT 24
Finished Mar 10 01:32:31 PM PDT 24
Peak memory 256404 kb
Host smart-f18d035d-42ba-4b98-8bbc-90d3d7cdca43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98561
5793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.985615793
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.2864399802
Short name T82
Test name
Test status
Simulation time 1340679528 ps
CPU time 34.15 seconds
Started Mar 10 01:28:55 PM PDT 24
Finished Mar 10 01:29:29 PM PDT 24
Peak memory 255364 kb
Host smart-10e20631-cbf8-43aa-9925-6871df8ab7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28643
99802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.2864399802
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2694965488
Short name T626
Test name
Test status
Simulation time 39942880904 ps
CPU time 927.05 seconds
Started Mar 10 01:28:58 PM PDT 24
Finished Mar 10 01:44:25 PM PDT 24
Peak memory 272664 kb
Host smart-ae971f7a-da66-45ec-ae53-b8ba84e4dd1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694965488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2694965488
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3559379084
Short name T319
Test name
Test status
Simulation time 87204759379 ps
CPU time 541.66 seconds
Started Mar 10 01:28:52 PM PDT 24
Finished Mar 10 01:37:54 PM PDT 24
Peak memory 247932 kb
Host smart-a4e5b96e-daff-43a5-a905-b2741eb5841c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559379084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3559379084
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3942118846
Short name T610
Test name
Test status
Simulation time 69355477 ps
CPU time 5.04 seconds
Started Mar 10 01:28:50 PM PDT 24
Finished Mar 10 01:28:56 PM PDT 24
Peak memory 240784 kb
Host smart-c5a68b42-e674-46ec-a671-91a6e11dc598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39421
18846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3942118846
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3460106046
Short name T68
Test name
Test status
Simulation time 44556095 ps
CPU time 5.45 seconds
Started Mar 10 01:28:54 PM PDT 24
Finished Mar 10 01:29:00 PM PDT 24
Peak memory 247264 kb
Host smart-a0eee763-47c0-4b83-831c-2c054c2b56a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34601
06046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3460106046
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.511936489
Short name T590
Test name
Test status
Simulation time 2646723056 ps
CPU time 43.56 seconds
Started Mar 10 01:28:54 PM PDT 24
Finished Mar 10 01:29:38 PM PDT 24
Peak memory 249080 kb
Host smart-968930b7-ffd0-4985-acb4-6622d77ccd95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51193
6489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.511936489
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3064998070
Short name T679
Test name
Test status
Simulation time 244027455 ps
CPU time 16.14 seconds
Started Mar 10 01:28:58 PM PDT 24
Finished Mar 10 01:29:14 PM PDT 24
Peak memory 253288 kb
Host smart-de6209b4-5e7c-4404-b655-61b35cb7edf7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064998070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3064998070
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.336975751
Short name T108
Test name
Test status
Simulation time 17927358504 ps
CPU time 1208.2 seconds
Started Mar 10 01:29:02 PM PDT 24
Finished Mar 10 01:49:11 PM PDT 24
Peak memory 272792 kb
Host smart-b434edeb-3d75-4038-9326-e04894357646
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336975751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.336975751
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1093660277
Short name T66
Test name
Test status
Simulation time 420928056 ps
CPU time 27.82 seconds
Started Mar 10 01:29:02 PM PDT 24
Finished Mar 10 01:29:30 PM PDT 24
Peak memory 253768 kb
Host smart-f7daa8ea-7d89-4b9f-9b2f-bc9d351abd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10936
60277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1093660277
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4216617099
Short name T421
Test name
Test status
Simulation time 473391165 ps
CPU time 17.92 seconds
Started Mar 10 01:29:02 PM PDT 24
Finished Mar 10 01:29:20 PM PDT 24
Peak memory 251876 kb
Host smart-e9b5c71a-3c9d-479c-bcc2-2e94918693cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42166
17099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4216617099
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2902024266
Short name T325
Test name
Test status
Simulation time 229736213476 ps
CPU time 2117.92 seconds
Started Mar 10 01:29:03 PM PDT 24
Finished Mar 10 02:04:21 PM PDT 24
Peak memory 281248 kb
Host smart-81849d91-8d73-4b3b-bc09-099edc4f360b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902024266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2902024266
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.297013246
Short name T410
Test name
Test status
Simulation time 19793098078 ps
CPU time 1296.4 seconds
Started Mar 10 01:29:03 PM PDT 24
Finished Mar 10 01:50:40 PM PDT 24
Peak memory 281844 kb
Host smart-ea5b7394-150f-4072-8ebb-a2a6c9df4263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297013246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.297013246
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2508095759
Short name T692
Test name
Test status
Simulation time 40464903609 ps
CPU time 386.52 seconds
Started Mar 10 01:29:01 PM PDT 24
Finished Mar 10 01:35:28 PM PDT 24
Peak memory 247880 kb
Host smart-c110a3bf-5343-4b56-b427-870599652119
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508095759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2508095759
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.4217402424
Short name T377
Test name
Test status
Simulation time 240972611 ps
CPU time 15.93 seconds
Started Mar 10 01:29:00 PM PDT 24
Finished Mar 10 01:29:16 PM PDT 24
Peak memory 248944 kb
Host smart-e61a2681-9853-4a9a-94fc-d6909e1a967d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42174
02424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4217402424
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1569498711
Short name T37
Test name
Test status
Simulation time 59881700 ps
CPU time 5.81 seconds
Started Mar 10 01:28:59 PM PDT 24
Finished Mar 10 01:29:05 PM PDT 24
Peak memory 239096 kb
Host smart-6390d356-c2a0-443a-a3de-5e253b64e6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
98711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1569498711
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2598351578
Short name T245
Test name
Test status
Simulation time 635016170 ps
CPU time 36.98 seconds
Started Mar 10 01:29:00 PM PDT 24
Finished Mar 10 01:29:37 PM PDT 24
Peak memory 249044 kb
Host smart-c7783bda-8d4f-4823-ae4d-81976a84f182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
51578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2598351578
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2499518682
Short name T472
Test name
Test status
Simulation time 1448038021 ps
CPU time 162.14 seconds
Started Mar 10 01:29:02 PM PDT 24
Finished Mar 10 01:31:44 PM PDT 24
Peak memory 257176 kb
Host smart-1c272e43-e257-4bea-961f-c875677e3694
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499518682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2499518682
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3562082638
Short name T226
Test name
Test status
Simulation time 53280336 ps
CPU time 3.89 seconds
Started Mar 10 01:26:12 PM PDT 24
Finished Mar 10 01:26:16 PM PDT 24
Peak memory 249168 kb
Host smart-d17f3133-64f2-4c27-9ae6-6ae5ddb89bbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3562082638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3562082638
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1369665912
Short name T101
Test name
Test status
Simulation time 58240962392 ps
CPU time 1266.67 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:47:23 PM PDT 24
Peak memory 289984 kb
Host smart-d0ec876a-cef3-4ccc-89d5-bdc2cec05838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369665912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1369665912
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2217682858
Short name T663
Test name
Test status
Simulation time 967692687 ps
CPU time 13.19 seconds
Started Mar 10 01:26:07 PM PDT 24
Finished Mar 10 01:26:21 PM PDT 24
Peak memory 240752 kb
Host smart-27e83f47-76a2-46d1-ad39-fce6e0f935fc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2217682858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2217682858
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.547819323
Short name T591
Test name
Test status
Simulation time 6264165066 ps
CPU time 182.65 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:29:17 PM PDT 24
Peak memory 256412 kb
Host smart-107112df-48ba-4ce7-9f76-86ca92245c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54781
9323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.547819323
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2913879969
Short name T264
Test name
Test status
Simulation time 3003855310 ps
CPU time 47.17 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 255356 kb
Host smart-eb5fc491-581e-4aba-a111-2d8ae8cd36d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29138
79969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2913879969
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3994215760
Short name T69
Test name
Test status
Simulation time 37055382677 ps
CPU time 1384.78 seconds
Started Mar 10 01:26:12 PM PDT 24
Finished Mar 10 01:49:17 PM PDT 24
Peak memory 285076 kb
Host smart-e1c562b4-cc87-4458-80ad-97228faa13dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994215760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3994215760
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3043829712
Short name T613
Test name
Test status
Simulation time 60281531462 ps
CPU time 1565.21 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:52:17 PM PDT 24
Peak memory 285848 kb
Host smart-4ee7c1ee-4435-4c01-94e3-87f25bf4629b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043829712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3043829712
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.4108920376
Short name T303
Test name
Test status
Simulation time 24839278598 ps
CPU time 278.97 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:30:59 PM PDT 24
Peak memory 247596 kb
Host smart-3d4a7c45-7e27-4c6e-83be-2b93e21a686c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108920376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.4108920376
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1659178279
Short name T490
Test name
Test status
Simulation time 1163756980 ps
CPU time 40.68 seconds
Started Mar 10 01:26:12 PM PDT 24
Finished Mar 10 01:26:54 PM PDT 24
Peak memory 249008 kb
Host smart-54ba3d97-6b2f-4a44-bb4c-5ad52ad7afbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
78279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1659178279
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.2677755131
Short name T562
Test name
Test status
Simulation time 444711210 ps
CPU time 33.37 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:39 PM PDT 24
Peak memory 247476 kb
Host smart-22e80112-b56d-483d-b47f-979702f9c4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26777
55131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.2677755131
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2605019041
Short name T79
Test name
Test status
Simulation time 2906604723 ps
CPU time 46.64 seconds
Started Mar 10 01:26:02 PM PDT 24
Finished Mar 10 01:26:51 PM PDT 24
Peak memory 247348 kb
Host smart-bab4b7c3-fd1b-4537-aa80-aa38436fec23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
19041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2605019041
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.807915083
Short name T523
Test name
Test status
Simulation time 176890247 ps
CPU time 14.15 seconds
Started Mar 10 01:26:04 PM PDT 24
Finished Mar 10 01:26:20 PM PDT 24
Peak memory 249036 kb
Host smart-fd2226f3-a694-4169-90d2-16d2f1ad1d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80791
5083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.807915083
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1018381516
Short name T224
Test name
Test status
Simulation time 20217469 ps
CPU time 3.15 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:23 PM PDT 24
Peak memory 249132 kb
Host smart-a531c0a9-40ca-4623-a2e6-b8318f76a5e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1018381516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1018381516
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.140004288
Short name T110
Test name
Test status
Simulation time 10004728974 ps
CPU time 874.86 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:40:52 PM PDT 24
Peak memory 267504 kb
Host smart-b37e0560-4afb-4b7d-8edb-9ae7bee95f2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140004288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.140004288
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.764011316
Short name T130
Test name
Test status
Simulation time 229384903 ps
CPU time 13.03 seconds
Started Mar 10 01:26:07 PM PDT 24
Finished Mar 10 01:26:20 PM PDT 24
Peak memory 240780 kb
Host smart-efacfceb-8f1d-4945-a7ac-37ee6b5ef454
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=764011316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.764011316
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4000748647
Short name T555
Test name
Test status
Simulation time 3899674632 ps
CPU time 240.54 seconds
Started Mar 10 01:26:07 PM PDT 24
Finished Mar 10 01:30:08 PM PDT 24
Peak memory 256504 kb
Host smart-e3e77e92-7d64-4dd1-b716-d91ebfa43733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40007
48647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4000748647
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2547587421
Short name T25
Test name
Test status
Simulation time 5547840632 ps
CPU time 23.71 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 254596 kb
Host smart-cd78ce89-a0ef-4f01-8cf0-97ecd2c26476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25475
87421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2547587421
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4001923916
Short name T70
Test name
Test status
Simulation time 14316432481 ps
CPU time 1238.36 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:46:55 PM PDT 24
Peak memory 270988 kb
Host smart-390f2d83-1fa5-400b-9845-4f6c6d08fbca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001923916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4001923916
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2220750854
Short name T323
Test name
Test status
Simulation time 196719101235 ps
CPU time 563.81 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:35:36 PM PDT 24
Peak memory 255076 kb
Host smart-08bd00cc-9001-47d0-b9fc-e254a0590878
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220750854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2220750854
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.662832666
Short name T286
Test name
Test status
Simulation time 447452615 ps
CPU time 37.27 seconds
Started Mar 10 01:26:05 PM PDT 24
Finished Mar 10 01:26:43 PM PDT 24
Peak memory 255792 kb
Host smart-01bca15b-be55-4136-869e-570d00aff869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66283
2666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.662832666
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.447917091
Short name T206
Test name
Test status
Simulation time 1780387076 ps
CPU time 44.55 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:27:04 PM PDT 24
Peak memory 247684 kb
Host smart-b15c7e97-944f-4d40-993b-5382f2a83ae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44791
7091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.447917091
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.81867610
Short name T353
Test name
Test status
Simulation time 214559843 ps
CPU time 7.15 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:24 PM PDT 24
Peak memory 253872 kb
Host smart-9ada7824-3944-4251-a742-71ee66bac3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81867
610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.81867610
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.2344643015
Short name T583
Test name
Test status
Simulation time 1691015393 ps
CPU time 26.24 seconds
Started Mar 10 01:26:08 PM PDT 24
Finished Mar 10 01:26:35 PM PDT 24
Peak memory 248920 kb
Host smart-aa386fc4-af4c-4192-9f6a-08f418e4579a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23446
43015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2344643015
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2151042718
Short name T95
Test name
Test status
Simulation time 30743910991 ps
CPU time 2826.05 seconds
Started Mar 10 01:26:06 PM PDT 24
Finished Mar 10 02:13:13 PM PDT 24
Peak memory 322616 kb
Host smart-3a2c0f00-64e8-4fd8-b647-9088f65d58e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151042718 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2151042718
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3109862660
Short name T195
Test name
Test status
Simulation time 25832992 ps
CPU time 2.58 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:20 PM PDT 24
Peak memory 249096 kb
Host smart-554b3d22-4d63-405a-bbf4-afadacef1769
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3109862660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3109862660
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1072518368
Short name T112
Test name
Test status
Simulation time 87554763167 ps
CPU time 1198.64 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:46:14 PM PDT 24
Peak memory 289392 kb
Host smart-432556e3-7b03-44d9-97fe-cad533217ba8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072518368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1072518368
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.429824023
Short name T547
Test name
Test status
Simulation time 659196745 ps
CPU time 9.46 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:30 PM PDT 24
Peak memory 240708 kb
Host smart-9788f20b-0d5e-4153-ad04-13e7f75ce09b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=429824023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.429824023
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.866621872
Short name T493
Test name
Test status
Simulation time 1034349884 ps
CPU time 92.95 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:27:48 PM PDT 24
Peak memory 249036 kb
Host smart-d2ce96fd-250b-42f1-abd5-2b6c1dc31add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86662
1872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.866621872
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1090581539
Short name T670
Test name
Test status
Simulation time 2125930725 ps
CPU time 37.18 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:55 PM PDT 24
Peak memory 255400 kb
Host smart-eb8ab895-139b-4e72-8852-8a0b37a29725
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
81539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1090581539
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.744073404
Short name T296
Test name
Test status
Simulation time 11264970631 ps
CPU time 1091.21 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:44:27 PM PDT 24
Peak memory 273652 kb
Host smart-34106a99-701a-4dcc-a3ca-83ffd49c71f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744073404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.744073404
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.703026033
Short name T417
Test name
Test status
Simulation time 136998096013 ps
CPU time 2070.97 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 02:00:49 PM PDT 24
Peak memory 273584 kb
Host smart-fab0ed8e-5422-4e65-879a-29df6c37fcc7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703026033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.703026033
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.4281477932
Short name T207
Test name
Test status
Simulation time 5609886563 ps
CPU time 238.01 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:30:16 PM PDT 24
Peak memory 255108 kb
Host smart-6883c621-e899-4231-8495-0faa0f68d54c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281477932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.4281477932
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3314795581
Short name T381
Test name
Test status
Simulation time 3585624254 ps
CPU time 12.35 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:29 PM PDT 24
Peak memory 249052 kb
Host smart-471e0325-37eb-4e68-b529-0b65f2075f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33147
95581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3314795581
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3732185999
Short name T375
Test name
Test status
Simulation time 202639051 ps
CPU time 4.99 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:22 PM PDT 24
Peak memory 249564 kb
Host smart-b96ec145-18d2-45e2-9600-6e20e0eb4d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37321
85999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3732185999
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2090451097
Short name T370
Test name
Test status
Simulation time 269032318 ps
CPU time 28.41 seconds
Started Mar 10 01:26:07 PM PDT 24
Finished Mar 10 01:26:36 PM PDT 24
Peak memory 247472 kb
Host smart-fe7d58f6-2887-46ec-a5a3-8ebee16f66b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
51097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2090451097
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1870476213
Short name T10
Test name
Test status
Simulation time 315669227 ps
CPU time 25.11 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:41 PM PDT 24
Peak memory 249036 kb
Host smart-f6733abe-773a-44d3-ad2b-b2902084a762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18704
76213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1870476213
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3298784074
Short name T59
Test name
Test status
Simulation time 170989508006 ps
CPU time 3007.45 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 02:16:26 PM PDT 24
Peak memory 289352 kb
Host smart-d2e785c3-3dbf-4e78-a0c0-26bb3efed0d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298784074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3298784074
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1259513066
Short name T212
Test name
Test status
Simulation time 93039805122 ps
CPU time 1420.96 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:49:57 PM PDT 24
Peak memory 287456 kb
Host smart-95dc0550-c917-4be3-a1f2-f1b91c64ac7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259513066 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1259513066
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1797897137
Short name T220
Test name
Test status
Simulation time 200909845 ps
CPU time 3.54 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:23 PM PDT 24
Peak memory 249112 kb
Host smart-357773bf-7d32-4da5-bcba-8a15fb30f5ce
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1797897137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1797897137
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1298534098
Short name T566
Test name
Test status
Simulation time 36381712347 ps
CPU time 2161.39 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 02:02:15 PM PDT 24
Peak memory 289000 kb
Host smart-71196054-7534-46ea-93c1-b65f3b7fc7c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298534098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1298534098
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.821781345
Short name T535
Test name
Test status
Simulation time 1718727611 ps
CPU time 20.56 seconds
Started Mar 10 01:26:26 PM PDT 24
Finished Mar 10 01:26:46 PM PDT 24
Peak memory 240784 kb
Host smart-58fb583a-1222-45b8-bb62-5047f050b8b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=821781345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.821781345
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.402461182
Short name T488
Test name
Test status
Simulation time 1806260463 ps
CPU time 39.17 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:53 PM PDT 24
Peak memory 256324 kb
Host smart-58360407-63b3-4451-83d2-90693ee0a454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40246
1182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.402461182
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3995250868
Short name T636
Test name
Test status
Simulation time 814631908 ps
CPU time 33.76 seconds
Started Mar 10 01:26:13 PM PDT 24
Finished Mar 10 01:26:47 PM PDT 24
Peak memory 255336 kb
Host smart-00d4f9f3-8c08-45de-9419-2a33c806a5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39952
50868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3995250868
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2383682238
Short name T699
Test name
Test status
Simulation time 43611246136 ps
CPU time 2733.18 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 02:11:47 PM PDT 24
Peak memory 289404 kb
Host smart-6215e4eb-5561-4242-b4db-a77a52b930cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383682238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2383682238
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3858949441
Short name T637
Test name
Test status
Simulation time 48171169809 ps
CPU time 508.75 seconds
Started Mar 10 01:26:10 PM PDT 24
Finished Mar 10 01:34:40 PM PDT 24
Peak memory 247960 kb
Host smart-9ce59392-195f-40d1-a76a-ba0dc5e35700
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858949441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3858949441
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3450482822
Short name T651
Test name
Test status
Simulation time 897333478 ps
CPU time 14.03 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:33 PM PDT 24
Peak memory 253980 kb
Host smart-fa1623d1-35bd-4d7c-8d45-a63f968f5568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504
82822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3450482822
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.1741685370
Short name T431
Test name
Test status
Simulation time 482736428 ps
CPU time 13.29 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:34 PM PDT 24
Peak memory 254016 kb
Host smart-d15f691f-e5d1-40c9-bc00-6cb655a10e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17416
85370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.1741685370
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2829164617
Short name T76
Test name
Test status
Simulation time 914277268 ps
CPU time 43.47 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 01:26:58 PM PDT 24
Peak memory 247280 kb
Host smart-794c78ff-c044-4e81-95c5-4f477357ee94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291
64617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2829164617
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2442324905
Short name T649
Test name
Test status
Simulation time 831723604 ps
CPU time 51.92 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:27:11 PM PDT 24
Peak memory 255860 kb
Host smart-ec428c34-61a6-4163-8197-aa837c9f2770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24423
24905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2442324905
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1996861484
Short name T86
Test name
Test status
Simulation time 21346914399 ps
CPU time 1851.67 seconds
Started Mar 10 01:26:24 PM PDT 24
Finished Mar 10 01:57:16 PM PDT 24
Peak memory 297792 kb
Host smart-98c605c8-d120-4d51-96e1-db3bc77430c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996861484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1996861484
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1774216979
Short name T222
Test name
Test status
Simulation time 116942846 ps
CPU time 2.95 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:26:21 PM PDT 24
Peak memory 249168 kb
Host smart-224f4aa4-1375-4ece-9757-475b9e2e58a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1774216979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1774216979
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1269035005
Short name T483
Test name
Test status
Simulation time 49569348095 ps
CPU time 1495.08 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:51:14 PM PDT 24
Peak memory 265460 kb
Host smart-98e34ea7-e493-41c7-83bb-c18cef95301f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269035005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1269035005
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3710227163
Short name T74
Test name
Test status
Simulation time 771993294 ps
CPU time 33.93 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:52 PM PDT 24
Peak memory 240768 kb
Host smart-54531833-36c4-471e-bbf6-220c951a559d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3710227163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3710227163
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1099506786
Short name T233
Test name
Test status
Simulation time 801367333 ps
CPU time 8.75 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:26:28 PM PDT 24
Peak memory 248552 kb
Host smart-98d8af9e-ef5c-4e71-8bfb-892ec6d883f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10995
06786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1099506786
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2352273232
Short name T257
Test name
Test status
Simulation time 260211431 ps
CPU time 22.43 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:26:38 PM PDT 24
Peak memory 247412 kb
Host smart-e52cab94-ee57-4358-bdb9-df42ca5c8a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522
73232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2352273232
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3642712630
Short name T689
Test name
Test status
Simulation time 107755705905 ps
CPU time 3158.94 seconds
Started Mar 10 01:26:23 PM PDT 24
Finished Mar 10 02:19:02 PM PDT 24
Peak memory 287728 kb
Host smart-672ed1a9-4dc7-48e1-90f7-5752c965aff3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642712630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3642712630
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1666076497
Short name T532
Test name
Test status
Simulation time 8626790845 ps
CPU time 253.12 seconds
Started Mar 10 01:26:19 PM PDT 24
Finished Mar 10 01:30:32 PM PDT 24
Peak memory 247960 kb
Host smart-1376b24b-9ebf-425b-887e-9122173cccd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666076497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1666076497
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1312910256
Short name T627
Test name
Test status
Simulation time 678978108 ps
CPU time 28.46 seconds
Started Mar 10 01:26:13 PM PDT 24
Finished Mar 10 01:26:42 PM PDT 24
Peak memory 248996 kb
Host smart-60cb04fa-a00a-4a11-83ea-439600451452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13129
10256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1312910256
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.476377079
Short name T402
Test name
Test status
Simulation time 222911311 ps
CPU time 14.85 seconds
Started Mar 10 01:26:17 PM PDT 24
Finished Mar 10 01:26:32 PM PDT 24
Peak memory 247252 kb
Host smart-588b149b-beb5-46f9-8405-530f7a422274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47637
7079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.476377079
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.654890835
Short name T271
Test name
Test status
Simulation time 67479472 ps
CPU time 5.45 seconds
Started Mar 10 01:26:20 PM PDT 24
Finished Mar 10 01:26:25 PM PDT 24
Peak memory 240792 kb
Host smart-8f2d2be5-2772-474e-9f0d-11ceec558f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65489
0835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.654890835
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.2467329214
Short name T445
Test name
Test status
Simulation time 1771496340 ps
CPU time 52.5 seconds
Started Mar 10 01:26:18 PM PDT 24
Finished Mar 10 01:27:11 PM PDT 24
Peak memory 249016 kb
Host smart-ff145883-2f83-4e13-be17-161d845c0bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673
29214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.2467329214
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.519853138
Short name T399
Test name
Test status
Simulation time 709995609 ps
CPU time 55.98 seconds
Started Mar 10 01:26:16 PM PDT 24
Finished Mar 10 01:27:12 PM PDT 24
Peak memory 257172 kb
Host smart-99bbcc81-ea5e-4ee1-a93b-13c440753e2f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519853138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.519853138
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1030155361
Short name T117
Test name
Test status
Simulation time 143625176277 ps
CPU time 5132.51 seconds
Started Mar 10 01:26:14 PM PDT 24
Finished Mar 10 02:51:47 PM PDT 24
Peak memory 321680 kb
Host smart-10afccde-b6e2-4615-b6fc-28cfc6faf5dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030155361 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1030155361
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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