Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T113,T201
1	1	Covered	T2,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	15187	0	0
DisabledNoTrigBkwd_A	2147483647	783298	0	0
DisabledNoTrigFwd_A	2147483647	1472607284	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	15187	0	0
T59	0	505	0	0
T113	0	1606	0	0
T201	974	238	0	0
T202	4284	655	0	0
T203	0	543	0	0
T204	0	201	0	0
T205	0	855	0	0
T206	0	696	0	0
T207	4025	1407	0	0
T208	0	416	0	0
T209	0	613	0	0
T210	0	1432	0	0
T211	0	912	0	0
T212	0	753	0	0
T213	0	522	0	0
T214	0	1302	0	0
T215	0	444	0	0
T216	0	510	0	0
T217	0	731	0	0
T218	0	846	0	0
T219	20235	0	0	0
T220	16176	0	0	0
T221	33919	0	0	0
T222	37798	0	0	0
T223	82452	0	0	0
T224	39992	0	0	0
T225	8458	0	0	0
T226	1045188	0	0	0
T227	229436	0	0	0
T228	42562	0	0	0
T229	800003	0	0	0
T230	50116	0	0	0
T231	368403	0	0	0
T232	18050	0	0	0
T233	234538	0	0	0
T234	634703	0	0	0
T235	30724	0	0	0
T236	6017	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	783298	0	0
T2	536400	3407	0	0
T3	2273664	1272	0	0
T4	402968	4955	0	0
T5	1663840	447	0	0
T6	301262	2	0	0
T11	0	1149	0	0
T12	0	263	0	0
T14	0	4012	0	0
T15	185860	41	0	0
T16	186188	21	0	0
T17	13148	2	0	0
T18	148452	301	0	0
T19	83924	0	0	0
T21	1130972	208	0	0
T24	0	169	0	0
T29	0	5	0	0
T31	40103	0	0	0
T36	0	1306	0	0
T39	0	1	0	0
T40	0	472	0	0
T41	0	849	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1472607284	0	0
T1	3579856	2687576	0	0
T2	715200	220924	0	0
T3	3031552	2268598	0	0
T4	402968	205130	0	0
T5	1663840	835943	0	0
T15	185860	68548	0	0
T16	186188	83611	0	0
T17	13148	4964	0	0
T18	148452	76428	0	0
T19	83924	65431	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T212,T213
1	1	Covered	T15,T4,T16

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T15,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658350810	4715	0	0
DisabledNoTrigBkwd_A	658350810	214719	0	0
DisabledNoTrigFwd_A	658350810	331698888	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	4715	0	0
T207	4025	1407	0	0
T212	0	753	0	0
T213	0	522	0	0
T214	0	1302	0	0
T217	0	731	0	0
T228	42562	0	0	0
T229	800003	0	0	0
T230	50116	0	0	0
T231	368403	0	0	0
T232	18050	0	0	0
T233	234538	0	0	0
T234	634703	0	0	0
T235	30724	0	0	0
T236	6017	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	214719	0	0
T4	100742	3244	0	0
T5	415960	447	0	0
T6	301262	0	0	0
T11	0	402	0	0
T12	0	263	0	0
T14	0	4	0	0
T15	46465	9	0	0
T16	46547	13	0	0
T17	3287	0	0	0
T18	37113	267	0	0
T19	20981	0	0	0
T21	282743	27	0	0
T31	40103	0	0	0
T40	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	331698888	0	0
T1	894964	894905	0	0
T2	178800	178791	0	0
T3	757888	757813	0	0
T4	100742	2862	0	0
T5	415960	2000	0	0
T15	46465	3524	0	0
T16	46547	2671	0	0
T17	3287	582	0	0
T18	37113	11437	0	0
T19	20981	20900	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T201,T204,T208
1	1	Covered	T2,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658350810	4153	0	0
DisabledNoTrigBkwd_A	658350810	206834	0	0
DisabledNoTrigFwd_A	658350810	366627701	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	4153	0	0
T201	974	238	0	0
T202	2142	0	0	0
T204	0	201	0	0
T208	0	416	0	0
T210	0	1432	0	0
T211	0	912	0	0
T215	0	444	0	0
T216	0	510	0	0
T219	20235	0	0	0
T220	16176	0	0	0
T221	33919	0	0	0
T222	18899	0	0	0
T223	41226	0	0	0
T224	19996	0	0	0
T225	4229	0	0	0
T226	522594	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	206834	0	0
T2	178800	1273	0	0
T3	757888	1261	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	2082	0	0
T15	46465	12	0	0
T16	46547	6	0	0
T17	3287	2	0	0
T18	37113	2	0	0
T19	20981	0	0	0
T21	282743	16	0	0
T41	0	849	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	366627701	0	0
T1	894964	894905	0	0
T2	178800	6450	0	0
T3	757888	1640	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	16279	0	0
T16	46547	3633	0	0
T17	3287	586	0	0
T18	37113	17870	0	0
T19	20981	20900	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T202,T203,T218
1	1	Covered	T2,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658350810	2044	0	0
DisabledNoTrigBkwd_A	658350810	196743	0	0
DisabledNoTrigFwd_A	658350810	370173138	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	2044	0	0
T46	25464	0	0	0
T90	39606	0	0	0
T202	2142	655	0	0
T203	0	543	0	0
T218	0	846	0	0
T222	18899	0	0	0
T223	41226	0	0	0
T224	19996	0	0	0
T225	4229	0	0	0
T226	522594	0	0	0
T227	229436	0	0	0
T237	56760	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	196743	0	0
T2	178800	1301	0	0
T3	757888	4	0	0
T4	100742	1711	0	0
T5	415960	0	0	0
T6	0	2	0	0
T14	0	1922	0	0
T15	46465	2	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	32	0	0
T19	20981	0	0	0
T21	282743	56	0	0
T39	0	1	0	0
T40	0	471	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	370173138	0	0
T1	894964	894905	0	0
T2	178800	24889	0	0
T3	757888	755532	0	0
T4	100742	800	0	0
T5	415960	2035	0	0
T15	46465	39376	0	0
T16	46547	46476	0	0
T17	3287	590	0	0
T18	37113	21764	0	0
T19	20981	2731	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T15
1	1	Covered	T2,T3,T15

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T59,T113,T205
1	1	Covered	T2,T3,T15

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	658350810	4275	0	0
DisabledNoTrigBkwd_A	658350810	165002	0	0
DisabledNoTrigFwd_A	658350810	404107557	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	4275	0	0
T27	46214	0	0	0
T59	2743	505	0	0
T60	5123	0	0	0
T61	22772	0	0	0
T62	847810	0	0	0
T63	15953	0	0	0
T64	79742	0	0	0
T65	206267	0	0	0
T66	29104	0	0	0
T67	4154	0	0	0
T113	0	1606	0	0
T205	0	855	0	0
T206	0	696	0	0
T209	0	613	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	165002	0	0
T2	178800	833	0	0
T3	757888	7	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	746	0	0
T14	0	4	0	0
T15	46465	18	0	0
T16	46547	2	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	109	0	0
T24	0	169	0	0
T29	0	5	0	0
T36	0	1306	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	404107557	0	0
T1	894964	2861	0	0
T2	178800	10794	0	0
T3	757888	753613	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	9369	0	0
T16	46547	30831	0	0
T17	3287	3206	0	0
T18	37113	25357	0	0
T19	20981	20900	0	0