Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.63	100.00	97.78	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.96	100.00		99.87			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T20
1	1	1	Covered	T2,T3,T15

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T17
1	0	1	Covered	T2,T15,T16
1	1	0	Covered	T3,T18,T19
1	1	1	Covered	T3,T18,T19

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T18,T19
0	1	Covered	T21,T22,T23
1	0	Covered	T3,T24,T23

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T18,T19
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T3,T24,T23

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T18,T19
1	0	Covered	T25
1	1	Covered	T21,T22,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T3,T4

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T5,T17

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T15,T4

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T15,T16,T18

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T4

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T8,T9,T10
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T15
Phase1St	193	Covered	T2,T3,T15
Phase2St	210	Covered	T2,T3,T15
Phase3St	228	Covered	T2,T3,T15
TerminalSt	244	Covered	T2,T3,T15
TimeoutSt	154	Covered	T3,T18,T19

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	279	Covered	T8,T9,T10
IdleSt->Phase0St	147	Covered	T2,T3,T15
IdleSt->TimeoutSt	154	Covered	T3,T18,T19
Phase0St->FsmErrorSt	279	Not Covered
Phase0St->IdleSt	189	Covered	T26,T24,T27
Phase0St->Phase1St	193	Covered	T2,T3,T15
Phase1St->FsmErrorSt	279	Not Covered
Phase1St->IdleSt	206	Covered	T14,T24,T28
Phase1St->Phase2St	210	Covered	T2,T3,T15
Phase2St->FsmErrorSt	279	Not Covered
Phase2St->IdleSt	224	Covered	T14,T29,T30
Phase2St->Phase3St	228	Covered	T2,T3,T15
Phase3St->FsmErrorSt	279	Not Covered
Phase3St->IdleSt	240	Covered	T2,T29,T30
Phase3St->TerminalSt	244	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	279	Not Covered
TerminalSt->IdleSt	256	Covered	T2,T3,T4
TimeoutSt->FsmErrorSt	279	Not Covered
TimeoutSt->IdleSt	176	Covered	T19,T21,T31
TimeoutSt->Phase0St	167	Covered	T3,T21,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T18,T19
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T31
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T24,T27
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T24,T28
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T29,T30
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	1065	0	0
CheckAccumTrig0_A	2147483647	2337	0	0
CheckAccumTrig1_A	2147483647	100	0	0
CheckClr_A	2147483647	1103	0	0
CheckEn_A	2147483647	1114218728	0	0
CheckPhase0_A	2147483647	2619	0	0
CheckPhase1_A	2147483647	2556	0	0
CheckPhase2_A	2147483647	2496	0	0
CheckPhase3_A	2147483647	2440	0	0
CheckTimeout0_A	2147483647	5211	0	0
CheckTimeoutSt1_A	2147483647	558093	0	0
CheckTimeoutSt2_A	2147483647	4865	0	0
CheckTimeoutStTrig_A	2147483647	241	0	0
ErrorStAllEscAsserted_A	2147483647	5618	0	0
ErrorStIsTerminal_A	2147483647	4658	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065	0	0
T8	169928	296	0	0
T9	0	269	0	0
T10	0	132	0	0
T24	1086408	0	0	0
T26	755352	0	0	0
T28	66856	0	0	0
T30	974336	0	0	0
T32	0	229	0	0
T33	0	139	0	0
T34	40236	0	0	0
T35	133816	0	0	0
T36	694632	0	0	0
T37	184124	0	0	0
T38	1303104	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2337	0	0
T2	536400	7	0	0
T3	2273664	3	0	0
T4	402968	4	0	0
T5	1663840	1	0	0
T6	301262	1	0	0
T11	0	5	0	0
T12	0	1	0	0
T14	0	6	0	0
T15	185860	5	0	0
T16	186188	3	0	0
T17	13148	1	0	0
T18	148452	3	0	0
T19	83924	0	0	0
T21	1130972	4	0	0
T24	0	4	0	0
T29	0	1	0	0
T31	40103	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	100	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T23	541623	1	0	0
T24	0	1	0	0
T27	92428	1	0	0
T42	683555	1	0	0
T43	364916	2	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	2743	0	0	0
T60	5123	0	0	0
T61	45544	0	0	0
T62	1695620	0	0	0
T63	31906	0	0	0
T64	159484	0	0	0
T65	412534	0	0	0
T66	58208	0	0	0
T67	4154	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1103	0	0
T2	536400	4	0	0
T3	2273664	3	0	0
T4	402968	2	0	0
T5	1663840	0	0	0
T6	301262	0	0	0
T11	0	2	0	0
T14	0	3	0	0
T15	139395	1	0	0
T16	186188	0	0	0
T17	13148	0	0	0
T18	148452	0	0	0
T19	83924	0	0	0
T21	1130972	0	0	0
T22	0	1	0	0
T23	0	6	0	0
T24	0	6	0	0
T26	0	5	0	0
T27	0	7	0	0
T28	0	4	0	0
T29	0	12	0	0
T30	0	3	0	0
T31	40103	0	0	0
T35	0	2	0	0
T39	70682	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T60	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1114218728	0	0
T1	3579856	2687573	0	0
T2	715200	220924	0	0
T3	3031552	2268154	0	0
T4	402968	205130	0	0
T5	1663840	835943	0	0
T15	185860	32704	0	0
T16	186188	67380	0	0
T17	13148	4963	0	0
T18	148452	49799	0	0
T19	83924	65428	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2619	0	0
T2	536400	7	0	0
T3	2273664	4	0	0
T4	402968	4	0	0
T5	1663840	1	0	0
T6	301262	1	0	0
T11	0	5	0	0
T12	0	1	0	0
T14	0	6	0	0
T15	185860	5	0	0
T16	186188	3	0	0
T17	13148	1	0	0
T18	148452	4	0	0
T19	83924	0	0	0
T21	1130972	5	0	0
T24	0	3	0	0
T29	0	1	0	0
T31	40103	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2556	0	0
T2	536400	7	0	0
T3	2273664	4	0	0
T4	402968	4	0	0
T5	1663840	1	0	0
T6	301262	1	0	0
T11	0	5	0	0
T12	0	1	0	0
T14	0	5	0	0
T15	185860	5	0	0
T16	186188	3	0	0
T17	13148	1	0	0
T18	148452	4	0	0
T19	83924	0	0	0
T21	1130972	5	0	0
T24	0	3	0	0
T29	0	1	0	0
T31	40103	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2496	0	0
T2	536400	7	0	0
T3	2273664	4	0	0
T4	402968	4	0	0
T5	1663840	1	0	0
T6	301262	1	0	0
T11	0	5	0	0
T12	0	1	0	0
T14	0	3	0	0
T15	185860	5	0	0
T16	186188	3	0	0
T17	13148	1	0	0
T18	148452	3	0	0
T19	83924	0	0	0
T21	1130972	5	0	0
T24	0	3	0	0
T29	0	1	0	0
T31	40103	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2440	0	0
T2	536400	6	0	0
T3	2273664	4	0	0
T4	402968	4	0	0
T5	1663840	1	0	0
T6	301262	1	0	0
T11	0	5	0	0
T12	0	1	0	0
T14	0	3	0	0
T15	185860	4	0	0
T16	186188	3	0	0
T17	13148	1	0	0
T18	148452	3	0	0
T19	83924	0	0	0
T21	1130972	5	0	0
T24	0	3	0	0
T29	0	1	0	0
T31	40103	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5211	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T6	903786	0	0	0
T7	1504040	0	0	0
T11	1316592	0	0	0
T12	341541	0	0	0
T13	306561	0	0	0
T14	1336959	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	74226	1	0	0
T19	41962	4	0	0
T21	848229	2	0	0
T22	0	3	0	0
T23	0	375	0	0
T24	0	3	0	0
T26	0	29	0	0
T27	0	4	0	0
T30	0	1	0	0
T31	120309	8	0	0
T39	212046	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T42	0	16	0	0
T43	0	7	0	0
T61	0	2	0	0
T64	0	1	0	0
T66	0	16	0	0
T68	0	2	0	0
T69	28870	5	0	0
T70	0	2	0	0
T71	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	558093	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T6	903786	0	0	0
T7	1504040	0	0	0
T11	1316592	0	0	0
T12	341541	0	0	0
T13	306561	0	0	0
T14	1336959	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	74226	605	0	0
T19	41962	847	0	0
T21	848229	172	0	0
T22	0	466	0	0
T23	0	60057	0	0
T24	0	160	0	0
T26	0	1253	0	0
T27	0	123	0	0
T30	0	42	0	0
T31	120309	1333	0	0
T39	212046	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T42	0	2346	0	0
T43	0	629	0	0
T61	0	124	0	0
T64	0	121	0	0
T66	0	937	0	0
T68	0	263	0	0
T69	28870	486	0	0
T70	0	605	0	0
T71	0	933	0	0
T72	0	167	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4865	0	0
T6	602524	0	0	0
T7	3008080	0	0	0
T11	1755456	0	0	0
T12	455388	0	0	0
T13	408748	0	0	0
T14	1782612	0	0	0
T19	20981	4	0	0
T21	565486	1	0	0
T23	0	364	0	0
T24	0	2	0	0
T26	0	29	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	160412	8	0	0
T39	282728	0	0	0
T40	301120	0	0	0
T41	1021306	0	0	0
T42	0	11	0	0
T43	0	8	0	0
T45	0	1	0	0
T61	0	2	0	0
T64	0	1	0	0
T66	0	16	0	0
T68	0	2	0	0
T69	43305	5	0	0
T70	0	1	0	0
T71	0	8	0	0
T73	0	11	0	0
T74	0	255	0	0
T75	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	241	0	0
T6	602524	0	0	0
T7	752020	0	0	0
T11	877728	0	0	0
T12	227694	0	0	0
T13	204374	0	0	0
T14	891306	0	0	0
T18	37113	0	0	0
T21	565486	1	0	0
T22	0	2	0	0
T23	1083246	8	0	0
T27	92428	0	0	0
T31	80206	0	0	0
T39	141364	0	0	0
T42	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	5	0	0
T59	5486	0	0	0
T60	10246	0	0	0
T61	45544	0	0	0
T62	1695620	0	0	0
T63	31906	0	0	0
T64	159484	0	0	0
T65	412534	0	0	0
T66	58208	0	0	0
T69	14435	0	0	0
T70	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	5	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5618	0	0
T8	169928	1406	0	0
T9	0	1459	0	0
T10	0	696	0	0
T24	1086408	0	0	0
T26	755352	0	0	0
T28	66856	0	0	0
T30	974336	0	0	0
T32	0	1355	0	0
T33	0	702	0	0
T34	40236	0	0	0
T35	133816	0	0	0
T36	694632	0	0	0
T37	184124	0	0	0
T38	1303104	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4658	0	0
T8	169928	1166	0	0
T9	0	1219	0	0
T10	0	576	0	0
T24	1086408	0	0	0
T26	755352	0	0	0
T28	66856	0	0	0
T30	974336	0	0	0
T32	0	1115	0	0
T33	0	582	0	0
T34	40236	0	0	0
T35	133816	0	0	0
T36	694632	0	0	0
T37	184124	0	0	0
T38	1303104	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3579856	3579620	0	0
T2	715200	715164	0	0
T3	3031552	3031252	0	0
T4	402968	402936	0	0
T5	1663840	1663816	0	0
T15	185860	185484	0	0
T16	186188	185904	0	0
T17	13148	12824	0	0
T18	148452	148120	0	0
T19	83924	83600	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T15

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T17
1	0	1	Covered	T16,T21,T86
1	1	0	Covered	T18,T19,T31
1	1	1	Covered	T21,T31,T26

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T21,T31,T26
0	1	Covered	T21,T22,T23
1	0	Covered	T27,T43,T45

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T21,T31,T26
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T27,T43,T45

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T21,T31,T26
1	0	Not Covered
1	1	Covered	T21,T22,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T15,T17
1	Covered	T3,T16,T18

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T17,T21

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T11,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T16
1	Covered	T15,T21,T29

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T15,T17

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T16

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T15,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T15,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T8,T9,T10
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T15
Phase1St	193	Covered	T2,T3,T15
Phase2St	210	Covered	T2,T3,T15
Phase3St	228	Covered	T2,T3,T15
TerminalSt	244	Covered	T2,T3,T15
TimeoutSt	154	Covered	T21,T31,T26

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T8,T9,T10
IdleSt->Phase0St	147	Covered	T2,T3,T15
IdleSt->TimeoutSt	154	Covered	T21,T31,T26
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T27,T78
Phase0St->Phase1St	193	Covered	T2,T3,T15
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T87,T79,T88
Phase1St->Phase2St	210	Covered	T2,T3,T15
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14,T30,T45
Phase2St->Phase3St	228	Covered	T2,T3,T15
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T2,T27,T89
Phase3St->TerminalSt	244	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T21,T29
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T31,T26,T23
TimeoutSt->Phase0St	167	Covered	T21,T22,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T31,T26
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T21,T22,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T21,T31,T26
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T31,T26,T23
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T27,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T87,T79,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T30,T45
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T2,T27,T89
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T29,T22
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658350810	195	0	0
CheckAccumTrig0_A	658350810	518	0	0
CheckAccumTrig1_A	658350810	23	0	0
CheckClr_A	658350810	243	0	0
CheckEn_A	658166328	251142955	0	0
CheckPhase0_A	658350810	578	0	0
CheckPhase1_A	658350810	566	0	0
CheckPhase2_A	658350810	549	0	0
CheckPhase3_A	658350810	536	0	0
CheckTimeout0_A	658350810	1460	0	0
CheckTimeoutSt1_A	658350810	139792	0	0
CheckTimeoutSt2_A	658350810	1382	0	0
CheckTimeoutStTrig_A	658350810	54	0	0
ErrorStAllEscAsserted_A	658350810	1411	0	0
ErrorStIsTerminal_A	658350810	1171	0	0
u_state_regs_A	658350810	658181139	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	195	0	0
T8	42482	55	0	0
T9	0	46	0	0
T10	0	29	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	46	0	0
T33	0	19	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	518	0	0
T2	178800	3	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	1	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	23	0	0
T27	46214	1	0	0
T42	683555	0	0	0
T43	364916	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	4	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T61	22772	0	0	0
T62	847810	0	0	0
T63	15953	0	0	0
T64	79742	0	0	0
T65	206267	0	0	0
T66	29104	0	0	0
T67	4154	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	243	0	0
T2	178800	2	0	0
T3	757888	0	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T14	0	1	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T22	0	1	0	0
T23	0	1	0	0
T24	0	1	0	0
T27	0	3	0	0
T29	0	1	0	0
T30	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166328	251142955	0	0
T1	894964	894904	0	0
T2	178800	6450	0	0
T3	757888	1640	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	16279	0	0
T16	46547	3633	0	0
T17	3287	586	0	0
T18	37113	15340	0	0
T19	20981	20899	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	578	0	0
T2	178800	3	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	1	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	2	0	0
T41	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	566	0	0
T2	178800	3	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	1	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	2	0	0
T41	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	549	0	0
T2	178800	3	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	1	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	2	0	0
T41	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	536	0	0
T2	178800	2	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	1	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	2	0	0
T41	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1460	0	0
T6	301262	0	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T21	282743	1	0	0
T22	0	2	0	0
T23	0	4	0	0
T26	0	1	0	0
T27	0	1	0	0
T31	40103	2	0	0
T39	70682	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T69	14435	0	0	0
T70	0	2	0	0
T71	0	9	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	139792	0	0
T6	301262	0	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T21	282743	29	0	0
T22	0	178	0	0
T23	0	567	0	0
T26	0	69	0	0
T31	40103	340	0	0
T39	70682	0	0	0
T42	0	10	0	0
T43	0	252	0	0
T69	14435	0	0	0
T70	0	605	0	0
T71	0	933	0	0
T72	0	167	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1382	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T23	0	3	0	0
T26	0	1	0	0
T31	40103	2	0	0
T39	70682	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T69	14435	0	0	0
T70	0	1	0	0
T71	0	8	0	0
T73	0	1	0	0
T74	0	255	0	0
T75	0	9	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	54	0	0
T6	301262	0	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T21	282743	1	0	0
T22	0	2	0	0
T23	0	1	0	0
T31	40103	0	0	0
T39	70682	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T69	14435	0	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T77	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1411	0	0
T8	42482	329	0	0
T9	0	375	0	0
T10	0	191	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	342	0	0
T33	0	174	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1171	0	0
T8	42482	269	0	0
T9	0	315	0	0
T10	0	161	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	282	0	0
T33	0	144	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	658181139	0	0
T1	894964	894905	0	0
T2	178800	178791	0	0
T3	757888	757813	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	46371	0	0
T16	46547	46476	0	0
T17	3287	3206	0	0
T18	37113	37030	0	0
T19	20981	20900	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T2,T3,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T15,T4

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T17
1	0	1	Covered	T2,T5,T21
1	1	0	Covered	T3,T21,T26
1	1	1	Covered	T3,T19,T31

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T19,T31
0	1	Covered	T23,T70,T73
1	0	Covered	T3,T24,T44

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T19,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T24,T44

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T31
1	0	Not Covered
1	1	Covered	T23,T70,T73

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T18
1	Covered	T2,T3,T41

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T6,T39,T26

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T18
1	Covered	T15,T4,T14

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T18,T21,T40

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T4,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T18,T6

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T15,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T8,T9,T10
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T15
Phase1St	193	Covered	T2,T3,T15
Phase2St	210	Covered	T2,T3,T15
Phase3St	228	Covered	T2,T3,T15
TerminalSt	244	Covered	T2,T3,T15
TimeoutSt	154	Covered	T3,T19,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T8,T9,T10
IdleSt->Phase0St	147	Covered	T2,T15,T4
IdleSt->TimeoutSt	154	Covered	T3,T19,T31
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T27,T70
Phase0St->Phase1St	193	Covered	T2,T3,T15
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T24,T78,T91
Phase1St->Phase2St	210	Covered	T2,T3,T15
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T54,T92,T93
Phase2St->Phase3St	228	Covered	T2,T3,T15
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T78,T94,T20
Phase3St->TerminalSt	244	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T3,T39
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T19,T31,T69
TimeoutSt->Phase0St	167	Covered	T3,T24,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T15,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T24,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T19,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T19,T31,T69
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T27,T70
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T78,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T92,T93,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T78,T94,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T15,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T39
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658350810	275	0	0
CheckAccumTrig0_A	658350810	485	0	0
CheckAccumTrig1_A	658350810	17	0	0
CheckClr_A	658350810	223	0	0
CheckEn_A	658166328	307998705	0	0
CheckPhase0_A	658350810	558	0	0
CheckPhase1_A	658350810	539	0	0
CheckPhase2_A	658350810	529	0	0
CheckPhase3_A	658350810	524	0	0
CheckTimeout0_A	658350810	1422	0	0
CheckTimeoutSt1_A	658350810	170272	0	0
CheckTimeoutSt2_A	658350810	1344	0	0
CheckTimeoutStTrig_A	658350810	61	0	0
ErrorStAllEscAsserted_A	658350810	1437	0	0
ErrorStIsTerminal_A	658350810	1197	0	0
u_state_regs_A	658350810	658181139	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	275	0	0
T8	42482	65	0	0
T9	0	57	0	0
T10	0	50	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	66	0	0
T33	0	37	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	485	0	0
T2	178800	2	0	0
T3	757888	0	0	0
T4	100742	1	0	0
T5	415960	0	0	0
T6	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	17	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T6	301262	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T24	0	1	0	0
T25	0	1	0	0
T44	0	1	0	0
T49	0	1	0	0
T80	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T99	0	2	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	223	0	0
T2	178800	1	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T23	0	3	0	0
T24	0	2	0	0
T27	0	2	0	0
T29	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T39	0	1	0	0
T60	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166328	307998705	0	0
T1	894964	894904	0	0
T2	178800	24889	0	0
T3	757888	755090	0	0
T4	100742	800	0	0
T5	415960	2035	0	0
T15	46465	9310	0	0
T16	46547	46475	0	0
T17	3287	590	0	0
T18	37113	6583	0	0
T19	20981	2731	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	558	0	0
T2	178800	2	0	0
T3	757888	1	0	0
T4	100742	1	0	0
T5	415960	0	0	0
T6	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	539	0	0
T2	178800	2	0	0
T3	757888	1	0	0
T4	100742	1	0	0
T5	415960	0	0	0
T6	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	529	0	0
T2	178800	2	0	0
T3	757888	1	0	0
T4	100742	1	0	0
T5	415960	0	0	0
T6	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	524	0	0
T2	178800	2	0	0
T3	757888	1	0	0
T4	100742	1	0	0
T5	415960	0	0	0
T6	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T39	0	1	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1422	0	0
T3	757888	1	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T6	301262	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	4	0	0
T21	282743	0	0	0
T23	0	352	0	0
T24	0	1	0	0
T26	0	2	0	0
T31	0	4	0	0
T42	0	10	0	0
T61	0	2	0	0
T68	0	2	0	0
T69	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	170272	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T6	301262	0	0	0
T15	46465	0	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	847	0	0
T21	282743	0	0	0
T23	0	55578	0	0
T26	0	127	0	0
T31	0	656	0	0
T42	0	1978	0	0
T43	0	245	0	0
T61	0	124	0	0
T68	0	263	0	0
T69	0	333	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1344	0	0
T6	301262	0	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T19	20981	4	0	0
T21	282743	0	0	0
T23	0	348	0	0
T26	0	2	0	0
T31	40103	4	0	0
T39	70682	0	0	0
T42	0	10	0	0
T43	0	3	0	0
T61	0	2	0	0
T68	0	2	0	0
T69	0	3	0	0
T73	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	61	0	0
T23	541623	4	0	0
T27	46214	0	0	0
T49	0	2	0	0
T59	2743	0	0	0
T60	5123	0	0	0
T61	22772	0	0	0
T62	847810	0	0	0
T63	15953	0	0	0
T64	79742	0	0	0
T65	206267	0	0	0
T66	29104	0	0	0
T70	0	2	0	0
T73	0	1	0	0
T77	0	1	0	0
T78	0	2	0	0
T81	0	1	0	0
T82	0	1	0	0
T84	0	1	0	0
T85	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1437	0	0
T8	42482	368	0	0
T9	0	361	0	0
T10	0	191	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	341	0	0
T33	0	176	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1197	0	0
T8	42482	308	0	0
T9	0	301	0	0
T10	0	161	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	281	0	0
T33	0	146	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	658181139	0	0
T1	894964	894905	0	0
T2	178800	178791	0	0
T3	757888	757813	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	46371	0	0
T16	46547	46476	0	0
T17	3287	3206	0	0
T18	37113	37030	0	0
T19	20981	20900	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T15

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T15

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T15,T18
1	0	1	Covered	T2,T3,T16
1	1	0	Covered	T3,T18,T19
1	1	1	Covered	T18,T21,T31

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T18,T21,T31
0	1	Covered	T18,T22,T23
1	0	Covered	T100,T44,T74

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T18,T21,T31
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T100,T44,T74

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T21,T31
1	0	Not Covered
1	1	Covered	T18,T22,T23

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T3,T15,T14

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T3,T15

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T2,T23,T27

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T15
1	Covered	T16,T11,T24

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T15,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T3,T16,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T15

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T8,T9,T10
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T2,T3,T15
Phase1St	193	Covered	T2,T3,T15
Phase2St	210	Covered	T2,T3,T15
Phase3St	228	Covered	T2,T3,T15
TerminalSt	244	Covered	T2,T3,T15
TimeoutSt	154	Covered	T18,T21,T31

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T8,T9,T10
IdleSt->Phase0St	147	Covered	T2,T3,T15
IdleSt->TimeoutSt	154	Covered	T18,T21,T31
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T24,T101,T49
Phase0St->Phase1St	193	Covered	T2,T3,T15
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T102,T103,T104
Phase1St->Phase2St	210	Covered	T2,T3,T15
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T79,T98,T105
Phase2St->Phase3St	228	Covered	T2,T3,T15
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T15,T23,T101
Phase3St->TerminalSt	244	Covered	T2,T3,T15
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T2,T3,T11
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T21,T31,T69
TimeoutSt->Phase0St	167	Covered	T18,T22,T23

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T15
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T18,T21,T31
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T18,T22,T23
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T18,T21,T31
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T21,T31,T69
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T101,T49
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T102,T103,T104
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T15
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T79,T98,T105
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T15
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T23,T101
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T3,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T15
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658350810	313	0	0
CheckAccumTrig0_A	658350810	495	0	0
CheckAccumTrig1_A	658350810	26	0	0
CheckClr_A	658350810	237	0	0
CheckEn_A	658166328	302993069	0	0
CheckPhase0_A	658350810	593	0	0
CheckPhase1_A	658350810	580	0	0
CheckPhase2_A	658350810	572	0	0
CheckPhase3_A	658350810	558	0	0
CheckTimeout0_A	658350810	883	0	0
CheckTimeoutSt1_A	658350810	106676	0	0
CheckTimeoutSt2_A	658350810	772	0	0
CheckTimeoutStTrig_A	658350810	83	0	0
ErrorStAllEscAsserted_A	658350810	1421	0	0
ErrorStIsTerminal_A	658350810	1181	0	0
u_state_regs_A	658350810	658181139	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	313	0	0
T8	42482	80	0	0
T9	0	104	0	0
T10	0	34	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	55	0	0
T33	0	40	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	495	0	0
T2	178800	2	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	46465	2	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T24	0	4	0	0
T29	0	1	0	0
T36	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	26	0	0
T44	0	1	0	0
T57	0	1	0	0
T71	219047	0	0	0
T72	78297	0	0	0
T73	336993	0	0	0
T74	0	1	0	0
T76	5642	0	0	0
T79	0	1	0	0
T84	0	1	0	0
T100	125850	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	51397	0	0	0
T110	39719	0	0	0
T111	386886	0	0	0
T112	30889	0	0	0
T113	4659	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	237	0	0
T2	178800	1	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	1	0	0
T15	46465	1	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T27	0	2	0	0
T42	0	1	0	0
T61	0	2	0	0
T70	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166328	302993069	0	0
T1	894964	2861	0	0
T2	178800	10794	0	0
T3	757888	753612	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	3591	0	0
T16	46547	14601	0	0
T17	3287	3205	0	0
T18	37113	25357	0	0
T19	20981	20899	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	593	0	0
T2	178800	2	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	46465	2	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T24	0	3	0	0
T29	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	580	0	0
T2	178800	2	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	46465	2	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T24	0	3	0	0
T29	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	572	0	0
T2	178800	2	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	46465	2	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T24	0	3	0	0
T29	0	1	0	0
T36	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	558	0	0
T2	178800	2	0	0
T3	757888	2	0	0
T4	100742	0	0	0
T5	415960	0	0	0
T11	0	2	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T24	0	3	0	0
T29	0	1	0	0
T36	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	883	0	0
T6	301262	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T22	0	1	0	0
T23	0	4	0	0
T24	0	1	0	0
T26	0	23	0	0
T31	40103	1	0	0
T39	70682	0	0	0
T42	0	2	0	0
T66	0	9	0	0
T69	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	106676	0	0
T6	301262	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T18	37113	605	0	0
T19	20981	0	0	0
T21	282743	143	0	0
T22	0	288	0	0
T23	0	521	0	0
T24	0	85	0	0
T26	0	889	0	0
T31	40103	173	0	0
T39	70682	0	0	0
T42	0	84	0	0
T66	0	545	0	0
T69	0	153	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	772	0	0
T6	301262	0	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T21	282743	1	0	0
T23	0	2	0	0
T24	0	1	0	0
T26	0	23	0	0
T31	40103	1	0	0
T39	70682	0	0	0
T43	0	1	0	0
T66	0	9	0	0
T69	14435	2	0	0
T73	0	6	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	83	0	0
T6	301262	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T22	0	1	0	0
T23	0	2	0	0
T31	40103	0	0	0
T39	70682	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	4	0	0
T73	0	2	0	0
T77	0	2	0	0
T78	0	5	0	0
T114	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1421	0	0
T8	42482	362	0	0
T9	0	393	0	0
T10	0	163	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	317	0	0
T33	0	186	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1181	0	0
T8	42482	302	0	0
T9	0	333	0	0
T10	0	133	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	257	0	0
T33	0	156	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	658181139	0	0
T1	894964	894905	0	0
T2	178800	178791	0	0
T3	757888	757813	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	46371	0	0
T16	46547	46476	0	0
T17	3287	3206	0	0
T18	37113	37030	0	0
T19	20981	20900	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	129	89	89	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	287	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
ALWAYS	300	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
80	1	1
129	1	1
130	1	1
131	1	1
132	1	1
133	1	1
134	1	1
135	1	1
136	1	1
137	1	1
139	1	1
143	1	1
144	1	1
146	1	1
147	1	1
148	1	1
149	1	1
152	1	1
153	1	1
154	1	1
			MISSING_ELSE
164	1	1
166	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
176	1	1
177	1	1
182	1	1
183	1	1
184	1	1
185	1	1
186	1	1
188	1	1
189	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
195	1	1
			MISSING_ELSE
199	1	1
200	1	1
201	1	1
202	1	1
203	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
			MISSING_ELSE
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
			MISSING_ELSE
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
			MISSING_ELSE
253	1	1
254	1	1
255	1	1
256	1	1
			MISSING_ELSE
263	1	1
264	1	1
278	1	1
279	1	1
280	1	1
			MISSING_ELSE
287	4	4
290	4	4
300	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T4,T16
1	1	Covered	T1,T2,T3

 LINE       61
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T15,T4,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T15,T4,T16

 LINE       146
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T15,T4,T16
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T20
1	1	1	Covered	T15,T4,T16

 LINE       152
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T31,T115
1	0	1	Covered	T15,T16,T5
1	1	0	Covered	T19,T21,T31
1	1	1	Covered	T31,T26,T24

 LINE       166
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T31,T26,T24
0	1	Covered	T23,T42,T76
1	0	Covered	T23,T27,T42

 LINE       166
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T31,T26,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T27,T42

 LINE       166
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T26,T24
1	0	Covered	T25
1	1	Covered	T23,T42,T76

 LINE       186
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T16,T5
1	Covered	T4,T14,T24

 LINE       203
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T16
1	Covered	T5,T18,T11

 LINE       220
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T16,T5
1	Covered	T15,T40,T115

 LINE       237
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T15,T4,T5
1	Covered	T16,T21,T11

 LINE       278
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       290
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T5,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T16,T18

 LINE       290
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T18,T21

 LINE       290
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T15,T4,T18

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	279	Covered	T8,T9,T10
IdleSt	176	Covered	T1,T2,T3
Phase0St	147	Covered	T15,T4,T16
Phase1St	193	Covered	T15,T4,T16
Phase2St	210	Covered	T15,T4,T16
Phase3St	228	Covered	T15,T4,T16
TerminalSt	244	Covered	T15,T4,T16
TimeoutSt	154	Covered	T31,T26,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	279	Covered	T8,T9,T10
IdleSt->Phase0St	147	Covered	T15,T4,T16
IdleSt->TimeoutSt	154	Covered	T31,T26,T24
Phase0St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	189	Covered	T26,T24,T71
Phase0St->Phase1St	193	Covered	T15,T4,T16
Phase1St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	206	Covered	T14,T28,T49
Phase1St->Phase2St	210	Covered	T15,T4,T16
Phase2St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	224	Covered	T14,T29,T116
Phase2St->Phase3St	228	Covered	T15,T4,T16
Phase3St->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	240	Covered	T29,T30,T23
Phase3St->TerminalSt	244	Covered	T15,T4,T16
TerminalSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	256	Covered	T4,T11,T40
TimeoutSt->FsmErrorSt	279	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	176	Covered	T31,T26,T24
TimeoutSt->Phase0St	167	Covered	T23,T42,T43

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	139	22	22	100.00
IF	278	2	2	100.00
IF	300	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	139	case (state_q)
-2-:	146	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	152	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	166	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	173	if (timeout_en_i)
-6-:	188	if (clr_i)
-7-:	192	if (cnt_ge)
-8-:	205	if (clr_i)
-9-:	209	if (cnt_ge)
-10-:	223	if (clr_i)
-11-:	227	if (cnt_ge)
-12-:	239	if (clr_i)
-13-:	243	if (cnt_ge)
-14-:	255	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T15,T4,T16
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T31,T26,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T23,T27,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T31,T26,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T31,T26,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T26,T24,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T15,T4,T16
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T15,T4,T16
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T14,T28,T49
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T15,T4,T16
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T15,T4,T16
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T14,T29,T116
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T15,T4,T16
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T15,T4,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T30,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T15,T4,T16
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T15,T4,T16
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T11,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T15,T4,T16
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	278	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	658350810	282	0	0
CheckAccumTrig0_A	658350810	839	0	0
CheckAccumTrig1_A	658350810	34	0	0
CheckClr_A	658350810	400	0	0
CheckEn_A	658166328	252083999	0	0
CheckPhase0_A	658350810	890	0	0
CheckPhase1_A	658350810	871	0	0
CheckPhase2_A	658350810	846	0	0
CheckPhase3_A	658350810	822	0	0
CheckTimeout0_A	658350810	1446	0	0
CheckTimeoutSt1_A	658350810	141353	0	0
CheckTimeoutSt2_A	658350810	1367	0	0
CheckTimeoutStTrig_A	658350810	43	0	0
ErrorStAllEscAsserted_A	658350810	1349	0	0
ErrorStIsTerminal_A	658350810	1109	0	0
u_state_regs_A	658350810	658181139	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	282	0	0
T8	42482	96	0	0
T9	0	62	0	0
T10	0	19	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	62	0	0
T33	0	43	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	839	0	0
T4	100742	3	0	0
T5	415960	1	0	0
T6	301262	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	0	2	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T31	40103	0	0	0
T40	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	34	0	0
T23	541623	1	0	0
T27	46214	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T59	2743	0	0	0
T60	5123	0	0	0
T61	22772	0	0	0
T62	847810	0	0	0
T63	15953	0	0	0
T64	79742	0	0	0
T65	206267	0	0	0
T66	29104	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	400	0	0
T4	100742	2	0	0
T5	415960	0	0	0
T6	301262	0	0	0
T11	0	1	0	0
T14	0	2	0	0
T16	46547	0	0	0
T17	3287	0	0	0
T18	37113	0	0	0
T19	20981	0	0	0
T21	282743	0	0	0
T24	0	2	0	0
T26	0	5	0	0
T28	0	4	0	0
T29	0	10	0	0
T30	0	1	0	0
T31	40103	0	0	0
T39	70682	0	0	0
T40	0	1	0	0
T41	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658166328	252083999	0	0
T1	894964	894904	0	0
T2	178800	178791	0	0
T3	757888	757812	0	0
T4	100742	2862	0	0
T5	415960	2000	0	0
T15	46465	3524	0	0
T16	46547	2671	0	0
T17	3287	582	0	0
T18	37113	2519	0	0
T19	20981	20899	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	890	0	0
T4	100742	3	0	0
T5	415960	1	0	0
T6	301262	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	0	2	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T31	40103	0	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	871	0	0
T4	100742	3	0	0
T5	415960	1	0	0
T6	301262	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T31	40103	0	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	846	0	0
T4	100742	3	0	0
T5	415960	1	0	0
T6	301262	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T31	40103	0	0	0
T40	0	1	0	0
T41	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	822	0	0
T4	100742	3	0	0
T5	415960	1	0	0
T6	301262	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T15	46465	1	0	0
T16	46547	1	0	0
T17	3287	0	0	0
T18	37113	1	0	0
T19	20981	0	0	0
T21	282743	1	0	0
T31	40103	0	0	0
T40	0	1	0	0
T41	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1446	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T23	0	15	0	0
T24	0	1	0	0
T26	0	3	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	40103	1	0	0
T39	70682	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T42	0	3	0	0
T43	0	4	0	0
T64	0	1	0	0
T66	0	7	0	0
T69	14435	0	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	141353	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T23	0	3391	0	0
T24	0	75	0	0
T26	0	168	0	0
T27	0	123	0	0
T30	0	42	0	0
T31	40103	164	0	0
T39	70682	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T42	0	274	0	0
T43	0	132	0	0
T64	0	121	0	0
T66	0	392	0	0
T69	14435	0	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1367	0	0
T7	752020	0	0	0
T11	438864	0	0	0
T12	113847	0	0	0
T13	102187	0	0	0
T14	445653	0	0	0
T23	0	11	0	0
T24	0	1	0	0
T26	0	3	0	0
T27	0	3	0	0
T30	0	1	0	0
T31	40103	1	0	0
T39	70682	0	0	0
T40	150560	0	0	0
T41	510653	0	0	0
T42	0	1	0	0
T43	0	3	0	0
T64	0	1	0	0
T66	0	7	0	0
T69	14435	0	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	43	0	0
T23	541623	3	0	0
T27	46214	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T49	0	3	0	0
T59	2743	0	0	0
T60	5123	0	0	0
T61	22772	0	0	0
T62	847810	0	0	0
T63	15953	0	0	0
T64	79742	0	0	0
T65	206267	0	0	0
T66	29104	0	0	0
T73	0	3	0	0
T76	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1349	0	0
T8	42482	347	0	0
T9	0	330	0	0
T10	0	151	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	355	0	0
T33	0	166	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	1109	0	0
T8	42482	287	0	0
T9	0	270	0	0
T10	0	121	0	0
T24	271602	0	0	0
T26	188838	0	0	0
T28	16714	0	0	0
T30	243584	0	0	0
T32	0	295	0	0
T33	0	136	0	0
T34	10059	0	0	0
T35	33454	0	0	0
T36	173658	0	0	0
T37	46031	0	0	0
T38	325776	0	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	658350810	658181139	0	0
T1	894964	894905	0	0
T2	178800	178791	0	0
T3	757888	757813	0	0
T4	100742	100734	0	0
T5	415960	415954	0	0
T15	46465	46371	0	0
T16	46547	46476	0	0
T17	3287	3206	0	0
T18	37113	37030	0	0
T19	20981	20900	0	0