Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	56572	1			T21	572		T15	1515		T9	13
class_i[0x1]	65610	1			T20	57		T14	3734		T15	6386
class_i[0x2]	66092	1			T2	7		T4	5		T20	12
class_i[0x3]	50260	1			T20	9		T13	1		T15	2029

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	60265	1			T2	2		T4	1		T20	24
alert[0x1]	63479	1			T2	3		T20	14		T21	302
alert[0x2]	56064	1			T2	1		T4	2		T20	23
alert[0x3]	58726	1			T2	1		T4	2		T20	17

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

238260

1

T20

78

T21

572

T13

3130

esc_ping_fail

274

1

T2

7

T4

5

T9

12

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	60184	1			T20	24		T21	4		T13	782
esc_integrity_fail	alert[0x1]	63407	1			T20	14		T21	302		T13	786
esc_integrity_fail	alert[0x2]	55998	1			T20	23		T21	7		T13	768
esc_integrity_fail	alert[0x3]	58671	1			T20	17		T21	259		T13	794
esc_ping_fail	alert[0x0]	81	1			T2	2		T4	1		T9	3
esc_ping_fail	alert[0x1]	72	1			T2	3		T9	3		T47	2
esc_ping_fail	alert[0x2]	66	1			T2	1		T4	2		T9	4
esc_ping_fail	alert[0x3]	55	1			T2	1		T4	2		T9	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	56506	1			T21	572		T15	1515		T9	2
esc_integrity_fail	class_i[0x1]	65551	1			T20	57		T14	3734		T15	6386
esc_integrity_fail	class_i[0x2]	66018	1			T20	12		T13	3129		T15	4444
esc_integrity_fail	class_i[0x3]	50185	1			T20	9		T13	1		T15	2029
esc_ping_fail	class_i[0x0]	66	1			T9	11		T67	1		T69	7
esc_ping_fail	class_i[0x1]	59	1			T9	1		T105	1		T299	2
esc_ping_fail	class_i[0x2]	74	1			T2	7		T4	5		T67	7
esc_ping_fail	class_i[0x3]	75	1			T47	7		T300	3		T105	1