Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	667717896	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	667717896	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	667717896	667542665	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	667717896	667542665	0	0
tb.dut.EdnKnownO_A	0	0	667717896	667542665	0	0
tb.dut.EscPKnownO_A	0	0	667717896	667542665	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	667717896	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	667717896	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	667717896	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	667717896	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	667717896	80	0	0
tb.dut.IrqAKnownO_A	0	0	667717896	667542665	0	0
tb.dut.IrqBKnownO_A	0	0	667717896	667542665	0	0
tb.dut.IrqCKnownO_A	0	0	667717896	667542665	0	0
tb.dut.IrqDKnownO_A	0	0	667717896	667542665	0	0
tb.dut.TlAReadyKnownO_A	0	0	667717896	667542665	0	0
tb.dut.TlDValidKnownO_A	0	0	667717896	667542665	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	696061027	3489193	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	696061027	15368	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	696061027	15714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	696061027	16460	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	696061027	16269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	696061027	14859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	696061027	15217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	696061027	14581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	696061027	14403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	696061027	16996	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	696061027	15934	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	696061027	14308	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	696061027	15420	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	696061027	17586	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	696061027	17942	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	696061027	16517	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	696061027	16407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	696061027	17814	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	696061027	17260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	696061027	16955	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	696061027	14513	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	696061027	15823	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	696061027	16993	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	696061027	14712	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	696061027	15610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	696061027	15140	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	696061027	15112	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	696061027	17702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	696061027	14506	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	696061027	17572	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	696061027	17633	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	696061027	16121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	696061027	16278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	696061027	16783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	696061027	14714	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	696061027	14370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	696061027	15711	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	696061027	15992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	696061027	14227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	696061027	16334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	696061027	16492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	696061027	15408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	696061027	16769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	696061027	14726	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	696061027	16795	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	696061027	14657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	696061027	17983	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	696061027	17238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	696061027	16128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	696061027	16764	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	696061027	16760	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	696061027	17707	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	696061027	16491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	696061027	16078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	696061027	14787	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	696061027	14663	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	696061027	17284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	696061027	15159	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	696061027	16298	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	696061027	15859	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	696061027	14584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	696061027	15910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	696061027	14332	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	696061027	14995	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	696061027	17361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	696061027	16606	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	696061027	16596	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	696061027	14940	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	696061027	14537	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	696061027	14324	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	696061027	29174	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	696061027	14590	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	696061027	15458	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	696061027	17785	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	696061027	18921	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	696061027	14430	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	696061027	16806	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	696061027	15787	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	696061027	16714	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	667717896	8082	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	667717896	208982	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	667717896	328244904	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	667717896	214	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	667717896	886	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	667717896	45	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	667717896	463	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	667564288	253922854	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	667717896	987	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	667717896	963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	667717896	939	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	667717896	913	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	667717896	1246	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	667717896	141487	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	667717896	1127	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	667717896	71	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667717896	1403	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	667717896	1163	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	667717896	667542665	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	667717896	933	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	667717896	209621	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	667717896	367731881	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	667717896	246	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	667717896	508	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	667717896	30	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	667717896	249	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	667564288	293861305	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	667717896	590	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	667717896	576	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	667717896	561	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	667717896	554	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	667717896	1489	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	667717896	197726	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	667717896	1396	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	667717896	58	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667717896	1496	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	667717896	1256	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	667717896	667542665	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	667717896	2242	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	667717896	187891	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	667717896	417704770	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	667717896	248	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	667717896	490	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	667717896	34	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	667717896	225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	667564288	336781323	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	667717896	582	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	667717896	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	667717896	560	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	667717896	554	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	667717896	866	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	667717896	103934	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	667717896	762	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	667717896	67	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667717896	1483	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	667717896	1243	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	667717896	667542665	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	667717896	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	667717896	3012	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	667717896	185119	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	667717896	397530296	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	667717896	310	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	667717896	544	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	667717896	18	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	667717896	252	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	667564288	306399780	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	667717896	617	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	667717896	610	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	667717896	601	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	667717896	594	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	667717896	732	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	667717896	94223	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	667717896	647	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	667717896	63	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	667717896	1435	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	667717896	1195	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	667717896	667542665	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	696061027	135797510	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	696061027	695348259	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	696061027	695348259	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	696061027	182909597	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	696061027	695348259	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	696061027	695348259	0	0
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