Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	187	1			T5	1		T21	1		T14	1
index[0x1]	196	1			T15	2		T48	1		T32	1
index[0x2]	193	1			T1	2		T15	4		T8	2
index[0x3]	149	1			T3	1		T20	1		T15	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	275	1			T20	1		T15	3		T8	2
lens_less_than_1000[1]	136	1			T14	1		T15	1		T47	1
lens_less_than_1000[2]	91	1			T5	1		T21	1		T15	2
lens_less_than_1000[3]	68	1			T3	1		T15	1		T32	1
lens_less_than_1000[4]	58	1			T32	1		T222	1		T50	1
lens_less_than_1000[5]	34	1			T15	1		T221	1		T86	1
lens_less_than_1000[6]	23	1			T32	1		T30	1		T23	2
lens_less_than_1000[7]	15	1			T32	1		T55	1		T262	1
lens_less_than_1000[8]	13	1			T50	2		T27	1		T263	1
lens_less_than_1000[9]	4	1			T55	1		T43	1		T264	1
len_2	8	1			T1	2		T96	1		T233	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9]]	0	1	1
[index[0x3]]	[len_2]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	68	1			T30	1		T23	1		T70	1
index[0x0]	lens_less_than_1000[1]	38	1			T14	1		T47	1		T32	2
index[0x0]	lens_less_than_1000[2]	33	1			T5	1		T21	1		T23	1
index[0x0]	lens_less_than_1000[3]	15	1			T15	1		T81	1		T100	1
index[0x0]	lens_less_than_1000[4]	19	1			T32	1		T222	1		T86	1
index[0x0]	lens_less_than_1000[5]	4	1			T265	1		T266	1		T267	1
index[0x0]	lens_less_than_1000[6]	3	1			T23	1		T76	1		T268	1
index[0x0]	lens_less_than_1000[7]	3	1			T55	1		T269	1		T270	1
index[0x0]	lens_less_than_1000[8]	1	1			T263	1		-	-		-	-
index[0x0]	lens_less_than_1000[9]	1	1			T271	1		-	-		-	-
index[0x0]	len_2	2	1			T233	1		T209	1		-	-
index[0x1]	lens_less_than_1000[0]	78	1			T32	1		T30	1		T22	1
index[0x1]	lens_less_than_1000[1]	24	1			T22	1		T71	1		T272	1
index[0x1]	lens_less_than_1000[2]	21	1			T15	1		T48	1		T30	1
index[0x1]	lens_less_than_1000[3]	18	1			T22	1		T55	1		T257	1
index[0x1]	lens_less_than_1000[4]	15	1			T84	1		T55	1		T273	1
index[0x1]	lens_less_than_1000[5]	11	1			T15	1		T97	2		T274	1
index[0x1]	lens_less_than_1000[6]	13	1			T30	1		T23	1		T272	2
index[0x1]	lens_less_than_1000[7]	5	1			T262	1		T42	1		T247	2
index[0x1]	lens_less_than_1000[8]	7	1			T275	1		T276	3		T44	1
index[0x1]	len_2	4	1			T96	1		T209	1		T277	2
index[0x2]	lens_less_than_1000[0]	80	1			T15	2		T8	2		T30	4
index[0x2]	lens_less_than_1000[1]	48	1			T15	1		T22	4		T70	1
index[0x2]	lens_less_than_1000[2]	18	1			T15	1		T48	1		T278	1
index[0x2]	lens_less_than_1000[3]	17	1			T32	1		T86	1		T34	1
index[0x2]	lens_less_than_1000[4]	11	1			T50	1		T34	1		T98	1
index[0x2]	lens_less_than_1000[5]	7	1			T86	1		T246	1		T43	1
index[0x2]	lens_less_than_1000[6]	4	1			T32	1		T59	1		T242	1
index[0x2]	lens_less_than_1000[7]	1	1			T108	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	3	1			T50	1		T279	1		T280	1
index[0x2]	lens_less_than_1000[9]	2	1			T43	1		T264	1		-	-
index[0x2]	len_2	2	1			T1	2		-	-		-	-
index[0x3]	lens_less_than_1000[0]	49	1			T20	1		T15	1		T9	1
index[0x3]	lens_less_than_1000[1]	26	1			T22	1		T281	1		T282	1
index[0x3]	lens_less_than_1000[2]	19	1			T221	1		T105	1		T283	1
index[0x3]	lens_less_than_1000[3]	18	1			T3	1		T284	1		T84	1
index[0x3]	lens_less_than_1000[4]	13	1			T272	1		T55	1		T57	1
index[0x3]	lens_less_than_1000[5]	12	1			T221	1		T55	4		T285	1
index[0x3]	lens_less_than_1000[6]	3	1			T86	1		T59	1		T286	1
index[0x3]	lens_less_than_1000[7]	6	1			T32	1		T286	1		T233	1
index[0x3]	lens_less_than_1000[8]	2	1			T50	1		T27	1		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T55	1		-	-		-	-